Digital Systems Design Ch1 VHDL - VHDL Hardware Description Language

Digital Systems Design Chapter 1: VHDL
Prepared by: Mr. Araz Sabir Ameen

Assistant Lecturer (M.Sc. in Electronics and Communication)
2010--2011
Digital System Design
Prepared By: Mr. Araz Sabir Ameen

Chapter One VHDL Hardware Description Language
Design languages provide the means by which to describe the operation of both software programs and hardware. These descriptions, usually text based, are developed and stored as ASCII text files within the computer on which the descriptions are being developed. Design languages are of two types, software programming languages (SPL) and hardware description languages (HDL). At one time, designers were either software or hardware designers, or design teams were clearly distinguished by these separate roles
Digital Design
Design Language (ASCII text file inside Computer)
SPL Software Programming Language Needs CAD tool Needs Programmer The Program needs (P, C) to be executed Examples: C, C++, Assemply
HDL Hardware Description Language Needs CAD tool Needs Programmer The Program crates gates on (FPGA, CPLD) Examples: VHDL, Verilog HDL.
VHDL: In the 1980s rapid advances in integrated circuit technology leads to develop standard design practices for digital circuits. VHDL (Very high speed integrated circuit Hardware Description Language) VHDL was developed as a part of that effort. VHDL has become the industry standard language for describing digital circuits, largely because it is an official IEEE standard. The original standard for VHDL was adopted in 1987 and called IEEE 1076. A revised standard was adopted in 1993 and called IEEE 1164. VHDL is intended to serve three purposes: 1. Documentation: VHDL was originally used as a documentation language for describing the structure of complex digital circuits. As an official standard, VHDL provides a common way of documenting circuits designed by numerous designers. 2. Simulation: VHDL provide features for modeling the behavior of a digital circuit, which allowed its use as input to software program that were then used to simulate the circuits operation.
3. Hardware Synthesis: In the recent years, in addition to its use for documentation and simulation, VHDL has also become popular for use in design entry in CAD systems. The CAD tools are used to synthesize the VHDL code into a hardware implementation of the desired circuit. 1.1 Basic VHDL Language Elements. 1.1.1 Comments: Comments are preceded by two consecutive hyphens (--) and are terminated at the end of the line. Example: -- This is a comment
1.1.2 Identifiers: VHDL identifier syntax: A sequence of one or more uppercase letters, lowercase letters, digits, and the underscore. Upper and lowercase letters are treated the same (i.e., case insensitive). The first character must be a letter. The last character cannot be the underscore Two underscores cannot be together. Identifier values and numbers: 1. Individual logic signals 0, 1 2. Multiple logic signal 01110 1.1.3 Data Objects: There are three kinds of data objects: SIGNALs, VARIABLEs, and CONSTANTs. a) SIGNAL Data Objects: SIGNAL data objects represent logic signals on a wire in the circuit. A signal does not have memory; thus, if the source of the signal is removed, the signal will not have a value. There are three places in which SIGNALs can be declared in VHDL code: 1. ENTITY declaration. 2. Declarative part of ARCHITECTURE. 3. Declarative part of PACKAGE. General form of SIGNAL declaration: SIGNAL signal_name, signal_name, ... : type_name;
b) VARIABLE data objects: A VARIABLE; unlike SIGNAL; does not represent a signal on a wire in the circuit. VARIABLE data objects are sometimes used to hold results of computation and for index variables in the loops. VARIABLES can be declared only inside the declarative part of PROCESS. General form of VARIABLE declaration: VARIABLE variable_name, variable_name, . : type_name;
c) CONSTANT Data Objects: The CONSTANT data objects must be initialized with a value when declared and this value cannot be changed. CONSTANT can be declared only inside the declarative part of ARCHITECTURE. General form of CONSTANT declaration: CONSTANT constant_name: type_name:=constant value; Example: SIGNAL x: BIT; VARIABLE y: INTEGER; CONSTANT one: STD_LOGIC_VECTOR (3 DOWNTO 0):= "0001";
1.1.4 Data Types: a) BIT and BIT_VECTOR Data Type: The BIT and BIT_VECTOR types are predefined in VHDL standards IEEE1076 and IEEE1164, hence no need for LIBRARY statement. Objects of these types can only have the values 0 or 1. The BIT_VECTOR type is simply a vector of type BIT. A vector with all bits having the same value can be obtained using OTHERS. Example: SIGNAL x: BIT; SIGNAL y: BIT_VECTOR (5 DOWNTO 0); SIGNAL z: BIT_VECTOR (0 TO 4); . . . x <= '1'; y <= "000010"; z <= (OTHERS => '0'); -- same as "00000"
y y(5) y(4) y(3) y(2) y(1) y(0) z z(0) z(1) z(2) z(3) z(4)
Notes: 1. The syntax lower_index TO higher index is useful for a multi bit signal that is simply an array of bits. 2. The syntax higher_index DOWNTO lower_index is useful if the signal represents a binary number. b) STD_LOGIC and STD_LOGIC_VECTOR Data Type: The STD_LOGIC and STD_LOGIC_VECTOR types are not predefined, and so the following two library statements must be included in order to use these types. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; If objects of type STD_LOGIC_VECTOR are to be used as binary numbers in arithmetic manipulations, then either one of the following two USE statements must also be included: USE IEEE.STD_LOGIC_SIGNED.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
For signed number arithmetic. For signed number arithmetic.
The STD_LOGIC and STD_LOGIC_VECTOR types provide more values than the BIT type for modeling a real circuit more accurately. Objects of these types can have the following values: '0' = normal 0 L =weak 0 Useful for logic '1' = normal 1 'H' =weak 1 Circuits 'Z' =high impedance 'U' =uninitialized '_' = dont-care X = unknown 'W'=weak unknown STD_LOGIC and STD_LOGIC_VECTOR data objects are often used in logic expressions. A vector with all bits having the same value can be obtained using the OTHERS. Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; SIGNAL x: STD_LOGIC; SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); x <= 'Z'; y <= "0000001Z"; y <= (OTHERS => '0'); -- same as "00000000"
c) SIGNED and UNSIGNED Data Type: These types are used for arithmetic operation; they represent an array of STD_LOGIC signals. The purpose of SIGNED and UNSIGNED data types is to allow the user to indicate in the VHDL code what kind of number representation is being used. To use these types, the code must include the following statement: LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; The SIGNED is used with 2s complement representation. d) INTEGER Data Type: The predefined INTEGER type defines binary number objects for use with arithmetic operators. By default, an INTEGER signal uses 32 bits to represent a signed number. Integers using fewer bits can also be declared with the RANGE keyword. Example: SIGNAL x: INTEGER; SIGNAL y: INTEGER RANGE 64 to 63; This defines y as 7-bit binary number.
e) BOOLEAN Data Type: The predefined BOOLEAN type defines objects having the two values TRUE and FALSE. Example: SIGNAL x: BOOLEAN;
f) Enumeration Data Type: An enumeration type allows the user to specify the values that the data object can have. General form: TYPE identifier IS (value1, value2, ); Example: TYPE state IS (S1, S2, S3); SIGNAL y: state_machine; y <= S1;
g) ARRAY Data Type: The ARRAY type groups single data objects of the same type together into a onedimensional or multidimensional array. General form: TYPE identifier IS ARRAY (range) OF type; Example: TYPE byte IS ARRAY (7 DOWNTO 0) OF BIT; TYPE memory_type IS ARRAY (1 TO 128) OF byte; SIGNAL memory: memory_ type; . . . memory (3) <= "00101101";
h) SUBTYPE Data Type: A SUBTYPE is a subset of a type, that is, a type with a range constraint. Some standard subtypes include: - NATURAL (an integer in the range 0 to INTEGER'HIGH). - POSITIVE (an integer in the range 1 to INTEGER'HIGH). General form: SUBTYPE identifier IS type RANGE range; Example: SUBTYPE integer4 IS INTEGER RANGE 8 TO 7; SUBTYPE cell IS STD_LOGIC_VECTOR (3 DOWNTO 0); TYPE memarray IS ARRAY (0 TO 15) OF cell; 1.1.5 VHDL Operators: a) Logical Operators: Used with BIT, BIT_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR data types. Example: SIGNAL a, b, c, d, e: STD_LOGIC_VECTOR (1 T0 3); . . c <=NOT a; d(2) <= a(1) AND b(3); e <= a AND b;

Operator AND OR NOT NAND NOR XOR XNOR

Logical Operators Operation Example AND Y<= a AND b; OR Y<= a OR b; NOT Y<= NOT a; NAND Y<= a NAND b; NOR Y<= a NOR b; EX-OR Y<= a XOR b; EX-NOR Y<= a XNOR b;
b) Arithmetic Operators: Used with STD_LOGIC_VECTOR, SIGNED, UNSIGNED, INTEGER c <= -a; (c equals to the 2s complement of a). There are no synthesis restrictions regarding (Addition, Subtraction, and Multiplication). For Division, only power of two dividers is allowed. For Exponentiation, only static values of base and exponent are accepted. (y MOD x) returns the reminder of y/x. with the signal of x. (y REM x) returns the reminder of y/x with the signal y. (MOD, REM, ABS) operators are generally little or no synthesis support. Arithmetic Operators Operator + * / ** & MOD REM ABS Operation Addition Subtraction Multiplication(Integer or Floating Point) Division(Integer or Floating Point) Exponentiation Concatenation Modulus(Integer) Reminder(integer) Absolute Example y<= a +b; y<= a b; y<= a * b; y<= a / b; y<= a **2; y<= 001 & a& 11; y<= a MOD b; y<= a REM b; Y <= ABS a;
c) Relational Operator: Used to compare expressions. Result of comparison TRUE or FALSE. Compared expressions must be of the same type. Relational Operators Operation Example Equal IF (Y=10) THEN Not Equal IF (Y/=10) THEN Less Than IF (Y<10) THEN Less Than or Equal IF (Y<=10) THEN Greater Than IF (Y>10) THEN Greater Than or Equal IF (Y>=10) THEN
Operator = /= < <= > >=
d) Shift and Rotate Operators: General Form: x <= y shift operation z. x,y must be BIT_VECTOR type, z INTEGER Shift and Rotate Operators Operator Operation Example SLL Shift Left Logical Y<= "1001010" SLL 2; SRL Shift Right Logical Y<= "1001010" SRL 1; SLA Shift Left Arithmetic Y<= "1001010" SLA 2; SRA Shift Right Arithmetic Y<= "1001010" SRA 1; ROL Rotate Left Y<= "1001010" ROL 2; ROR Rotate Right Y<= "1001010" ROR 3; Example: ENTITY shiftoperations IS PORT(x : IN a, b, c, d, e, f : OUT END shiftoperations; ARCHITECTURE behavior OF shiftoperations IS BEGIN a <= x SLL 1; -- a = x2, x1, x0, 0 b <= x SRL 1; -- b = 0, x3, x2, x1 c <= x SLA 1; -- c = x2, x1, x0, x0 d <= x SRA 1; -- a = x3, x3, x2, x1 e <= x ROL 1; -- a = x2, x1, x0, x3 f <= x ROR 1; --a = x0, x3, x2, x1 END behavior; e) Assignment Operators: <= := => Used to assign a value to a SIGNAL. Used to assign values to VARIABLES, CONSTANT, or GENERIC Used to assign values to individual vector elements, or with OTHERS.
BIT_VECTOR (3 DOWNTO 0); BIT_VECTOR (3 DOWNTO 0));
Example: SIGNAL x: STD_LOGIC; VARIABLE y: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL w: STD_LOGIC_VECTOR (0 TO 7); . . x <= 1; y:= 0000; w<= 100000000; w<= (0 => 1, OTHERS=>0;)
1.1.6 VHDL Design Entity: A circuit or sub-circuit described with VHDL code is called a design entity or just entity. The figure below shows the general structure of an entity. It has three main parts:
Entity LIBRARY Declaration ENTITY Declaration ARCHITECTURE
The general structure of a VHDL design entity
a) LIBRARY declarations: Contains a list of all libraries to be used in the design. There are two types of Libraries: System Library: It is provide as part of the CAD system. User Library: It is created by the user. A special case of user library is represented by the file system directory where the VHDL source code file that declares a PACKAGE is stored. General form:
LIBRARY library_name ; USE library_name.package_name.all ;
Table1 identifies a number of key libraries and packages required for basic operations. The libraries and packages to be used by an ENTITY will appear immediately before the particular ENTITY declaration. Library Package STD_LOGIC_1164 Required for: Defines the standard for describing the interconnection data types used in the VHDL language, along with the STD_LOGIC and STD_LOGIC_VECTOR types.
IEEE
Functions to allow the use of STD_LOGIC_VECTOR types STD_LOGIC_UNSIGNED as if they were UNSIGNED types. STD_LOGIC_SIGNED Functions to allow the use of STD_LOGIC_VECTOR types as if they were SIGNED types.

Defines UNSIGNED and SIGNED types, conversion functions, and arithmetic/comparison operations for use with the UNSIGNED and SIGNED types. Arithmetic operations following the IEEE standard. For unsigned and signed arithmetic operations, this is the preferred package in many scenarios to using the STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED and STD_LOGIC_SIGNED packages. Predefined definitions for the types and functions of the VHDL language File I/O operations Current work library
STD_LOGIC_ARITH
IEEE NUEMERIC_STD
STANDARD STD TEXTIO WORK [set by user]
b) ENTITY declaration: Specifies the input and output pins of the circuit. The name of the entity can be any legal VHDL name (Identifier). The input and output signals are specified using the keyword PORT. Whether each port (pin) is an input, output, or bidirectional are specified by the mode of the port. The available modes are summarized in table2. General form: ENTITY entity_name IS PORT (signal_name, signal_name, signal_name, signal_name, END entity_name;
: mode : mode
type_name; type_name);
Table 2: The possible modes for signals that are entity ports
Mode IN OUT
Purpose Used for a signal that is an input to an entity. Used for signal that is an output from an entity. The value of the signal cannot be used inside the entity. This means that in an assignment statement, the signal can appear only to the left of the <= operator. Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement, the signal can be appear both on the left and right sides of the <= operator.
BUFFER
10
c) ARCHITECTURE: Provides the circuit details for an ENTITY. It has two main parts: the declarative region and architecture body. The declarative region appears preceding the BEGIN keyword. It can be used to declare signals, user defined data types, constants, components, and attributes. The functionality of the entity is specified in the architecture body, which follows the BEGIN keyword. This specification involves statements that define the logic function in the circuit. General form: ARCHITECTURE architecture_name OF entity_name IS [SIGNAL declarations] [CONSTANT declarations] [TYPE declarations] [COMPONENT declarations] [ATTRIBUTE declarations] BEGIN COMPONENT instantiation statements; CONCURRENT ASSIGNMENT statements; PROCESS statements; GENERATE statements; END architecture_name; Example1: Write a VHDL code for the following logic function: = 1 . 3 + 2 . 3 Solution: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY example1 IS PORT(x1, x2, x3 : IN STD_LOGIC; z : OUT STD_LOGIC); END example1; ARCHITECTURE behavior OF example1 IS SIGNAL p1, p2: STD_LOGIC; BEGIN p1<= x1 AND NOT x3; p2<= NOT x2 AND x3; z<= p1 OR p2; END behavior;
11
1.2 Concurrent SIGNAL Assignment Statements (Data Flow Model): Data flow model describes the transfer of data from input to output and between signals. Concurrent SIGNAL assignment statements used in the dataflow model are executed concurrently. The ordering of these statements does not affect the resulting output. 1.2.1 Simple SIGNAL Assignment Statement: The simple SIGNAL assignment statement assigns a value or the result of evaluating an expression to a signal. This statement is executed whenever a SIGNAL in its expression changes value. The expression can be any logical or arithmetical expressions. General form: signal <= expression; Example: y <= '1'; z <= y AND (NOT x); Example2: Write a VHDL code for a 4-to-1 Multiplexer using only simple SIGNAL assignment statement. Solution: To write a VHDL code using simple SIGNAL assignment statement, we must draw its logic diagram or write its logic expressions.
s1 s0 s1 x0 x0 x1 x1 f x2 x3 x2 x3 f s0
Logic diagram of 4-to-1 Multiplexer
Block diagram of 4-to-1 Multiplexer
12
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY example2 IS PORT( x : IN STD_LOGIC_VECTOR (0 TO 3); s :IN STD_LOGIC_VECTOR (1 DOWNTO); f : OUT STD_LOGIC); END example2; ARCHITECTURE behavior OF example2 IS SIGNAL p1, p2, p3, p4: STD_LOGIC; BEGIN p1<= x(0) AND NOT s(1) AND NOT s(0) ; p2<= x(1) AND NOT s(1) AND s(0) ; p3<= x(2) AND s(1) AND NOT s(0) ; p4<= x(3) AND s(1) AND s(0) ; f<= p1 OR p2 OR p3 OR p4; END behavior; 1.2.2 Conditional SIGNAL Assignment Statements: The conditional signal assignment statement selects one of several different values to assign to a SIGNAL based on different conditions. This statement is executed whenever a signal in any one of the value or condition changes. General form: signal_name <= expression WHEN logic expression ELSE expression WHEN logic expression ELSE . . . expression;
13
Example3: Write a VHDL code for 4-to-1 multiplexer using only conditional SIGNAL assignment statement. Solution: To write a VHDL code using conditional SIGNAL assignment statement, we must draw its truth table. s1 s0
s1 0 0 1 1 s0 0 1 0 1 f x0 x1 x2 x3 x0 x1 f x2 x3 Block diagram of 4-to-1 Multiplexer
Truth table of 4-to-1 Multiplexer
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY example3 IS PORT( x : IN STD_LOGIC_VECTOR (0 TO 3); s :IN STD_LOGIC_VECTOR (1 DOWNTO); f : OUT STD_LOGIC); END example3; ARCHITECTURE behavior OF example3 IS BEGIN f<= x(0) WHEN s=00 ELSE x(1) WHEN s=01 ELSE x(2) WHEN s=10 ELSE x(3); END behavior; 1.2.3 Selected SIGNAL Assignment Statements: It is used to set the value of a signal to one of several alternatives based on a selection criterion. All possible values of the condition input must be explicitly listed in the code. The word OTHERS provides an easy way to meet this requirement. OTHERS represent all possible values not already listed. General form:
14

WITH expression SELECT signal_name <= expression WHEN value, expression WHEN value, . . . expression WHEN OTHERS;
Example4: Write a VHDL code for 4-to-1 multiplexer using only selected SIGNAL assignment statement. Solution: To write a VHDL code using selected SIGNAL assignment statement, we must draw its truth table.
s1 s1 0 0 1 1 s0 0 1 0 1 f x0 x1 x2 x3 x0 x1 f x2 x3 Block diagram of 4-to-1 Multiplexer s0
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY example4 IS PORT( x : IN STD_LOGIC_VECTOR (0 TO 3); s :IN STD_LOGIC_VECTOR (1 DOWNTO); f : OUT STD_LOGIC); END example3; ARCHITECTURE behavior OF example3 IS BEGIN WITH s SELECT f<= x(0) WHEN 00, x(1) WHEN 01, x(2) WHEN 10, x(3) WHEN OTHERS; END behavior;
15
Home Work1: Write a VHDL code for full adder circuit using: 1. Only simple SIGNAL assignment statement. 2. Only conditional SIGNAL assignment statement. 3. Only Selected SIGNAL assignment statement. Home Work2: Write a VHDL code for a circuit that converts BCD code to excess-3 code using: 1. Only simple SIGNAL assignment statement. 2. Only conditional SIGNAL assignment statement. 3. Only Selected SIGNAL assignment statement. Home Work3: Write a VHDL code for the 4-bit binary adder using only simple SIGNAL assignment statements. 1.3 Structural Model Statements: The structural model allows the manual connection of several components together using signals. All components used must first be defined with their respective ENTITY and ARCHITECTURE sections, which can be in the same file or can be in separate files. 1.3.1 COMPONENTS: A VHDL code defined in one source code file can be used as a sub-circuit in another source code file. In VHDL jargon the sub-circuit is called a COMPONENT. a) COMPONENT Declaration: A sub-circuit must be declared using a COMPONENT declaration. This statement specifies the name of the sub-circuit and gives the names of its input and output ports. The COMPONENT declaration can appear either in the declarative region of an ARCHITECTURE or in PACKAGE declaration. General form COMPONENT component_name GENERIC ( parameter_name: integer: = default value ; parameter_name: Integer: = default value); PORT (signal_name, signal_name, : mode type_name; signal_name, signal_name, : mode type_name); END COMPONENT; b) COMPONENT Instantiation: Once a COMPONENT declaration is given, the COMPONENT can be instantiated as a subcircuit. This done using COMPONENT instantiation statement. The signal names following PORT MAP keyword can be written in two ways:
16
1. In name association, the order of the signal listed after PORT MAP keyword does not have to be the same as the order of the ports in the corresponding COMPONENT declaration. Each formal name is the name of a port in the sub-circuit. Each actual name is the name of a signal in the code that instantiate the sub-circuit. instance_name : component_name PORT MAP ( formal_name => actual_name, formal_name=> actual_name , ........) ; 2. In positional association, the signal names following the PORT MAP keyword are given in the same order as in the COMPONENT declaration, and then the formal name is not needed. Instance_name : component_name PORT MAP (actual_name, actual_name , ...........) ; Example5: Write a VHDL code for 4-bit binary adder. Use the full adder as a sub-circuit in your code. Solution: 1) We must write a VHDL code for the sub-circuit (i.e. full adder).
x y cin
x y cin
Block diagram of full adder circuit Logic diagram of full adder circuit
Full Adder
s cout
cout
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END fulladder; ARCHITECTURE behavior OF fulladder IS BEGIN s<= x XOR y XOR cin; cout<= (x AND y) OR (x AND cin) OR (y AND cin); END behavior;
17

b(0)
y
2) Now, we can write the VHDL code for the 4-bit binary adder. b(3) a(3) b(2) a(2) b(1) a(1)
y cout F.A3 s x cin y x cin y x cin
a(0)
x cin
c3
cout F.A2 s
c2
cout F.A1 s
c1
cout F.A0 s
cin
s(4)
s(3)
s(2)
s(1)
s(0)
Block diagram of 4-bit binary adder
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY adder4 IS PORT (a, b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); cin :IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)); END adder4; ARCHITECTURE behavior OF adder4 IS SIGNAL c1, c2, c3 :STD_LOGIC; COMPONENT fulladder PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END COMPONENT; BEGIN FA0: fulladder PORT MAP (a(0), b(0), cin, s(0), c1); FA1: fulladder PORT MAP (a(1), b(1), c1 , s(1), c2); FA2: fulladder PORT MAP (a(2), b(2), c2, s(2), c3); FA3: fulladder PORT MAP (s => s(3), x => a(3), cin => c3, y => b(3), cout => s(4)); END behavior; Note: During creating a project for the 4-bit adder, the VHDL file of the full adder must be added to the project (Page 2 of creating project procedure). 1.3.2 GENERATE Statement: There are two variants of GENERATE statement: FOR-GENERATE generate_label: FOR index_variable IN range GENERATE statement; statement; . . END GENERATE;
18

IF-GENERATE generate_label: IF expression GENERATE statement; statement; . . END GENERATE;
The IF-GENERATE statement is seldom needed, but the FOR-GENERATE is often used in practice. It provides a convenient way of repeating either a logic expression or a COMPONENT instantiation. Example6: Write a VHDL code for 4-bit binary adder. Use the full adder as a sub-circuit in your code, and the FOR-GENERATE statement. Solution: 1) We must write a VHDL code for the sub-circuit (i.e. full adder). LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END fulladder; ARCHITECTURE behavior OF fulladder IS BEGIN s<= x XOR y XOR cin; cout<= (x AND y) OR (x AND cin) OR (y AND cin); END behavior; 2) Now, we can write the VHDL code for the 4-bit binary adder.
b(3)
y
a(3)
x cin
b(2)
y
a(2)
x cin
b(1)
y
a(1)
x cin
b(0)
y
a(0)
x cin
c(4)
cout F.A3 s
c(3)
cout F.A2 s
c(2)
cout F.A1 s
c(1)
cout F.A0 s
cin c(0)
s(4)
s(3)
s(2)
s(1)
s(0)
19
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY adder4 IS PORT (a, b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); cin :IN STD_LOGIC s : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)); END adder4; ARCHITECTURE behavior OF adder4 IS SIGNAL c :STD_LOGIC_VECTOR (0 TO 4); COMPONENT fulladder PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END COMPONENT; BEGIN generate_fulladders: FOR i IN 0 TO 3 GENERATE FA: fulladder PORT MAP (a(i), b(i), c(i), s(i), c(i+1)); END GENERATE; c(0)<= cin; s(4)<= c(4); END behavior; Example7: Write a VHDL code for 4-bit binary adder using the arithmetic operator and UNSIGNED data type. Solution: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY adder4 IS PORT (a, b : IN cin :IN s : OUT END adder4; ARCHITECTURE behavior OF adder4 IS BEGIN s<= (0 & a) + b+cin; END behavior;
UNSIGNED (3 DOWNTO 0); UNSIGNED (0 DOWNTO 0); UNSIGNED (4 DOWNTO 0));
20
Example8: Write a VHDL code for 4-bit binary adder using the arithmetic operator and STD_LOGIC data type. Solution: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY adder4 IS PORT (a, b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); cin :IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)); END adder4; ARCHITECTURE behavior OF adder4 IS BEGIN s<= (0 & a) + b+cin; END behavior; 1.3.3 GENERIC Statement The code of the previous example (example 6) can be made more general by introducing a parameter in the code that represents the number of bits in the adder. In VHDL jargon such parameter is called GENERIC. Example9: Write a VHDL code for n-bit binary adder. Solution: 1) We must write a VHDL code for the sub-circuit (i.e. full adder). LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END fulladder; ARCHITECTURE behavior OF fulladder IS BEGIN s<= x XOR y XOR cin; cout<= (x AND y) OR (x AND cin) OR (y AND cin); END behavior;
21
2) Now, we can write the VHDL code for the n-bit binary adder.
b(n-1)
y
a(n-1)
x
b(1)
y
a(1)
x cin
b(0)
y
a(0)
x cin
c(n)
cout F.A(n-1) cin s
c(n-1)
c(2)
cout F.A1 s
c(1)
cout F.A0 s
cin c(0)
s(n)
s(n-1)
s(1)
Block diagram of n-bit binary adder
s(0)
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY addern IS GENERIC (n: INTEGER:=4); PORT (a, b : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0); cin :IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR (n DOWNTO 0)); END addern; ARCHITECTURE behavior OF addern IS SIGNAL c :STD_LOGIC_VECTOR (0 TO n); COMPONENT fulladder PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END COMPONENT; BEGIN generate_fulladders: FOR i IN 0 TO n-1 GENERATE FA: fulladder PORT MAP (a(i), b(i), c(i), s(i), c(i+1)); END GENERATE; c(0)<= cin; s(n)<= c(n); END behavior;
22
1.3.4 PACKAGE: A VHDL PACKAGE serves as store. It is used to hold VHDL codes that are of general use. The PACKAGE can be included for use in any number of other VHDL codes. PACKAGE can have two main parts a) PACKAGE Declaration: The PACKAGE declaration contains declarations that may be shared between different entity units. General form: PACKAGE package_name IS [TYPE declaration] [SIGNAL declaration] [COMPONENT declaration] END package_name;
b) PACKAGE body: It is an optional part; it is used to define VHDL functions. The PACKAGE can be used by any code that includes the following statement: LIBRARY library_name; USE library_name.package_name.ALL; The library_name represents the location in the computer file system where the PACKAGE is stored. Declaring a COMPONENT in PACKAGE: Consider the following example: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE fulladder_package IS COMPONENT fulladder PORT( x, y, cin s, cout END COMPONENT; END fulladder_package;
: IN : OUT
STD_LOGIC; STD_LOGIC);
This example defines the PACKAGE named fulladder_package which provides the COMPONENT declaration for the fulladder ENTITY. This PACKAGE can be stored in a separate source code file or can be included at the end of the file that defines the fulladder ENTITY. Any source code that includes the statement USE work.fulladder_package.ALL can use the fulladder COMPONENT as a subcircuit.
23
Example10: Write a VHDL code for 4-bit binary adder. Use the fulladder_package as a sub-circuit in your code. Solution: 1) We must write a VHDL code for the sub-circuit (i.e. full adder). LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END fulladder; ARCHITECTURE behavior OF fulladder IS BEGIN s<= x XOR y XOR cin; cout<= (x AND y) OR (x AND cin) OR (y AND cin); END behavior; 2) Write a VHDL code for the fulladder_package: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE fulladder_package IS COMPONENT fulladder PORT( x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC); END COMPONENT; END fulladder_package; 3) Now, we can write the VHDL code for the 4-bit binary adder. b(3) a(3) b(2) a(2) b(1) a(1)
y cout F.A3 s x cin y x cin y x cin
b(0)
y
a(0)
x cin
c3
cout F.A2 s
c2
cout F.A1 s
c1
cout F.A0 s
cin
s(4)
s(3)
s(2)
s(1)
s(0)
LIBRARY IEEE; LIBRARY work; USE IEEE.STD_LOGIC_1164.ALL; USE work.fulladder_package.ALL;
24
ENTITY adder4 IS PORT (a, b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); cin :IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)); END adder4; ARCHITECTURE behavior OF adder4 IS SIGNAL c1, c2, c3 :STD_LOGIC; BEGIN FA0: fulladder PORT MAP (a(0), b(0), cin, s(0), c1); FA1: fulladder PORT MAP (a(1), b(1), c1 , s(1), c2); FA2: fulladder PORT MAP (a(2), b(2), c2, s(2), c3); FA3: fulladder PORT MAP (a(3), b(3), c3, s(3),s(4)); END behavior; Home Work4: Write a VHDL code for n-bit binary adder using arithmetic operators and STD_LOGIC data type. Home Work5: Write a VHDL code for 16-to-1 multiplexer using: 1. (2 to-1) multiplexer as a COMPONENT. 2. (4 to-1) multiplexer as a COMPONENT. Home Work6: Write a VHDL code for the 4-bit binary adder using simple SIGNAL assignment statements and FOR-GENERATE statement 1.4 Sequential Assignment Statements (Behavioral Model): The behavioral model allows statements to be executed sequentially just like in a regular computer program. Sequential statements include many of the standard constructs, such as VARIABLE assignments, IF statements, CASE statement, LOOP statement, and WAIT statement. The order in which the concurrent SIGNAL assignment statement in ARCHITECTURE body appears does not affect the meaning of the code. Many types of logic circuits can be described using these statements. VHDL provides another type of statements; called sequential assignment statement; for which the order of the statement in the code can affect the meaning of the code. 1.4.1 PROCESS Statement: The PROCESS block contains statements that are executed sequentially. The PROCESS statement itself is a concurrent statement. Multiple PROCESS blocks in architecture will be executed simultaneously. These PROCESS blocks can be combined together with other concurrent statements.
25
The PROCESS statement is used to separate sequential statement and concurrent statements. PROCESS statement appears inside the ARCHITECTURE body. The statements (IF, CASE, LOOP) can appear only inside PROCESS. The structure of PROCESS is somewhat similar to ARCHITECTURE. VARIABLE data objects can be declared only inside the PROCESS. Any VARIABLE declared can be used only by the code within the PROCESS; to use the value of such VARIABLE outside the PROCESS, the VARIABLE value can be assigned to SIGNAL. The (IF, CASE, and LOOP) statements can be used to describe either combinational or sequential circuits. In VHDL jargon, a PROCESS is described as follows: When the value of a SIGNAL in the sensitivity list changes, the PROCESS becomes active, statements inside PROCESS evaluated in sequential order. Any SIGNAL assignment made inside PROCESS takes effect only after all the statements inside PROCESS evaluated. General form of PROCESS: PROCESS (sensitivity_list) [VARIABLE declarations] BEGIN [Simple SIGNAL Assignment Statement] [Variable Assignment Statement] [WAIT Statement] [CASE Statement] [IF Statement] [LOOP Statement] END PROCESS; The sensitivity list is a comma-separated list of SIGNALs, which the PROCESS is sensitive to. In other words, whenever a SIGNAL in the list changes value, the PROCESS will be executed (i.e., all of the statements in the sequential order listed). After the last statement has been executed, the PROCESS will be suspended until the next time that a SIGNAL in the sensitivity list changes value before it is executed again. 1.4.2 IF Statement: General Form: IF expression THEN Statements; ELSIF expression THEN Statements; ELSE Statements; END IF;
26
Example11: Write a VHDL code for 4-to-1 multiplexer using IF statement. Solution: To write a VHDL code using IF statement, we must draw its truth table.
s1 0 0 1 1 s0 0 1 0 1 f x0 x1 x2 x3 x0 x1 x2 x3
s1
s0 f
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4to1 IS PORT( x : IN STD_LOGIC_VECTOR (0 TO 3); s :IN STD_LOGIC_VECTOR (1 DOWNTO 0); f : OUT STD_LOGIC); END mux4to1; ARCHITECTURE behavior OF mux4to1 IS BEGIN PROCESS (s, x) BEGIN IF s =00 THEN f<= x(0); ELSIF s =01 THEN f<= x(1); ELSIF s =10 THEN f<= x(2); ELSE f<= x(3); END IF; END PROCESS; END behavior; 1.4.3 CASE Statement: General form: CASE expression IS WHEN constant_value => Statements; WHEN constant_value => Statements; WHEN OTHERS => Statements; END CASE;
27
Example12: Write a VHDL code for 4-to-1 multiplexer using CASE statement. Solution: To write a VHDL code using CASE statement, we must draw its truth table.
s1 0 0 1 1 s0 0 1 0 1 f x0 x1 x2 x3 x0 x1 x2 x3
s1 s0 f
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4to1 IS PORT( x : IN STD_LOGIC_VECTOR (0 TO 3); s :IN STD_LOGIC_VECTOR (1 DOWNTO 0); f : OUT STD_LOGIC); END mux4to1; ARCHITECTURE behavior OF mux4to1 IS BEGIN PROCESS (s, x) BEGIN CASE s IS WHEN 00 => f<= x(0); WHEN 01 => f<= x(1); WHEN 10 => f<= x(2); WHEN OTHERS => f<= x(3); END CASE; END PROCESS; END behavior; 1.4.4 LOOP Statement: There are two types of LOOP statements: FOR-LOOP WHILE-LOOP These statements are used to repeat one or more sequential assignment statements.
28

General form: FOR variable_name IN range LOOP Statements; END LOOP;
WHILE boolean_expresion LOOP Statements; END LOOP;
1.4.5 VARIABLE Assignment Statement: The VARIABLE assignment statement assigns a value or the result of evaluating an expression to a VARIABLE. The value is always assigned to the VARIABLE instantaneously whenever this statement is executed. VARIABLEs are only declared within a PROCESS block. Example: y := '1'; yn := NOT y; Example13: Write a VHDL code for a circuit that counts the number of ones in an 4-bit data. Solution:
[ x(3) x(2) x(1) x(0) ]
count
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ones IS PORT( x :IN STD_LOGIC_VECTOR(3 DOWNTO 0); count :OUT INTEGER RANGE 0 TO 4); END ones; ARCHITECTURE behavior OF ones IS BEGIN PROCESS (x) VARIABLE tmp:INTEGER; BEGIN tmp :=0; FOR i IN 0 TO 3 LOOP IF x(i) =1 THEN tmp := tmp +1; END IF; END LOOP; count<= tmp; END PROCESS; END behavior
29
1.4.6 WAIT Statement: When a PROCESS has a sensitivity list, the PROCESS always suspends after executing the last statement. An alternative to using a sensitivity list to suspend a process is to use a WAIT statement, which must also be the first statement in a PROCESS. General form: WAIT UNTIL condition; Example14: Write a VHDL code for D-type latch using: 1. Simple SIGNAL assignment statement. 2. PROCESS statement. Solution:
d clk
s1 q q s2
Logic diagram of D-type latch
clk
Block diagram of D-type latch
1) D-type latch using simple assignment statements. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dlatch IS PORT( d, clk :IN STD_LOGIC; q, qd :BUFFER STD_LOGIC); END dlatch; ARCHITECTURE behavior OF dlatch IS SIGNAL s1, s2:STD_LOGIC; BEGIN s1<= d NAND clk; s2<= NOT d NAND clk; q<= s1 NAND qd; qd<= s2 NAND q; END behavior; 2) D-type latch using PROCESS LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dlatch IS PORT( d, clk :IN q, qd :BUFER END dlatch;
STD_LOGIC; STD_LOGIC);
30

ARCHITECTURE behavior OF dlatch IS BEGIN PROCESS (d, clk) BEGIN IF clk =1 THEN q<= d; qd<= NOT q; END IF; END PROCESS; END behavior;
Example15: Write a VHDL code for +ve edge triggered D-type flip-flop using: 1. Simple SIGNAL assignment statement. 2. PROCESS statement. Solution:
d clk
q q
d clk
q q
d clk
q q
Block diagram of +ve edge triggered D- clk type flip-flop
Master-Slave connection
s1 s2
q1 qd1
s3 s4
q qd
clk
Logic diagram of +ve edge triggered D-type flip-flop.
1) +ve edge triggered D-type flip-flop using simple assignment statements. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY pedff IS PORT( d, clk :IN STD_LOGIC; q, qd :BUFFER STD_LOGIC); END pedff; ARCHITECTURE behavior OF pedff IS SIGNAL s1, s2, s3,s4,q1,qd1:STD_LOGIC; BEGIN s1<= d NAND clk; s2<= NOT d NAND NOT clk;
31

q<= s1 NAND qd1; qd<= s2 NAND q1; s3<= q1 NAND clk; s4<= qd1 NAND clk; q<= s3 NAND qd; qd<= s4 NAND q; END behavior;
2) +ve edge triggered D-type flip-flop using PROCESS: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY pedff IS PORT( d, clk :IN STD_LOGIC; q, qd :BUFFER STD_LOGIC); END pedff; ARCHITECTURE behavior OF pedff IS BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk =1 THEN - - line1 q<= d; qd<= NOT q; END IF; END PROCESS; END behavior; Notes: 1. For ve edge triggered D-type flip-flop, line 1 is replaced by: IF clkEVENT AND clk =0 THEN 2. We can use WAIT UNTIL statement instead of IF-THEN statement as follows: PROCESS - - No need for sensitivity list. BEGIN WAIT UNTIL clkEVENT AND clk=1 ; q<=d; qd<= NOT q; END PROCESS; Homework7: Write a VHDL code for -ve edge triggered D-type flip-flop using: 1. D-type latch as a COMPONENT. 2. Simple SIGNAL assignment statement.
32
Homework8: Write a VHDL code for +ve edge triggered JK flip-flop using: 1. +ve edge triggered d-type flip-flop as a COMPONENT. 2. Simple SIGNAL assignment statement. 3. PROCESS statement. Homework9: Repeat homework8 for: 1. +ve edge triggered SR flip-flop. 2. +ve edge triggered T-type flip-flop. Example16: Write a VHDL code for +ve edge triggered D-type flip-flop with asynchronous reset. Solution: reset clk d q+ d q 0 x x 0
clk reset
Block diagram of +ve edge triggered Dtype flip-flop
1 1
0 1
0 1
Truth table of +ve edge triggered D-type flip-flop
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY pedff IS PORT( d, clk, reset :IN STD_LOGIC; q :OUT STD_LOGIC); END pedff; ARCHITECTURE behavior OF pedff IS BEGIN PROCESS (clk, reset) BEGIN IF reset= 0 THEN q<=0; ELSIF clkEVENT AND clk =1 THEN q<=d; END IF; END PROCESS; END behavior;
33
Example17: Write a VHDL code for +ve edge triggered D-type flip-flop with synchronous reset. Solution: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY pedff IS PORT( d, clk, reset :IN STD_LOGIC; q :OUT STD_LOGIC); END pedff; ARCHITECTURE behavior OF pedff IS BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk =1 THEN IF reset= 0 THEN q<=0; ELSE q<=d; END IF; END IF; END PROCESS; END behavior; Example18: Write a VHDL code for 4-bit parallel in - parallel out register with asynchronous clear. Solution:
q(3) d q d q
q(2) d q
q(1) d q
q(0)
clk clear d(3)

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY reg4 IS PORT( d clk, clear q END reg4;
d(2)
d(1)
d(0)
:IN :IN :OUT
STD_LOGIC_VECTOR (3 DOWNTO 0); STD_LOGIC; STD_LOGIC_VECTOR (3 DOWNTO 0));
34

ARCHITECTURE behavior OF reg4 IS BEGIN PROCESS (clk, clear) BEGIN IF clear= 0 THEN q<=0000; ELSIF clkEVENT AND clk =1 THEN q<=d; END IF; END PROCESS; END behavior;
Example19: Write a VHDL code for 4-bit shift register (serial in- parallel out). Solution:
q(3) din d q d q
q(2) d q
q(1) d q
q(0)
clk
1) Using SIGNAL assignment statement: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift4 IS PORT ( din, clk :IN q :OUT END shift4; ARCHITECTURE behavior OF shift4 IS BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk =1 THEN q(3) <= din ; - - line1 q(2) <= q(3); - - line2 q(1) <= q(2); - - line3 q(0) <= q(1); - - line4 END IF; END PROCESS; END behavior;
STD_LOGIC; STD_LOGIC_VECTOR (3 DOWNTO 0));
q(0) <= q(1) ; q(1) <= q(2); q(2) <= q(3); q(3) <= din;
q(1) <= q(2); q(3) <= din ; q(0) <= q(1); q(2) <= q(3);
35
Note: The sequence for the assignments in (line1 to line4) does not affect the operation of the circuit because the SIGNAL assignment inside the PROCESS does not take effect immediately; but it is scheduled to occur at the end of the PROCESS. 2) Using VARIABLE assignment statement LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift4 IS PORT ( din, clk :IN STD_LOGIC; q :OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END shift4; ARCHITECTURE behavior OF shift4 IS BEGIN PROCESS (clk) VARIABLE s : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN IF clkEVENT AND clk =1 THEN s(0) := s(1) ; s(3) := din ; s(1) := s(2); s(1) := s(2); s(2) := s(3); s(3) := din ; s(2) := s(3); s(1) := s(2); s(0) := s(1); s(3) := din; s(0) := s(1); s(2) := s(3); END IF; q<= s; END PROCESS; END behavior; Homework10: Write a VHDL code for 4-bit parallel in-serial out register. Homework11: Write a VHDL code for 4-bit serial in-serial our register. Homework12: Write a VHDL code for n-bit parallel in- parallel out register with asynchronous reset using: 1. PROCESS statement. 2. +ve edge triggered D-type flip-flop as a COMPONENT. Homework13: Write a VHDL code for 4-bit parallel in-parallel out register with asynchronous preset and asynchronous reset input. The reset input must have the most priority.
36
Example20: Write a VHDL code for 4-bit binary up-counter with asynchronous reset input. Solution: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count4 IS PORT (clk, rst :IN STD_LOGIC; q :OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END count4; ARCHITECTURE behavior OF count4 IS BEGIN SIGNAL count: STD_LOGIC_VECTOR (3 DOWNTO 0); PROCESS (clk,rst) BEGIN IF rst =0 THEN count<=0000; ELSIF clkEVENT AND clk =1 THEN count<= count+1; END IF; END PROCESS; q<=count; END behavior; Homework14: Write a VHDL code for 4-bit binary down counter with asynchronous reset. Homework15: Write a VHDL code for 4-bit binary up-down counter with asynchronous reset. Homework16: Write a VHDL code for 4-bit binary up counter with asynchronous reset using: 1. +ve edge triggered D-type flip-flop as a COMPONENT. 2. +ve edge triggered T-type flip-flop as a PACKAGE. Homework17: Write a VHDL code for asynchronous 4-bit binary up counter with synchronous reset using -ve edge triggered T-type flip-flop as a PACKAGE. Homework18: Write a VHDL code for mode11 up counter with asynchronous reset using: 1. +ve edge triggered D-type flip-flop as a COMPONENT. 2. PROCESS statement.
37

reset
S1/0
Example21: Write a VHDL code for the Moore model state machine shown below:
0 0 1
S5/1
1
S2/0
Solution: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY moore IS PORT ( x, clk, reset :IN STD_LOGIC; z :OUT STD_LOGIC); END moore; ARCHITECTURE behavior OF moore IS TYPE state_machine IS (s1, s2, s5); SIGNAL y: state_machine; BEGIN PROCESS (clk, reset) BEGIN IF reset=0 THEN y<= s1; ELSIF clkEVENT AND clk=1 THEN CASE y IS WHEN s1 => IF x=0 THEN y<=s1; ELSE y<= s2; END IF; WHEN s2 => IF x=0 THEN y<=s1; ELSE y<= s5; END IF; WHEN s5 => IF x=0 THEN y<=s1; ELSE y<= s5; END IF; END CASE; END IF; END PROCESS; z<= 1 WHEN y=s5 ELSE 0; END behavior;
38
Example22: Write a VHDL code for the Mealy model state machine shown below: reset
1/0 0/0 a b 0/0 Solution: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mealy IS PORT ( x, clk, reset :IN STD_LOGIC; z :OUT STD_LOGIC); END mealy; ARCHITECTURE behavior OF mealy IS TYPE state_machine IS (a, b); SIGNAL y: state_machine; BEGIN PROCESS (clk, reset) BEGIN IF reset=0 THEN y<= a; ELSIF clkEVENT AND clk=1 THEN CASE y IS WHEN a => IF x=0 THEN y<=a; ELSE y<= b; END IF; WHEN b => IF x=0 THEN y<=a; ELSE y<= b; END IF; END CASE; END IF; END PROCESS; PROCESS (x, y) BEGIN CASE y IS WHEN a => z<=0; WHEN b => z<=x; END CASE; END PROCESS; END behavior; 1/1
39
1.5 Type Conversion: VHDL is a strongly type checked language, which means that it does not permit the value of a SIGNAL of one type to be assigned to another SIGNAL that has a different type. When it is necessary to use a code that has a mixture of types, type conversion function can be used. 1.5.1 CONV_INTEGER (): It is used to converts a STD_LOGIC_VECTOR type to an INTEGER type. Its use requires the inclusion of the UNSGNED package: General form: CONV_INTEGER (STD_LOGIC_VECTOR data type) Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_UNSIGNED.ALL; SIGNAL four_bit: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL n: INTEGER; n <= CONV_INTEGER(four_bit);
1.5.2 CONV_STD_LOGIC_VECTOR ( , ) It is used to converts an INTEGER type to a STD_LOGIC_VECTOR type. Its use requires the inclusion of the ARITH package. General Form: CONV_STD_LOGIC_VECTOR (integer, number_of_bits) Example: LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; SIGNAL x: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL y: INTEGER; x<= CONV_STD_LOGIC_VECTOR(y,4);
40

Digital Systems Design Ch1 VHDL - VHDL Hardware Description Language

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Systems Design Ch1 VHDL - VHDL Hardware Description Language

Uploaded by

Copyright:

Available Formats

Digital Systems Design Chapter 1: VHDL

Prepared by: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Design Language (ASCII text file inside Computer)

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

For signed number arithmetic. For signed number arithmetic.

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Operator = /= < <= > >=

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

BIT_VECTOR (3 DOWNTO 0); BIT_VECTOR (3 DOWNTO 0));

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

STANDARD STD TEXTIO WORK [set by user]

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Logic diagram of 4-to-1 Multiplexer

Block diagram of 4-to-1 Multiplexer

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Truth table of 4-to-1 Multiplexer

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Truth table of 4-to-1 Multiplexer

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Block diagram of 4-bit binary adder

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Block diagram of 4-bit binary adder

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

UNSIGNED (3 DOWNTO 0); UNSIGNED (0 DOWNTO 0); UNSIGNED (4 DOWNTO 0));

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

cout F.A(n-1) cin s

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Digital System Design

Prepared By: Mr. Araz Sabir Ameen

Block diagram of 4-bit binary adder