EC2354 0 03 AIM

VLSI DESIGN

LTPC 3

To introduce the technology, design concepts and testing of Very Large Scale Integrated Circuits. OBJECTIVES To learn the basic CMOS circuits. To learn the CMOS process technology. To learn techniques of chip design using programmable de ices. To learn the concepts of designing VLSI subsystems. To learn the concepts of modeling a digital system using !ard"are #escription Language. CMOS TECHNOLOGY 9

UNIT I

$ brief !istory%MOS transistor, Ideal I%V characteristics, C%V characteristics, &on ideal IV effects, #C transfer characteristics % CMOS technologies, Layout design 'ules, CMOS process enhancements, Technology related C$# issues, Manufacturing issues UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION 9

#elay estimation, Logical effort and Transistor si(ing, )o"er dissipation, Interconnect, #esign margin, 'eliability, Scaling% S)IC* tutorial, #e ice models, #e ice characteri(ation, Circuit characteri(ation, Interconnect simulation UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9

Circuit families +Lo" po"er logic design + comparison of circuit families + Sequencing static circuits, circuit design of latches and flip flops, Static sequencing element methodology% sequencing dynamic circuits + synchroni(ers

UNIT IV CMOS TESTING

&eed for testing% Testers, Te,t fi,tures and test programs% Logic erification% Silicon debug principles% Manufacturing test + #esign for testability + -oundary scan UNIT V SPECIFICATION USING VERILOG HDL 9

-asic concepts% identifiers% gate primiti es, gate delays, operators, timing controls, procedural assignments conditional statements, #ata flo" and 'TL, structural gate le el s"itch le el modeling, #esign hierarchies, -eha ioral and 'TL modeling, Test benches, Structural gate le el description of decoder, equality detector, comparator, priority encoder, half adder, full adder, 'ipple carry adder, # latch and # flip flop. TOT$L . /0 )*'IO#S TEXT BOO S 1. 2este and !arris3 CMOS VLSI #*SI4& 5Third edition6 )earson *ducation, 7880 7. 9yemura :.)3 Introduction to VLSI circuits and systems, 2iley 7887. REFERENCES 1. #.$ )uc;nell < =.*shraghian -asic VLSI #esign, Third edition, )!I, 788> 7. 2ayne 2olf, Modern VLSI design, )earson *ducation, 788> >. M.:.S.Smith3 $pplication specific integrated circuits, )earson *ducation, 1??@ /. :.-has;er3 Verilog !#L primer, -S publication,7881 0. Ciletti $d anced #igital #esign "ith the Verilog !#L, )rentice !all of India, 788>

EC235!

VLSI DESIGN LABORATORY

LTPC 0032

1. #esign *ntry and simulation of combinational logic circuits 5A bit adders, / bit multipliers, address decoders, multiple,ers6, Test bench creation, functional erification, and concepts of concurrent and sequential e,ecution to be highlighted. 7. #esign *ntry and simulation of sequential logic circuits 5counters, )'-S generators, accumulators6. Test bench creation, functional erification, and concepts of concurrent and sequential e,ecution to be highlighted. >. Synthesis, )<' and )ost )<' simulation for all the bloc;sBcodes de eloped in *,pt. &o. 1 and &o. 7 gi en abo e. Concepts of C)4$ floor plan, critical path, design gate count, IBO configuration and pin assignment to be taught in this e,periment. /. 4eneration of configurationBfuse files for all the bloc;sBcodes de eloped as part of *,pt.1. and *,pt. 7. C)4$ de ices must be configured and hard"are tested for the bloc;sBcodes de eloped as part of *,pt. 1. and *,pt. 7. The correctness of the inputs and outputs for each of the bloc;s must be demonstrated atleast on oscilloscopes 5logic analy(er preferred6. 0. Schematic *ntry and S)IC* simulation of MOS differential amplifier. #etermination of gain, band"idth, output impedance and CM''. D. Layout of a simple CMOS in erter, parasitic e,traction and simulation. @. #esign of a 18 bit number controlled oscillator using standard cell approach, simulation follo"ed by study of synthesis reports. A. $utomatic layout generation follo"ed by post layout e,traction and simulation of the circuit studied in *,pt. &o.@

&ote 1. Cor *,pt. 1 To / can be carried out using $ltera 5Euartus6 B Filin, 5$lliance6 B $CT*L 5Libero6 tools. &ote 7. Cor e,pt. 0%A introduce the student to basics of IC design. These ha e to be carried out using atleast 8.0u CMOS technology libraries. The SB2 tools needed Cadence B M$4M$ B Tanner.