INTRODUCTION FPGA-based Implementation of Efficient Sample Rate Conversion for Software Defined Radios Software Radio (SR) is a communication

device in which all the signal processing aspects are implemented as software components. New standards, protocols and services can be supported by simply upgrading the software of the device [1]. A fundamental problem relating to SR design is the complexity of the component (software module) immediately following the Analog to Digital converter (ADC). The main constituent blocks of the SR thus include (i) the analog Radio Frequency (RF) front end, (ii) the digital IF stage and (iii) the baseband processor as shown in Fig. 1(DIGITAL IF BASED SR) Most radios are hardware defined with little or no software control; they are fixed in function, have a short life and are designed to be discarded and replaced. To support multiple air interfaces it needs a dedicated hardware for each air interface, which increase the cost. Software defined radio (SDR) uses programmable digital devices to perform the signal processing necessary to transmit and receive baseband information at radio frequency, devices such as field programmable gate arrays (FPGAs) use software to provide the required signal processing functionality. This technology offers greater flexibility and potentially longer product life, since the radio can be upgraded very cost effectively with software. The SR has to support multiple standards, each requiring a different sampling clock. Hardware constraints limit a SR to only a single clock pulse, which in turn has to support multiple data rates. An efficient approach for sample rate conversion employing joint Cascaded Integrator Comb (CIC) compensation filter along with polynomial interpolation using the Farrow structure is proposed in [3].
This paper presents an innovative implementation of a SRC architecture for multi-standard SR receivers, using a rapid development and prototyping approach. The prime focus of this paper is the hardware implementation and analysis of the abovementioned architecture. The design has been implemented and tested using ModelSim SE 6.5 and Xilinx ISE Project Navigator, with top level simulations being done in

MATLAB. The architecture has been captured using VHDL.

DIGITAL UP CONVERTER
FROM ALTERA Accelerating DUC & DDC System Designs for WiMAX A digital up converter (DUC) provides the link between the digital baseband and analog RF front end and is required on the transmitter of a generic transceiver. The sampling frequency of the baseband data stream is increased before it is modulated onto a high frequency carrier.

The algorithm consists ofthree stages shown in Figure 2: 1. Channel Filter Applies pulse shaping to ensure that the spectral mask and restrictions imposed by the regulatory body are not violated. 2. Interpolation The sampling frequency of the baseband samples are increased. Filtering is required to mask spectral images that appear as part of the interpolation process. 3. Mixer/Combiner A numerically controlled oscillator (NCO) generates two orthogonal sinusoids at the carrier frequency and these are mixed with the I and Q streams. Finally the outputs of the mixers are added together before being passed on to the digital-toanalog converter (DAC).

FROM Design and implementation of low power digital up converter for power line communication systems The Digital up Converter is a digital circuit which implements

the conversion of a complex digital baseband signal to a real passband signal. The input complex baseband signal is sampled at a relatively low sampling rate, typically the digital modulation symbol rate. The baseband signal is filtered and converted to a higher sampling rate before being modulated onto a direct digitally synthesized (DDS) carrier frequency.

WCDMA DUC shown in Figure 2 converts the complex input chip-rate baseband signal d (j) to a real pass band signal s (n). The baseband signal is filtered and converted to a higher sampling rate before being modulated onto a DDS carrier c (n).

Radio Standard

GSM 900

CDMA 2000

UMT

Intermediate frequency (MHz)

80

80

80

Sampling Frequency (MSps)

160

160

160

Single channel Bandwidth (MHz)

0.2

1.25

Input Data rate (MSps)

0.270

1.2288

3.84

Sample Rate Conversion Ratio

590.77

130.02

41.66

A block diagram of the Digital up Converter is shown in Figure 1. Spectral shaping of the complex input signal is performed by the PFIR filter. Typically this filter would be performing a Nyquist transmit filter operation with a rate-change of 2. Bias-free convergent rounding or truncation is employed between each processing stage to limit the bit growth through the DUC

Output from each of the PFIR filters is input to each of the CFIR filters, which is used to compensate for the droop within the CIC filter and performs the second rate-change. The CFIR also performs a rate-change of 2. The CFIR filters output drives the input to the interpolating CIC filter, which is used for high sample rate change of 4. The complex data stream from the CIC filter is mixed with a local oscillator generated by the DDS. Results from the mixers are combined, forming the final DUC result. The DUCresult is often used as the input to a digital-to-analog converter (DAC) to generate an intermediate frequency analog signal.

DUC DESIGN
1) WCDMA Channel Filter Design: The transmitted pulse shaper is an RRC filter with roll-off = 0.22. The RRC filter

needs to be designed to meet the Spectral Mask Requirements. It was found that a 45-tap symmetric RRC filter with

Chebyshev windowing (side lobe parameter set to 27 dB) met all of the filter objectives.The Chebyshev windowing provides better side lobe suppression than a rectangular window. Also, it is a type of adjustable window that requires lower filter order to achieve similar performance than various windows.

Figure 4: Magnitude Response of RRC Filter