IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO.

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Design of High-Speed Power-Efcient MOS Current-Mode Logic Frequency Dividers

Massimo Alioto, Member, IEEE, Rosario Mita, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE
AbstractA methodology to design high-speed power-efcient MOS current-mode logic (MCML) static frequency dividers is proposed. Analytical criteria to exploit the speed potential of MCML gates are rst introduced. Then, an analytical strategy is formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, thereby reducing the overall power consumption. The proposed design approach is general and independent of the process adopted. Due to its simplicity, it can be used in a pencil-and-paper approach, avoiding a tedious and time-consuming trial-and-error approach based on simulations. Moreover, the analytical approach allows for a deeper understanding of the powerdelay tradeoff involved in the design. As a design example, a 1:8 frequency divider is designed and simulated by using a 0.18- m CMOS process. Index TermsCMOS, high speed, integrated circuit, low power, MOS current-mode logic (MCML), prescaler, RF, source coupled logic, static frequency divider.

Fig. 1. Architecture of a static frequency divider.

I. INTRODUCTION TATIC frequency dividers are fundamental building blocks in a number of applications, such as frequency synthesis in mobile or satellite communication systems, clock generation, data recovery, synchronization, and multiple gigabits per second optic-ber systems [1][6]. In these applications, the frequency divider is often the speed-limiting block; thus, a high-speed performance is required. Moreover, current applications require a low power consumption to reduce the heat generation, as well as to extend the battery lifetime in portable devices. In this scenario, the speed improvement allowed by the technology scaling has made the CMOS technology suitable for several high-speed applications, thereby enabling the integration of RF blocks in complex systems-on-chip [7]. static frequency divider is obtained by In general, a cascading 1:2 dividers whose output frequency is half that of their input waveform, as depicted in Fig. 1. When adopting a CMOS technology, all the stages are usually implemented with the MOS current-mode logic (MCML) approach and a differential signaling to achieve a very high speed performance [8], [9]. However, the latter is obtained at the cost of a signicant static power consumption, which is associated with the bias current of the divider stages.

In this brief, an analytical strategy is proposed to size the bias currents in the stages of a static frequency divider to achieve a high-speed performance. Moreover, since each stage operates at a halved frequency as compared to the previous one, an analytical strategy to progressively reduce the bias currents (and thus the power consumption) of the successive stages is developed. The analytical results are a useful tool for designing frequency dividers since they also afford a deeper understanding of the powerdelay tradeoff. Furthermore, the closed-form bias current design equations avoid the time-consuming approach based on simulations with trial-and-error values of the design parameters. This brief is organized as follows. Section II deals with the timing analysis of the basic MCML 1:2 divider stage, and its powerdelay tradeoff is analyzed in Section III. A practical dedividers to properly size sign strategy for more general the bias currents is presented in Section IV. Design examples are discussed in Section V. Finally, conclusions are reported in Section VI. II. TIMING ANALYSIS OF THE MCML 1:2 DIVIDER STAGE Let us consider the generic frequency divider depicted in Fig. 1, in which the rst stage has an input frequency , and the generic th 1:2 divider stage (with ) has an input frequency given by with (1)

Manuscript received November 17, 2005. This paper was recommended by Associate Editor V. Kursun. M. Alioto is with the Dipartimento di Ingegneria dellInformazione, Universit di Siena, 53100 Siena, Italy (e-mail: malioto@dii.unisi.it). R. Mita and G. Palumbo are with the Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universit di Catania, 95125 Catania, Italy (e-mail: rmita@diees.unict.it; gpalumbo@diees.unict.it). Digital Object Identier 10.1109/TCSII.2006.882350

since each stage has an input frequency that is halved as compared to the previous one. Since the 1:2 divider stage is the fundamental block of the divider, its speed performance is evaluated in the following. A 1:2 divider stage implemented in the MCML logic style is structured as in Fig. 2, where the two cross-coupled D latches implement a masterslave T ip-op (T-FF) with its clock terminals being driven by the differential input signal. Indeed, the two D latches are driven by opposite clock signals; hence, the input of each latch crosses both gates and turns to the opposite value every two clock edges due to the inversion associated with the cross coupling. The topology of the D latch in Fig. 2 is depicted in Fig. 3, where is the gate bias current [10],

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A. By taking the strict equality in (2), the maximum operating of the 1:2 stage results to frequency (3) From (3), it is apparent that a high-speed performance is achieved by reducing the delay of the level shifter and the latch. These timing parameters can be modeled by resorting to the general approach proposed in [2] and [3], which is valid for arbitrary MCML gates. Following this approach, the latch delay can be expressed as a function of the bias according to [2] and [3] current

Fig. 2. Structure of a 1:2 divider stage.

(4) is the logic swing; is the external load where capacitance; and , , and are coefcients that depend on the adopted technology, the voltage gain around the logic threshold , and the supply voltage , which are evaluated according to [2] and [3]. can also be modeled by reThe level shifter delay sorting to the methodology in [2] and [3] according to

(5) is the external load capacitance of the level shifter, is the gatesource capacitance of its transistor (M1M2), and are its effective channel width and length, and is its small-signal transconductance. According to [2], the latter was expressed with the traditional small-signal model after . substituting a suitable effective mobility In the following section, the timing model discussed until now is used to better understand the powerdelay tradeoff. where
Fig. 3. Topology of the MCML D latch.

[11]. Moreover, a level shifter (i.e., a common-drain stage implemented by M1M2) must be inserted at the clock input of the T-FF to avoid the operation in the triode region of transisbe the bias current tors M3M4 (see Fig. 3) [10], [11]. Let of the level shifter circuits. Now, let us evaluate the maximum operating frequency of a 1:2 frequency divider. To this aim, observe that, after the rising edge of the input signal (which is assumed to occur at time ), latch A must generate a valid output within , being the input period. Since the output evaluation of latch A is performed after the delay of the level shifter and the delay1 of latch A, the following condition must be satised to ensure correct operation (2) The same consideration leading to (2) holds in the negative half period for latch B; thus, it must have the same speed as latch
1The latch delay is measured from the clock transition to the output transition, which is usually referred to as the CK-Q delay.

III. POWERDELAY TRADEOFF IN THE MCML 1:2 DIVIDER STAGES The bias currents of the 1:2 divider stages in Fig. 1 must be sized to allow their correct operation, i.e., by setting their maximum operating frequency (3) greater than their input frequency (1). This is equivalent to make the level shifter and the latch delay in (3) sufciently low, which is achieved by making their bias current sufciently high. However, an increase in the bias currents determines an increase in the power consumpand the bias current); thus, tion (equal to the product of a powerdelay tradeoff exists. To better understand the powerdelay tradeoff, let us express the dependence of the delay of the latch (level shifter) on its bias currents . In regard to the latch delay in (4), from Fig. 2, its load capacitance is approximately2 equal to the input capacitance of an equal latch since latch A drives latch B and vice versa. From an analytical point of view, the latch
2In this evaluation, the input capacitance of the successive stage is neglected for latch B since from Fig. 2, it is only that of a common-drain stage (i.e., an overlap gatedrain capacitance [2]), which is much lower than the latch input capacitance.

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TABLE I PROCESS PARAMETERS FOR THE ADOPTED 0.18-m TECHNOLOGY

IV. DESIGN OF

FREQUENCY DIVIDERS

In practical applications, the frequency divider is often the speed-limiting block; thus, it must be designed for an almost maximum speed for a given process. Since from (1) the rst stage works at the highest frequency, it is the most critical block from a speed point of view, and its design is discussed in Section IV-A, whereas the design of the successive stages is dealt with in Section IV-B. Section IV-C reports a simplied design procedure. A. Design of the First Stage From (3), to fully exploit the speed potential of a given process, the latch and level shifter delay in the rst stage must be kept as low as possible by properly setting their bias currents and . Moreover, from (7), the minimum value of is obtained for , i.e., (10) In practical cases, the latch delay must be set close to (10) while within reasonable limits. Thus, dening for keeping the rst stage the ratio , we get

TABLE II NUMERICAL VALUES OF COEFFICIENTS IN (8)

input capacitance depends on its bias current according to the following relationship, as demonstrated in [2]: (6) where coefcient depends on the process parameters and the . Relationship (6) can preliminarily assigned voltage gain be substituted into (4) to achieve the explicit dependence of the latch delay on its bias current, i.e.,

(7) with coefcients , , and being dened as follows:

(11) whose value must be chosen from considerations on the powerdelay tradeoff. By inverting (11), the resulting bias that allows to achieve an assigned value of current is

(8) To have an idea about the order of magnitude of coefcients in (8), let us consider a 0.18- m CMOS process, whose main parameters are reported in Table I. The resulting numerical values of coefcients by applying the procedure in [2] and [3], asV and , are reported in Table II. suming , from Fig. 2, its In regard to the level shifter delay load capacitance consists of the input capacitance of the two latches A and B, which are driven by the level shifter. By substituting the latch input capacitance in (6), the level shifter delay results to (12) which, as expected, increases as decreases (i.e., improving the speed performance). To nd a suitable value of that ensures high speed without excessive power consumption, observe that for sufciently high values of , the second and third terms in (11) are much lower than unity; thus, a very high speed performance is obdoes not bring a sigtained, but a further increase in , the nicant delay reduction. Rather, for low values of second and third terms in (11) are much greater than unity; thus, a poor speed performance is achieved, but a further increase in greatly improves the speed performance. As a compromise, we suggest to make the sum of the second and third terms in (11) equal to unity, which leads to (13) (9) Obviously, different values of may be adopted depending on the application requirements. For example, a choice that optimally balances speed and power consumption is achieved by minimizing the powerdelay product [PDP; dened as the and the delay product of the power consumption

in (9) for a minThe numerical value of the capacitance imum-sized transistor in the adopted 0.18- m CMOS process is about 1.2 fF.

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(7)]. By nding the value of that minimizes PDP and substituting it into (11), the value of minimizing PDP is

whereas parameter of the th stage (dened in Section IV-A) is equal to that of the rst stage, i.e., . Thus, from (12) and of the th stage is (17), the latch current

(14) , it is well In regard to the choice of the bias current known that the level shifter delay can be made much smaller than (7). Indeed, the common-drain stage is often added to MCML gates to achieve a higher performance since it is able to achieve a much lower delay than an MCML gate for a given load capacitance and bias current [2]. Moreover, in Section III, was shown to be compathe level shifter load capacitance . rable to (more precisely, twice) that of the latch, i.e., As a consequence, the level shifter delay can be made much much smaller than that of the latch with a bias current lower than in (12). From these considerations and (3), a reasonable approach to achieve a high-speed performance is that makes the level shifter delay equal to nd the value of . In the following, let be to a small fraction of the ratio . When choosing parameter , it is worth noting that from (9), very low values of lead to a very , whereas values comparable to unity sighigh bias current nicantly reduce the maximum operating frequency in (3). As ranging from 0.1 to 0.2 are suga compromise, values of gested, which make the level shifter delay equal to 10%20% of the latch delay. By inverting (9), the resulting level shifter bias current is (18) where it was observed that the term is much greater than unity for submicrometer is equal to 17.8 technologies (for example, for the adopted 0.18- m process). For the adopted CMOS process, this approximation leads to an error lower than 20% and and as compared to the exact expression for rapidly tends to zero for greater values of and . From (15) and (17), the level shifter current of the th stage is

(19) The design equations (18), (19) express the bias currents of the generic th stage (including the rst one) as a function of the and , which have been preliminarily assigned parameters in the design of the rst stage, as discussed in Section IV-A. C. Simplied Design Procedure To quickly evaluate the stage bias currents, an easy scaling law through the divider stages can be found by approximating (18). Indeed, from (18), the ratio of the latch current of the th stage and the preceding th stage results to with (20) where the approximation hold if , which from (13) and (14) is certainly true for and still provides reasonably . Indeed, the approximation of accurate results even for the scaling factor (20) to 0.7 leads to a current ratio overestimaand and tion by at most 21% in the worst case much lower for greater values. Hence, in practical designs, it is sufcient to size the rst-stage bias current according to (12) and then progressively downscale the currents of the successive stages by a factor of 0.7. In each stage, the level shifter bias current is still evaluated by substituting into (19). V. DESIGN EXAMPLES AND VALIDATION To verify the theoretical derivations, a 1:8 frequency divider was designed and simulated with SPICE by using a 0.18- m CMOS process. By substituting the coefcients reported in Table II and setting V, mV, and , the two above-discussed design methodologies were applied, i.e., the high-speed design and the minimum PDP design, by respectively setting to 2 and to (14). Moreover,

(15) where the transistor aspect ratio is minimum due to the small load capacitance of the level shifter (simulations always leads to a also conrmed that a nonminimum speed degradation). From the above design considerations, the maximum frequency allowed by a 1:2 divider stage results to (16) where the rst factor is the frequency limit imposed by the and are chosen as previadopted technology, and terms ously discussed. B. Design of the Successive Stages As already discussed in Section II, the successive stages are not needed to be as fast as the previous ones under a given speed requirement; thus, their bias currents can be progressively reduced to achieve a power saving. To be more specic, from (1) and (3), each stage is allowed to have a latch delay that is twice that of the preceding stage, and the same consideration holds for the level shifter. This means that the ratio of the th stage in (11) is twice that of the previous th stage; thus with (17)

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TABLE III BIAS CURRENTS WITH EXACT CURRENT SCALING IN (20)

case of high-speed (minimum PDP) design as compared to the power consumption obtained with an exact scaling factor. VI. CONCLUSION In this brief, a strategy to design MCML static frequency dividers has been proposed. The strategy starts from the timing model of MCML gates in [2] and [3] and aims at achieving high speed with reasonable power consumption. To this purpose, an analytical expression of the rst-stage bias current has been provided to exploit the speed potential of the adopted technology. From analytical considerations, the authors suggest to set the latch delay to twice its minimum value allowed by the technology when the speed performance is of utmost importance and to a value greater than two [see (14)] when an optimum balance between power consumption and delay is desired. In regard to the rst-stage level shifter, it is suggested to set its bias current to make its delay to about 20% of the latch delay. To reduce the overall power consumption, analytical criteria are derived to progressively scale the bias currents of the successive stages. In particular, it is shown that the latch bias current of each stage can be downscaled by a factor of 0.7 as compared to that of the previous stage. This affords a signicant power saving as compared to the case of equally biased stages. The analytical design equations are general and can be used for pencil-and-paper evaluations, thereby avoiding a tedious and time-consuming trial-and-error approach based on simulations. Moreover, the analytical approach allows for a deeper understanding of the powerdelay tradeoff involved in the design. As a design example, a 1:8 frequency divider is designed and simulated by using a 0.18- m CMOS process by assuming different powerdelay requirements. Results show that the maximum operating frequency of the divider is always within 18% of the simulated value, thereby conrming the adequate accuracy of the analytical design equations. REFERENCES [1] Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and DesignB. Razavi, Ed.. Piscataway, NJ: IEEE Press, 1996. [2] M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits. Norwell, MA: Springer-Verlag, 2005. [3] , Design strategies for source coupled logic gates, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 5, pp. 640654, May 2003. [4] C. Hung, B. Floyd, B. Park, and K. O. Kenneth, Fully integrated 5.35-GHz CMOS VCOs and prescalers, IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 1722, Jan. 2001. [5] C. Lam and B. Razavi, A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4- m CMOS technology, IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 788794, May 2000. [6] A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okiara, H. Sakuraba, T. Endoh, and F. Masuoka, 0.18- m CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage uctuation, IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 988996, Jun. 2001. [7] A. A. Abidi, RF CMOS come of age, IEEE Microw. Mag., vol. 4, no. 4, pp. 4760, Dec. 2003. [8] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2003. [9] B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, 2003. [10] S. Kiaei, S. Chee, and D. Allstot, CMOS source-coupled logic for mixed-mode VLSI, in Proc. Int. Symp. Circuits Syst., 1990, pp. 16081611. [11] S. Maskai, S. Kiaei, and D. Allstot, Synthesis techniques for CMOS folded source-coupled logic circuits, IEEE J. Solid-State Circuits, vol. 27, no. 8, pp. 11571167, Aug. 1992.

Fig. 4. Input and output waveform of a 1:8 frequency divider (high-speed design, exact current scaling factor). TABLE IV BIAS CURRENTS WITH APPROXIMATE CURRENT SCALING IN (20)

the currents in the various 1:2 stages were scaled by using the exact and the approximate current scaling factor in (20) (i.e., and 0.7, respectively). The bias currents obtained for the high-speed and minimum PDP frequency dividers with exact scaling factor in (20) are reported in Table III, where all the level shifters bias currents were increased to 1 A to avoid subthreshold operation. In the high-speed design, the resulting maximum predicted frequency (16) is equal to 415 MHz, whereas in the minimum PDP design, it is equal to 335 MHz. Simulation results showed that the maximum operating frequency of the divider is 510 MHz (394 MHz) for the high-speed (minimum PDP) design; thus, the error of (16) is within 18% of the simulated value. This conrms the adequate accuracy of the analytical design equations. As an example, the input and output waveforms are plotted in Fig. 4 for the high-speed design case with exact current scaling factor in (20). Finally, Table IV summarizes the bias currents of the divider 1:2 stages in both the high-speed design and the minimum PDP design by using the approximate current scaling factor of 0.7 in (20), which makes the design easier. As expected, comparison of Tables III and IV shows that the bias currents are greater than those obtained with an exact scaling factor. According to the considerations in Section IV-C, this leads to only a slight increase in the power consumption of about 12% (9%) in the