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CHAPTER 13

MULTIPROCESSOR SYSTEMS There are basically two ways of i creasi ! the s"ee# of co$"%ter har#ware& They are by %si !' Hi!h s"ee# co$"o e ts (ew architect%ral str%ct%res

I the first cate!ory) hi!h*s"ee# co$"o e ts rely o e+otic tech olo!y a # fabricatio "rocesses a # s%ch tech olo!ies a # "rocesses te # to be e+"e si,e a # o *sta #ar#i-e#& M%lti"rocessor syste$s fall i to the seco # cate!ory a # "ro,i#e a alter ati,e for i$"ro,i ! "erfor$a ce of co$"%ter syste$s by co%"li ! a %$ber of low cost sta #ar# "rocessors& M%lti"rocessi ! ca be a""lie# to "ro,i#e' I crease# thro%!h"%t' by e+ec%ti ! a %$ber of #iffere t %ser "rocesses o #iffere t "rocessors i "arallel A""licatio s"ee#%"' by e+ec%ti ! so$e "ortio of the a""licatio i "arallel

Thro%!h"%t ca be i$"ro,e# by e+ec%ti ! a %$ber of % relate# %ser "rocesses o #iffere t "rocessors i "arallel& Syste$ thro%!h"%t is i$"ro,e# as a lar!e %$ber of tas.s are co$"lete# i % it ti$e& A""licatio s"ee#%" $ay be obtai e# by e+"loiti ! the hi##e "arallelis$ i the a""licatio by creati ! $%lti"le threa#s / "rocesses / tas.s for e+ec%tio o #iffere t "rocessors& I ter*"rocessor co$$% icatio a # sy chro i-atio are a o,erhea# i $%lti"rocessor syste$s& 0esi! !oals ai$ to $i i$i-e i ter*"rocessor i teractio a # "ro,i#e a efficie t $echa is$ for carryi ! the$ o%t whe 13&1 ecessary&

A01A(TA2ES O3 MULTIPROCESSORS Perfor$a ce a # co$"%ti ! "ower' Use of $%lti"rocessor syste$s s"ee#s %" a a""licatio & Proble$s with hi!h i ter*"rocessor i teractio ca be sol,e# 4%ic.ly&

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3a%lt tolera ce' The i here t re#% #a cy i $%lti"rocessor syste$s ca be %se# to i crease a,ailability a # eli$i ate si !le "oi t fail%res& 3le+ibility' A $%lti"rocessor syste$ ca be $a#e to #y a$ically reco fi!%re itself so as to o"ti$i-e #iffere t ob5ecti,es for #iffere t a""licatio s s%ch as thro%!h"%t) a""licatio s"ee#%" or fa%lt tolera ce&

Mo#%lar !rowth' Use of a $o#%lar syste$ #esi! o,erco$es certai "roble$s a # ca be acco$"lishe# say by a##i ! e+actly tailor $a#e co$"o e ts s%ch as be a##e# to i$"ro,e "rocessors) $e$ories) I/O #e,ices a # the li.e&

3% ctio al s"eciali-atio ' s"eciali-e# "rocessors ca "erfor$a ce i "artic%lar a""licatio s&

Cost / "erfor$a ce' cost "erfor$a ce ratio i case of $%lti"rocessor syste$s is far below that of lar!e co$"%ters of the sa$e ca"acity a # he ce $%lti"rocessor syste$s are cost effecti,e& They $ay be str%ct%re# si$ilar to lar!e co$"%ters for a wi#e ra !e of a""licatio s&

13&6

MULTIPROCESSOR CLASSI3ICATIO( 3ly classifie# co$"%ter syste$s base# o how the $achi e relates its i str%ctio s to the

#ata bei ! "rocesse#& I str%ctio s $ay for$ either a si !le i str%ctio strea$ or a $%lti"le i str%ctio strea$& Si$ilarly the #ata which the i str%ctio s %se co%l# be either si !le or $%lti"le& 7ase# o s%ch i str%ctio s a # #ata) 3ly serial co$"%ter syste$s& SIM0' si !le i str%ctio strea$) $%lti"le #ata strea$& These are ,ector "rocessors / array "rocessors where a si !le i str%ctio o"erates o #iffere t #ata i #iffere t e+ec%tio % its at the sa$e ti$e& MIS0' $%lti"le i str%ctio strea$s) si !le #ata strea$& M%lti"le i str%ctio s o"erate o a si !le #ata strea$& (ot a "ractical ,iability& classifie# co$"%ter syste$s as follows' SIS0' si !le i str%ctio strea$) si !le #ata strea$& Us%ally fo% # i co ,e tio al

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MIM0' $%lti"le i str%ctio strea$s) $%lti"le #ata strea$& This is the $ost !e eral classificatio where $%lti"le i str%ctio s o"erate o $%lti"le #ata strea$ si$%lta eo%sly& This is the class that co tai s $%lti"rocessors of #iffere t ty"es&

7ase# o the relatio shi"s betwee "rocesses a # $e$ory) $%lti"rocessor syste$s ca be classifie# as' Ti!htly co%"le#' i #i,i#%al "rocessors withi the $%lti"rocessor syste$ share !lobal share# $e$ory& Loosely co%"le#' i #i,i#%al "rocessors withi the $%lti"rocessor syste$ access their ow "ri,ate / local $e$ory& This classificatio $ay ot be ,ery ri!i# a # $%lti"rocessor syste$s ha,e both share# $e$ory as well as local $e$ory& I ter*"rocessor co$$% icatio 8IPC9 a # sy chro i-atio i ti!htly co%"le# $%lti"rocessor syste$s is thro%!h share# $e$ory& Hi!h ba #wi#th a # low #elay i i terco ectio "aths are the $ai characteristics of ti!htly co%"le# $%lti"rocessor syste$s& I loosely co%"le# $%lti"rocessor syste$s) $essa!e "assi ! is the "ri$ary $echa is$ for IPC& 0istrib%te# syste$s fit i to this class of loosely co%"le# syste$s& Lower ba #wi#th a # hi!h #elay i the i terco ectio "aths of the "ast ha,e re#%ce# #rastically with the %se of o"tical fiber li .s a # hi!h s"ee# LA(s& Hybri# syste$s ha,e both local a # !lobal $e$ories& So$e loosely co%"le# syste$s also allow access of !lobal $e$ory i a##itio to local $e$ory& 7ase# o $e$ory a # access #elays) $%lti"rocessor syste$s are classifie# as' U ifor$ $e$ory access 8UMA9' $%lti"le "rocessors ca access all the a,ailable $e$ory with the sa$e s"ee#& (o % ifor$ $e$ory access 8(UMA9' 0iffere t areas of $e$ory ha,e #iffere t access ti$es& This is base# o the ear ess of the $e$ory to a !i,e "rocessor a # also o the co$"le+ity of the switchi ! lo!ic betwee the "rocessor a # the $e$ory& 13&3 (o re$ote $e$ory access 8(ORMA9' syste$s ha,e o share# $e$ory&

MULTIPROCESSOR I(TERCO((ECTIO(S

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The

at%re of $%lti"rocessor i terco ectio s has a

affect o

the ba #wi#th for

co$$% icatio & Co$"le+ity) cost) IPC a # scalability are so$e feat%res co si#ere# i i terco ectio s& 7asic architect%res for $%lti"rocessor i terco ectio s are as follows' 7%s*orie te# syste$s Crossbar*co ecte# syste$s Hy"er c%bes M%ltista!e switch*base# syste$s

13&3&1 7US*ORIE(TE0 SYSTEMS A share# b%s co ects "rocessors a # $e$ory i the $%lti"rocessor syste$ as show below 83i!%re 13&19& P Cache P Cache P Cache P Cache

Share# $e$ory

3i!%re 13&1' Share#*b%s $%lti"rocessor or!a i-atio Processors co$$% icate with each other a # the share# $e$ory thro%!h the share# b%s& 1ariatio s of this basic sche$e are "ossible where "rocessors $ay or $ay ot ha,e local $e$ory) I/O #e,ices $ay be attache# to i #i,i#%al "rocessors or the share# b%s a # the share# $e$ory itself ca ha,e $%lti"le ba .s of $e$ory& The b%s a # the $e$ory bei ! share# reso%rces there is always a "ossibility of co te tio & Cache $e$ory is ofte %se# to release co te tio & Cache associate# with i #i,i#%al "rocessors "ro,i#es a better "erfor$a ce& A :;< cache hit ratio i$"ro,es the s"ee# of the $%lti"rocessor syste$s early 1; ti$es as co$"are# to syste$s witho%t cache&

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E+iste ce of $%lti"le cache i i #i,i#%al "rocessors creates "roble$s& Cache cohere ce is a "roble$ to be a##resse#& M%lti"le "hysical co"ies of the sa$e #ata $%st be co siste t i case of a %"#ate& Mai tai i ! cache cohere ce i creases b%s traffic a # re#%ces the achie,e# s"ee#%" by so$e a$o% t& Use of a "arallel b%s i creases ba #wi#th& The ti!htly co%"le#) share# b%s or!a i-atio %s%ally s%""orts 1; "rocessors& 7eca%se of its si$"le i$"le$e tatio $a y co$$ercial #esi! s of $%lti"rocessor syste$s are base# o share#*b%s co ce"t& 13&3&6 CROSS7AR*CO((ECTE0 SYSTEMS A i terco ectio of "rocessors a # $e$ory i a $%lti"rocessor syste$ %si ! crossbar a""roach is show below 83i!%re 13&69' M; P; P1 M6 M1 M6 M *1

M *1

3i!%re 13&6' Crossbar i terco ectio Si$%lta eo%s access of = > "rocessors a # = > $e$ories is "ossible if each of the "rocessors accesses a #iffere t $e$ory& The crossbar switch is the o ly ca%se of #elay betwee "rocessor a # $e$ory& If o local $e$ory is a,ailable i the "rocessors the the syste$ is a UMA $%lti"rocessor syste$& Co te tio occ%rs whe $ore tha o e "rocessor atte$"ts to access the sa$e $e$ory at the sa$e ti$e& Caref%l #istrib%tio of #ata a$o ! the #iffere t $e$ory locatio s ca re#%ce or eli$i ate co te tio &

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Hi!h #e!ree of "arallelis$ e+ists betwee % relate# tas.s b%t co te tio is "ossible if i ter*"rocess a # i ter*"rocessor co$$% icatio $e$ory) for e+a$"le) se$a"hore& Si ce = > "rocessors a # = > $e$ory locatio s are f%lly co ecte#)
6

a # sy chro i-atio

are base# o

share#

cross "oi ts e+ist&

The 4%a#ratic !rowth of the syste$ $a.es the syste$ e+"e si,e a # li$its scalability& 13&3&3 HYPERCU7ES A 3*#i$e sio al hy"erc%be ca be ,is%ali-e# as show below 83i!%re 13&39' 11; ;1; ;11 111 To"olo!y

1;;

1;1 ;;1

;;; I ter*"rocessor co ectio s

P M ;;;

P M ;;1

P M ;1;

P M ;11

P M 1;;

P M 1;1

P M 11;

P M 111

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3i!%re 13&3' Hy"erc%be i terco ectio C%be to"olo!y has o e "rocessor at each o#e / ,erte+& 2i,e a 3*#i$e tio al c%be 8a hi!her #i$e sio al c%be ca ot be ,is%ali-e#9) 6 3 ? @ "rocessors are i terco ecte#& The res%lt is a (ORMA ty"e $%lti"rocessor a # is a co$$o hy"erc%be i$"le$e tatio & Each "rocessor at a o#e has a #irect li . to lo! 6( o#es where ( is the total %$ber of o#es i the hy"erc%be& 3or e+a$"le) i a 3*#i$e sio al hy"erc%be) ( ? @ a # each o#e is co ecte# to lo!6@ ? 3 o#es& Hy"erc%bes ca be rec%rsi,e str%ct%res with hi!h #i$e sio c%bes co tai i ! low #i$e sio c%bes as "ro"er s%bsets& 3or e+a$"le) a 3*#i$e sio al c%be has two 6* #i$e sio al c%bes as s%bsets& Hy"erc%bes ha,e a !oo# basis for scalability si ce co$"le+ity !rows lo!arith$ically where as it is 4%a#ratic i the "re,io%s case& They are best s%ite# for "roble$s that $a" o to a c%be str%ct%re) those that rely o rec%rsio or e+hibit locality of refere ce i the for$ of fre4%e t co$$% icatio with a#5ace t o#es& Hy"erc%bes for$ a "ro$isi ! basis for lar!e*scale $%lti"rocessors& Messa!e "assi ! is %se# for i ter*"rocessor co$$% icatio re"ositories of #ata for cl%sters of o#es& 13&3&A MULTISTA2E SBITCH*7ASE0 SYSTEMS Processors a # $e$ory i a $%lti"rocessor syste$ ca be i terco ecte# by %se of a $%ltista!e switch& A !e erali-e# ty"e of i terco ectio li .s ( i "%ts a # ( o%t"%ts thro%!h lo! 6( sta!es) each sta!e ha,i ! ( li .s to ( / 6 i tercha !e bo+es& The str%ct%re of a $%ltista!e switch etwor. is show below 83i!%re 13&A9' a # sy chro i-atio & I crease# ba #wi#th is so$eti$es "ro,i#e# thro%!h #e#icate# o#es that act as so%rces /

P; P1 P6 P3 PA PC PD PE

M; M1 M6 M3 MA MC MD ME

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3i!%re 13&A' M%ltista!e switchi ! etwor. The etwor. has lo!6( ? lo!663 ? 3 sta!es of ( / 6 ? @ / 6 ? A switches each& Each switch is a 6+6 crossbar that ca #o a yo e of the followi !' Co"y i "%t to o%t"%t Swa" i "%t a # o%t"%t Co"y i "%t to both o%t"%t

Ro%ti ! is fi+e# a # is base# o the #esti atio a##ress a # the so%rce a##ress& I !e eral to !o fro$ so%rce S to #esti atio 0 the i th sta!e switch bo+ i the "ath fro$ S to 0 sho%l# be set to swa" if Si 0i a # set to strai!ht if Si ? 0i& Ill%stratio ' If S ? ;;; a # 0 ? ;;; the Si ? 0i for all bits& Therefore all switches are strai!ht& If S ? ;1; a # 0 ? 1;; the S 1 01 ) S6 06 a # S3 ? 03& Therefore switches i the first two sta!es sho%l# be set to swa" a # the thir# to strai!ht& M%ltista!e switchi ! etwor. "ro,i#es a for$ of circ%it switchi ! where traffic ca flow freely %si ! f%ll ba #wi#th whe bloc.s of $e$ory are re4%este# at a ti$e& All i "%ts ca be co ecte# to all o%t"%ts "ro,i#e# each "rocessor is accessi ! a #iffere t $e$ory& Co te tio at the $e$ory $o#%le or withi the i terco ectio co te tio to so$e e+te t& 13&A TYPES O3 MULTIPROCESSOR OPERATI(2 SYSTEMS Three basic ty"es of $%lti"rocessor o"erati ! syste$s are' Se"arate s%"er,isors Master / sla,e Sy$$etric etwor. $ay occ%r& 7%fferi ! ca relie,e

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13&A&1 SEPARATE SUPER1ISORS I se"arate s%"er,isor syste$s) each o#e is a "rocessor ha,i ! a se"arate o"erati ! syste$ with a $e$ory a # I/O reso%rces& A##itio of a few a##itio al ser,ices a # #ata str%ct%res will hel" to s%""ort as"ects of $%lti"rocessors& A co$$o e+a$"le is the hy"erc%be& 0%e to their re!%lar re"eati ! str%ct%re co str%cte# of i#e tical b%il#i ! bloc.s) they te # to re"licate i#e tical co"ies of a .er el i each o#e& Fer el "ro,i#es ser,ices s%ch as local "rocess) $e$ory $a a!e$e t a # $essa!e "assi ! "ri$iti,es& Parallelis$ is achie,e# by #i,i#i ! a a""licatio i to s%btas.s that e+ec%te o #iffere t o#es& 13&A&6 MASTER / SLA1E I this a""roach) o e "rocessor G the $aster is #e#icate# to e+ec%te the o"erati ! syste$& The re$ai i ! "rocessors are sla,es a # for$ a "ool of co$"%tatio al "rocessors& The $aster sche#%les a # co trols the sla,es& This arra !e$e t allows "arallelis$ i a a""licatio by allocati ! to it $a y sla,es& Master / sla,e syste$s are easy to #e,elo"& A % i"rocessor o"erati ! syste$ ca be a#a"te# for $aster / sla,e $%lti"rocessor o"eratio s with the a##itio of sla,e sche#%li !& S%ch syste$s ha,e li$ite# scalability& Ma5or #isa#,a ta!es are that co$"%tatio al "ower of a whole "rocessor is #e#icate# for co trol acti,ity o ly a # if the $aster fails) the e tire syste$ is #ow & 13&A&3 SYMMETRIC All "rocessors are f% ctio ally i#e tical& They for$ a "ool of reso%rces& Other reso%rces s%ch as $e$ory a # I/O #e,ices are a,ailable to all "rocessors& If they are a,ailable to o ly a few the the syste$ beco$es asy$$etric& The o"erati ! syste$ is also sy$$etric& A y "rocessor ca e+ec%te it& I res"o se to wor.loa# re4%ire$e ts a # "rocessor a,ailability) #iffere t "rocessors e+ec%te the o"erati ! syste$ at #iffere t ti$es& That "rocessor which e+ec%tes the o"erati ! syste$ te$"orarily is the $aster 8also calle# floati ! $aster9&

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A e+isti ! % i"rocessor o"erati ! syste$ s%ch as U(IH ca easily be "orte# to a share# $e$ory UMA $%lti"rocessor& Share# $e$ory co tai s the resi#e t o"erati ! syste$ co#e a # #ata str%ct%res& A y "rocessor ca e+ec%te the o"erati ! syste$& Parallel e+ec%tio of a""licatio s is "ossible %si ! a rea#y 4%e%e of "rocesses i share# $e$ory& The e+t rea#y "rocess to the e+t a,ailable "rocessor % til either all "rocessors are b%sy / 4%e%e is e$"ty co%l# be a "ossible allocatio sche$e& Co c%rre t access of share# #ata str%ct%res "ro,i#es "arallelis$& 13&C MULTIPROCESSOR OPERATI(2 SYSTEM 3U(CTIO(S A(0 REIUIREME(TS M%lti"rocessor o"erati ! syste$s $a a!e a,ailable reso%rces to facilitate "ro!ra$ e+ec%tio a # i teractio with %sers& Reso%rces to be $a a!e# i cl%#e' to' Allocate "rocessors a$o ! a""licatio s E s%re efficie t %se of "rocessors allocate# to a a""licatio & Processors Me$ory I/O #e,ices

Processor sche#%li ! is cr%cial for efficie t %se of $%lti"le "rocessors& The sche#%ler has

A tra#eoff e+ists betwee the two& The for$er affects thro%!h"%t while the latter affects s"ee#%"& 0e"e #i ! o a a""licatio if s"ee#%" is !i,e "riority the a lar!e "ortio of the "rocessors is #e#icate# to the a""licatio & O the other ha # if thro%!h"%t is to be i crease# the se,eral a""licatio s are sche#%le# each a,aili ! fewer "rocessors& The two $ai facets of o"erati ! syste$ s%""ort for $%lti"rocessor are' 3le+ible a # efficie t i ter*"rocess a # i ter*"rocessor sy chro i-atio $echa is$s& Efficie t creatio a # $a a!e$e t of a lar!e %$ber of threa#s / "rocesses&

Me$ory $a a!e$e t i $%lti"rocessor syste$s is #e"e #e t o the architect%re a # i terco ectio sche$e& I loosely co%"le# syste$s) $e$ory $a a!e$e t is %s%ally i #e"e #e t& I share# $e$ory syste$) o"erati ! syste$ sho%l# "ro,i#e access to share# #ata str%ct%res a # sy chro i-atio ,ariables i a safe a # efficie t way& A har#ware i #e"e #e t % ifie# $o#el of a

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share# $e$ory for easy "ortability is e+"ecte# of a $%lti"rocessor o"erati ! syste$& A % ifie# $e$ory $o#el co sisti ! of $essa!es a # share# $e$ory "ro,i#es a fle+ible tool& 0e,ice $a a!e$e t is of little i$"orta ce i a $%lti"rocessor o"erati ! syste$& This $ay be #%e to the i$"orta ce attache# to s"ee#%" i the so calle# co$"%te*i te si,e a""licatio s with $i i$al I/O& As $ore !e eral "%r"ose a""licatio s are r% o $%lti"rocessor syste$s) I/O re4%ire$e ts will also be a $atter of co cer alo ! with thro%!h"%t a # s"ee#& 13&D OPERATI(2 SYSTEM 0ESI2( A(0 IMPLEME(TATIO( ISSUES So$e $a5or iss%es i ,ol,e# i "rocessor a # $e$ory $a a!e$e t i $%lti"rocessor o"erati ! syste$s are #escribe# below' 13&D&1 PROCESSOR MA(A2EME(T A(0 SCHE0ULI(2 The $ai iss%es i "rocessor $a a!e$e t i cl%#e' S%""ort for $%lti"rocessi ! Allocatio of "rocessi ! reso%rces Sche#%li !

The o"erati ! syste$ ca s%""ort $%lti"rocessors by "ro,i#i ! a $echa is$ for creati ! a # $ai tai i ! a %$ber of "rocesses / threa#s& Each "rocess has allocate# reso%rces) state a # accesses I/O #e,ices& A a""licatio ha,i ! se,eral co*o"erati ! "rocesses ca be ,iewe# as a ,irt%al $%lti"rocessor& I a $%lti"rocessor e ,iro $e t tr%e $%lti"rocessi ! is "ossible by allocati ! a "hysical "rocessor to each ,irt%al "rocessor where as i a % i"rocessor syste$ a ill%sio of $%lti"rocessi ! is create# by $%lti"le+i ! the "rocessor a$o ! ,irt%al "rocesses& Bhe threa#s are %se#) each a""licatio is i$"le$e te# as a "rocess& Its co c%rre t "ortio s are co#e# as se"arate threa#s withi the e closi ! "rocess& Threa#s of a si !le "rocess share $e$ory a # reso%rces ac4%ire# by the "rocess& Threa#s ot o ly facilitate $%lti"rocessors bot also hel" the sche#%li ! "rocess& Relate# threa#s co%l# be co*sche#%le# to re#%ce slow#ow associate# with the o%t*of*"hase sche#%li !&

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Processor allocatio creates "roble$s i $assi,ely "arallel syste$s& O e way of .ee"i ! trac. of "rocessor reso%rces is to or!a i-e the$ i to a hierarchy& A "rocessor at the hi!hest le,el i the hierarchy otes state a # acti,ity of a !ro%" of "rocessors& Bhe a a""licatio is to be allocate# the$ the i#le $achi es at the botto$ le,el !et allocate#& The hierarchy ca !row %"war#s& This is calle# wa,e sche#%li !& If wa te# %$ber of reso%rces is ot a,ailable the a re4%est to a hi!her le,el i the hierarchy is $a#e& 3a%lt tolera ce is "ossible as a "rocess hi!her %" i the hierarchy co%l# reallocate acti,ities of a faile# "rocessor to a other& 7%t i$"le$e tatio has "ractical #iffic%lties s%ch as a ote of wro ! a,ailability& Processors are allocate# to a""licatio s& These ha,e to be sche#%le#& O e $ai ob5ecti,e is to co*sche#%le "rocesses that i teract so that they r% at the sa$e ti$e& Processes that ca be co*sche#%le# i cl%#e se,eral threa#s of a si !le "rocess) se #er a # recei,er of a $essa!e) "rocesses at the e # of a "i"e) etc& I #i,i#%al "rocesses $ay be % i"ro!ra$$e# or $%lti"ro!ra$$e#& Si ce $%lti"ro!ra$$i ! of i #i,i#%al "rocesses creates "roble$s for co$$% icatio ) co*sche#%li ! "rocess !ro%"s that co$$% icate with each other are "referre#& I loosely co%"le# syste$s the sche#%ler sho%l# ote affi ity of so$e "rocesses for certai "rocessors that $ay be #%e to "rocess state store# i local $e$ory& Also "laci ! i teracti ! "rocesses i the sa$e "rocessor or cl%ster with #irect i ter"rocessor li .s ca re#%ce co$$% icatio costs& 13&D&6 MEMORY MA(A2EME(T I ti!htly co%"le# $%lti"rocessor syste$s the o"erati ! syste$ $%st "ro,i#e access to share# $e$ory thro%!h "ri$iti,es for allocatio a # reallocatio of share# $e$ory se!$e ts& If share# ,irt%al $e$ory is s%""orte# the tra slatio loo. asi#e b%ffers 8TL7s9 co tai $a""i !s to share# se!$e ts& Si$ilarly o"e files co%l# also be share#& Use of share# $e$ory i$"ro,es "erfor$a ce of $essa!e "assi !& 13&E SUMMARY

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Be ha,e st%#ie# the a#,a ta!es of %si ! $%lti"rocessor syste$s a # their classificatio & Be ha,e also st%#ie# the #iffere t sta #ar# i terco ectio "atter s of $%lti"rocessor syste$s a # ty"es of $%lti"rocessor e ,iro $e ts li.e s%"er,isors a # $aster / sla,e& The cha"ter bri !s o%t the f% ctio s) re4%ire$e ts) a # #esi! a # i$"le$e tatio iss%es of $%lti"rocessor syste$s&

13&@

EHERCISE 1& 6& 3& A& C& List the a#,a ta!es of $%lti"rocessor syste$s& How ca $%lti"rocessors be classifie#J E+"lai the ,ario%s $%lti"rocessor i terco ectio s& 0escribe the basic ty"es of $%lti"rocessor o"erati ! syste$s& 0isc%ss the ,ario%s iss%es for $%lti"rocessor o"erati ! syste$ #esi! &

13&:

ACTI1ITY 3i # o%t if the o"erati ! syste$s ote# are $%lti"rocessor syste$s& If so st%#y their ty"es

a # i terco ectio s&