1)A NOR gate is ON only when all its inputs are A. B. C. D.

ON positive high OFF

Q.2) The number system that we use in our day to day life is called the Number System A. B. C. D. Octal !inary "e#adecimal $ecimal

Q.3) The three logical operations% which are said to be logically &omplete% as any !oolean function may be reali'ed using these Three operations are( A. B. C. D. Q.4) A. B. C. D. Q.5) AN$% OR and NOT AN$% OR and )OR AN$% OR and NAN$ )OR% NOR and NAN$ *ictorial representation of !oolean algebra is +nown as ,enn $iagram Flow &hart $ata Flow $iagram Truth Table $evice or &ircuit whose output will remain unchanged once set FlipFlop .ate !oolean Algebra

A. B. C.

Q.6) ///0Are used for converting one type of number system in to other form A. B. C. 1ncoder logic gate half adder

D.

FA

Q.7) 2n a 3nd complement a number which is subtracted from other number is +nown as///00 A. B. C. D. &arry Subtrahend 4inuend None of these

9. The voltage drop across a silicon se icond!ctor is" 5v - 6v 0 705v - 706v 0 7075v - 7076v0 57mv - 67mv 0

#6. The electrical s$ %ol ill!strated %elo& represents a"

OR gate0

AN$ gate0

NOR .ate0

NAN$ .ate0

#7. The electrical s$ %ol ill!strated %elo& represents a"

OR gate0

O*-A4*0

NOR .ate0

NOT .ate0

#'. The electrical s$ %ol ill!strated %elo& represents an"

OR gate0

O*-A4*0

NOR .ate0

NOT .ate0

#9. (or the electrical s$ %ol ill!strated %elo& to represent )*) as it+s o!tp!t, the inp!ts !st %e"

one input 8on8 the other 8off80 both inputs 8off80

both inputs 8on80

first input 8off8 the second 8on80

2*. (or the electrical s$ %ol ill!strated %elo& to represent )*) as it+s o!tp!t, the inp!ts !st %e"

one input 818 the other 8780 both inputs 8780

both inputs 8180 the top input 878% the bottom input 8180

2#. (or the electrical s$ %ol ill!strated %elo& to represent )#) as it+s o!tp!t, the inp!ts !st %e"

one input 818 the other 8780 both inputs 8780

both inputs 8180 the top input 878% the bottom input 81800 !st %e"

22. -n order .or o!tp!t +/+ to %e a)#), inp!ts A, B, and C

A91% !97% &970

A97% !97% &970

A91% !97% &910

A97% !91% &970

2n the decimal numbering system% what is the 4S$: A0The middle digit of a stream of numbers !0The digit to the right of the decimal point &0The last digit on the right

$0The digit with the most weight ;hen used with an 2&% what does the term 8<=A$8 indicate: A03 circuits !0> circuits &0? circuits $0@ circuits 2f a signal passing through a gate is inhibited by sending a AO; into one of the inputs% and the output is "2."% the gate is aBn)( A0AN$ &0NOR !0NAN$ $0OR

2mplementing the e#pression A! C &$1 using NAN$ logic% we get(

A0BA) &0B&)

!0B!) $0B$) would reDuire a total of

!efore an SO* implementation% the e#pression how many gates: A01 &0> !03 $05

A >-variable AN$-OR-2nvert circuit produces a 7 at its E output0 ;hich combination of inputs is correct: A0 !0 &0 $0none of the above The inverter can be produced with how many NAN$ gates: A01 &0F !03 $0>

A >-variable AN$-OR circuit produces a 1 at its E output0 ;hich combination of inputs is correct: A0A 9 7% ! 9 7% & 9 7% $ 9 7 !0A 9 7% ! 9 1% & 9 1% $ 9 7 &0A 9 1% ! 9 1% & 9 7% $ 9 7 $0A 9 1% ! 9 7% & 9 7% $ 9 7

One possible output e#pression for an AN$-OR-2nvert circuit having one AN$ gate with inputs A% !% and & and one AN$ gate with inputs $ and 1 is 0 A0 !0 &0 $0

"ow many flip-flops are reDuired to produce a divide-by-13@ device: A01 &0? !0> $06

One e#ample of the use of an S-R flip-flop is as aBn)(

A0racer !0astable oscillator &0binary storage register $0transition pulse generator ;hen is a flip-flop said to be transparent: A0when the Q output is opposite the input !0when the Q output follows the input &0when you can see through the 2& pac+aging ;hich of the following is correct for a $ latch: A0The output toggles if one of the inputs is held "2."0 !0 Q output follows the input D when the enable is "2."0 &0Only one of the inputs can be "2." at a time0 $0The output complement follows the input when enabled0 ;hich of the following is not generally associated with flip-flops: A0"old time !0*ropagation delay time &02nterval time $0Set up time Select the statement that best describes the parity method of error detection( *arity chec+ing is best suited for detecting double-bit errors that occur during the transmission of codes from one location to another0 !0*arity chec+ing is not suitable for detecting single-bit errors in transmitted codes0 &0*arity chec+ing is best suited for detecting single-bit errors in transmitted codes0 $0*arity chec+ing is capable of detecting and correcting errors in transmitted codes0 A0 ;hy is an e#clusive-NOR gate also called an eDuality gate: A0The output is false if the inputs are eDual0 !0The output is true if the inputs are opposite0 &0The output is true if the inputs are eDual0