6809 Instruction Set

6809 Instruction Set Addressing Mode Immediate Direct Indexed Extended Inherent Instruction Mnemonic Op ~ # Op ~ # Op ~ # Op ~ # Op ~ # Description ABX 3A 3 1 X = B+X (Unsigned) ADC ADCA ADCB ADDA ADDB ADDD ANDA ANDB ANDCC ASLA ASLB ASL ASRA ASRB ASR BITA BITB CLRA CLRB CLR CMPA CMPB CMPD CMP CMPS CMPU CMPX CMPY COM CWAI DAA DEC DECA DECB DEC EORA EORB R1,R2 COMA COMB COM 3C => 2 20 89 C9 8B CB C3 84 C4 1C 2 2 2 2 4 2 2 3 2 99 4 2 A9 4+ 2+ B9 2 2 2 3 2 2 2 D9 9B DB D3 94 D4 4 2 E9 4 2 AB 4 2 EB 6 2 E3 4 2 A4 4 2 E4 4+ 4+ 4+ 6+ 4+ 4+ 2+ 2+ 2+ 2+ 2+ 2+ F9 BB FB F3 B4 F4 5 3 5 5 5 7 5 5 3 3 3 3 3 3 48 2 1 58 2 1 08 6 2 68 6+ 2+ 78 7 3 47 2 1 57 2 1 85 2 C5 2 07 6 2 67 6+ 2+ 77 7 3 2 95 4 2 A5 4+ 2+ B5 5 3 2 D5 4 2 E5 4+ 2+ F5 5 3 A = A+M+C B = B+M+C A = A+M B = B+M D = D+M:M+1 A = A && M B = B && M C = CC && IMM Arithmetic shift left Arithmetic shift right

CC bit 5 3 2 1 0 HNZVC + + + + + + + + + + + + + ? + + + + + + + + 0 0 0 + + ++ ++ ++ ++ ++ ++ +0 +0 ? ? + + + + + + + + + +0 +0 1 0 1 0 1 0 ++ ++ + + + + + +

ADD

AND

ASL

ASR

? 8 8 8 8 8 8

? + + + + + +

BIT

CLR

81 C1 10 83 11 8C 11 83 8C 10 8C

2 2 5 5 5 4 5

2 2 4 4 4 3 4

0F 91 D1 10 93 11 9C 11 93 9C 10 9C

6 4 4 7 7 7 6 7

2 6F 2 A1 2 E1 3 10 A3 3 11 AC 3 11 A3 2 AC 3 10 AC

6+ 4+ 4+ 7+

2+ 2+ 2+ 3+

7+ 3+ 7+ 3+ 6+ 2+ 7+ 3+

7F B1 F1 10 B3 11 BC 11 B3 BC 10 BC

Bit Test A (M&&A) Bit Test B (M&&B) 4F 2 1 A = 0 5F 2 1 B = 0 7 3 M=0 5 3 Compare M from A 8 5 3 Compare M from B 8 8 4 Compare M:M+1 from D + + + Compare M:M+1 from S Compare M:M+1 from U Compare M:M+1 from X Compare M:M+1 from Y 43 2 1 A = complement(A) 53 2 1 B = complement(B) M = complement(M) CC = CC ^ IMM; Wait for Interrupt 19 2 1 Decimal Adjust A 4A 2 1 A = A 1 5A 2 1 B = B 1 M=M1 A = A XOR M B = M XOR B exchange R1,R2

0 0 0 + + +

8 4 8 4 7 3 8 4

+ + + + + + + + + + + + + + + + + + 0 1 + + 0 1 + + 0 1 7 + + + + + + + + + + + + 0 + + + + 0 0

03 6 2 63 6+ 2+ 73 7 3

EOR EXG

88 2 C8 2 1E 8

0A 6 2 6A 6+ 2+ 7A 7 3 2 98 4 2 A8 4+ 2+ B8 5 3 2 D8 4 2 E8 4+ 2+ F8 5 3 2

6809 Instruction Set

INC JMP JSR

INCA INCB INC

4C 2 1 A = A + 1 5C 2 1 B = B + 1 0C 6 2 6C 6+ 2+ 7C 7 3 M=M+1 0E 3 2 6E 3+ 2+ 7E 4 3 pc = EA 9D 7 2 AD 7+ 2+ BD 8 3 jump to subroutine

+ + + + + + + + +

6809 Instruction Set Addressing Mode Immediate Direct Indexed Extended Inherent Instruction Mnemonic Op ~ # Op ~ # Op ~ # Op ~ # Op ~ # LDA 86 2 2 96 4 2 A6 4+ 2+ B6 5 3 LDB C6 2 2 D6 4 2 E6 4+ 2+ F6 5 3 LDD CC 3 3 DC 5 2 EC 5+ 2+ FC 6 3 10 4 4 10 6 3 10 6+ 3+ 10 7 4 LDS LD CE DE EE FE LDU CE 3 3 DE 5 2 EE 5+ 2+ FE 6 3 LDX 8E 3 3 9E 5 2 AE 5+ 2+ BE 6 3 10 4 4 10 6 3 10 6+ 3+ 10 7 4 LDY 8E 9E AE BE LEAS 32 4+ 2+ LEAU 33 4+ 2+ LEA LEAX 30 4+ 2+ LEAY 31 4+ 2+ LSLA 48 2 1 LSL LSLB 58 2 1 LSL 08 6 2 68 6+ 2+ 78 7 3 LSRA 44 2 1 LSR LSRB 54 2 1 LSR 04 6 2 64 6+ 2+ 74 7 3 MUL 3D 11 1 NEGA 40 2 1 NEG NEGB 50 2 1 NEG 00 6 2 60 6+ 2+ 70 7 3 NOP 12 2 1 ORA 8A 2 2 9A 4 2 AA 4+ 2+ BA 5 3 OR ORB CA 2 2 DA 4 2 EA 4+ 2+ FA 5 3 ORCC 1A 3 2 PSHS 34 5+ 2 PSH PSHU 36 5+ 2 PULS 35 5+ 2 PUL PULU 37 5+ 2 ROLA 49 2 1 ROL ROLB 59 2 1 ROL 09 6 2 69 6+ 2+ 79 7 3 RORA 46 2 1 ROR RORB 56 2 1 ROR 06 6 2 66 6+ 2+ 76 7 3

Description A=M B=M D = M:M+1 S = M:M+1 U = M:M+1 X = M:M+1 Y = M:M+1 S = EA U = EA X = EA Y = EA Logical shift left Logical shift right D = A*B (Unsigned) A = !A + 1 B = !B + 1 M = !M + 1 No Operation A = A || M B = B || M C = CC || IMM Push Registers on S Stack Push Registers on U Stack Pull Registers from S Stack Pull Registers from U Stack Rotate left thru carry

CC bit 5 3 21 0 HNZV C + +0 + +0 ++ 0 ++ 0 ++ 0 ++ 0 ++ 0

+ + + 0 0 0 8 + 8 + 8 +

+ + + + + + + + + + + +

+ + + + + + + + + 9 + + + + + +

+ +0 + +0 ? ? ? ? ?

Rotate Right thru carry

+ + + 0 0 0

+ + + + + + + + + + + + + + +

6809 Instruction Set

RTI RTS SBC SEX STA STB STD ST STS STU STX STY SUB SUBA SUBB SUBD SWI SWI2 SWI3 SYNC TFR TST R1,R2 TSTA TSTB TST 1F 6 2 80 2 C0 2 83 4 97 4 2 A7 D7 4 2 E7 DD 5 2 ED 10 6 3 10 DF EF DF 5 2 EF 9F 5 2 AF 10 6 3 10 9F AF 2 90 4 2 A0 2 D0 4 2 E0 3 93 6 2 A3 4+ 4+ 5+ 6+ 2+ 2+ 2+ 3+ B7 F7 FD 10 FF FF BF 10 BF B0 F0 B3 5 5 6 7 3 3 3 4 SBCA SBCB 82 2 C2 2 2 92 4 2 A2 4+ 2+ B2 5 3 2 D2 4 2 E2 4+ 2+ F2 5 3

3B 6/15 1 39 5 1

1D 2 1

Return from Interrupt Return from subroutine A=A-M-C B=B-M-C Sign extend B into A M=A M=B M:M+1 = D M:M+1 = S M:M+1 = U M:M+1 = X M:M+1 = Y A=A-M B=B-M D = D - M:M+1 Software interrupt 1 Software interrupt 2 Software interrupt 3 Synchronize to Interrupt R2 = R1 Test A Test B Test M

? ? ? ? ? 8 + ++ + 8 + ++ + ++ 0 + +0 + +0 ++ 0 ++ 0 ++ 0 ++ 0 ++ 0 8 ++ + + 8 ++ + + ++ + +

5+ 2+ 5+ 2+ 6+ 3+ 4+ 2+ 4+ 2+ 6+ 2+

6 3 6 3 7 4 5 3 5 3 7 3 3F 19 10 20 3F 11 20 3F >= 13 4 1 2 2 1

SWI

4D 2 1 5D 2 1 0D 6 2 6D 6+ 2+ 7D 7 3

++ 0 ++ 0 ++ 0

: Legend: ! Complement of M = Transfer from H Halfcarry (from bit 3) N Negative (sign bit) Z Zero (Reset) V Overflow, 2's complement C Carry from ALU + Test and set if true, cleared otherwise - Not Affected CC Condition Code Register : Concatenation || Logical or && Logical and EOR Logical Exclusive or OP Operation Code(Hexadecimal) ~ Number of MPU Cycles # Number of Program Bytes + Arithmetic Plus Arithmetic Minus * Multiply EA Effective Address:w

:Notes 1. This column gives a base cycle and byte count. To obtain total count,
add the values obtained from the INDEXED ADDRESSING MODE table,
in Appendix F. 2. Rl and R2 may be any pair of 8 bit or any pair of 16 bit registers.
The 8 bit registers are: A, B, CC, DP

6809 Instruction Set

The 16 bit registers are: X, Y, U, S, D, PC 3. EA is the effective address. 4. The PSH and PUL instructions require 5 cycles plus 1 cycle for each byte
pushed or pulled. 5. 5(6) means: 5 cycles if branch not taken, 6 cycles if taken (Branch
instructions. 6. SWI sets I and F bits. SW12 and SW13 do not affect I and F. 7. Conditions Codes set as a direct result of the instruction. 8. Value of halfcarry flag is undefined. 9. Special Case Carry set if b7 is SET.