Intel Microprocessors: 8008 to 8086

Stephen P. Morse / Bruce W Ravenel / Stanley Mazor / William B. Pohlman

Originally published in I !omputer" #ol $%" &o. $'" pages ()*+'" October $,-' Reprinted in !omputer Structures" pages +$.*+(+" Sie/iore0/Bell/&e/ell" $,-) I. Introduction

1In the beginning Intel created the (''( and the -''-.1 A. The Prophecy Intel introduced the microprocessor in &ovember $,2$ /ith the advertisement" 13nnouncing a &e/ ra in Integrated lectronics.1 4he 5ul5illment o5 this prophecy has already occurred /ith the delivery o5 the -''- in $,2)" the -'-' in $,2(" the -'-. in $,2+" and the -'-+ in $,2-. 6uring this time" throughput has improved $''*5old" the price o5 a !P7 chip has declined 5rom 8%'' to 8%" and microcomputers have revolutionized design concepts in countless applications. 4hey are no/ entering our homes and cars. ach successive product implementation depended on semiconductor process innovation" improved architecture" better circuit design" and more sophisticated so5t/are" yet up/ard compatibility not envisioned by the 5irst designers /as maintained. 4his paper provides an insight into the evolutionary process that trans5ormed the -''- into the -'-+" and gives descriptions o5 the various processors" /ith emphasis on the -'-+. B. Historical Setting In the late $,+'s it became clear that the practical use o5 large*scale integrated circuits 9:SI; depended on de5ining chips having <igh gate*to*pin ratio Regular cell structure :arge standard*part mar0ets In $,+-" Intel !orporation /as 5ounded to e=ploit the semiconductor memory mar0et" /hich uni>uely 5ul5illed these criteria. arly semiconductor R3Ms" ROMs" and shi5t registers /ere /elcomed /herever small memories /ere needed" especially in calculators and !R4 terminals" In $,+," Intel engineers began to study /ays o5 integrating and partitioning the control logic 5unctions o5 these systems into :SI chips. 3t this time other companies 9notably 4e=as Instruments; /ere e=ploring /ays to reduce the design time to develop custom integrated circuits usable in a customer?s application. !omputer*aided design o5 custom I!s /as a hot issue then. !ustom I!s are ma0ing a

comebac0 today" this time in high*volume applications /hich typi5y the lo/ end o5 the microprocessor mar0et. 3n alternate approach /as to thin0 o5 a customer?s application as a computer system re>uiring a control program" I/O monitoring" and arithmetic routines" rather than as a collection o5 special*purpose logic chips. @ocusing on its strength in memory" Intel partitioned systems into R3M" ROM" and a single controller chip" the central processor unit 9!P7;. Intel embar0ed on the design o5 t/o customer*sponsored microprocessors" the (''( 5or a calculator and the -''- 5or a !R4 terminal. 4he (''(" in particular" replaced /hat /ould other/ise have been si= customized chips" usable by only one customer" Because the 5irst microcomputer applications /ere 0no/n" tangible" and easy to understand" instruction sets and architectures /ere de5ined in a matter o5 /ee0s. Since they /ere programmable computers" their uses could be e=tended inde5initely. Both o5 these 5irst microprocessors /ere complete !P7s*on*a*chip and had similar characteristics. But because the (''( /as designed 5or serial B!6 arithmetic /hile the -''- /as made 5or -*bit character handling" their instruction sets /ere >uite di55erent. 4he succeeding years sa/ the evolutionary process that eventually led to the -'-+. 4able $ summarizes the progression o5 5eatures that too0 place during these years. Table 1 Feature Comparison -''&umber o5 instructions &umber o5 5lags Ma=imum memory size I/O ports &umber o5 pins 3ddress bus /idth 6ata bus /idth 6ata types ++ ( $+A bytes - input )( output $-B -B -*bit unsigned $+ -*bit unsigned $+*bit unsigned -'-' $$$ . +(A bytes ).+ input ).+ output (' -'-. $$% . +(A bytes ).+ input ).+ output (' $+ -*bit unsigned $+*bit unsigned -'-+ $%% , $ M bytes +(A input +(A output (' $+B $+B -*bit unsigned -*bit signed

9limited; Pac0ed B!6 9limited; 3ddressing modes Register C Immediate Memory direct 9limited; Memory indirect 9limited; Register C Immediate $,2(

9limited; Pac0ed B!6 9limited; Memory direct 9limited; Memory indirect 9limited; Register C Immediate $,2+

$+*bit unsigned $+*bit signed Pac0ed B!6 7npac0ed B!6 Memory direct Memory indirect Register Immediate Inde=ing $,2-

Introduction date

$,2)

B 3ddress and data bus multiple=ed. C Memory can be addressed as a special case by using register M. II. 8008 Objectives and Constraints :ate in $,+, Intel !orporation /as contracted by !omputer 4erminal !orporation 9today called 6atapoint; to do a pushdo/n stac0 chip 5or a processor to be used in a !R4 terminal. 6atapoint had intended to build a bit*serial processor in 44: logic using shi5t* register memory. Intel counterproposed to implement the entire processor on one chip" /hich /as to become the -''-. 4his processor" along /ith the (''(" /as to be 5abricated using the then*current memory 5abrication technology" p*MOS. 6ue to the long lead time re>uired by Intel" !omputer 4erminal proceeded to mar0et the serial processor and thus compatibility constraints /ere imposed on the -''-. Most o5 the instruction*set and register organization /as speci5ied by !omputer 4erminal. Intel modi5ied the instruction set so the processor /ould 5it on one chip and added instructions to ma0e it more general*purpose. @or although Intel /as developing the -''- 5or one particular customer" it /anted to have the option o5 selling it to others. Intel /as using only $+* and $-*pin pac0ages in those days" and rather than re>uire a ne/ pac0age 5or /hat /as believed to be a lo/*volume chip" they chose to use $- pins 5or the -''-. III. 8008 Instruction- et !rocessor 4he -''- processor architecture is >uite simple compared to modern*day microprocessors. 4he data*handling 5acilities provide 5or byte data only. 4he memory space is limited to $+A bytes" and the stac0 is on the chip and limited to a depth o5 -. 4he instruction set is small but symmetrical" /ith only a 5e/ operand*addressing modes available. 3n interrupt mechanism is provided" but there is no /ay to disable interrupts.

A. Memory and I/O Structure 4he -''- addressable memory space consists o5 $+A bytes. 4hat seemed li0e a lot bac0 in $,2'" /hen memories /ere e=pensive and :SI devices /ere slo/. It /as inconceivable in those days that anybody /ould /ant to put more than $+A o5 this precious resource on anything as slo/ as a microprocessor. 4he memory size limitation /as imposed by the lac0 o5 available pins. 3ddresses are sent out in t/o consecutive cloc0 cycles over an -*bit address bus. 4/o control signals" /hich /ould have been on dedicated pins i5 these had been available" are sent out together /ith every address" thereby limiting addresses to $( bits. 4he -''- provides eight -*bit input ports and t/enty*5our -*bit output ports. ach o5 these ports is directly addressable by the instruction set. It /as 5elt that output ports /ere more important than input ports because input ports can al/ays be multiple=ed by e=ternal hard/are under control o5 additional output ports. One o5 the interesting things about that era /as that" 5or the 5irst time" the users /ere given access to the memory bus and could de5ine their o/n memory structureD they /ere not con5ined to /hat the vendors o55ered" as they had been in the minicomputer era. 3s an e=ample" the user had the option o5 putting I/O ports inside the memory address space instead o5 in a separate I/O space. B. Register Structure 4he -''- processor contains t/o register 5iles and 5our $*bit 5lags. 4he register 5lies are re5erred to as the scratchpad and the address stac0. 1. cratc"pad. The scratchpad file contains an 8-bit accumulator called A and six additional 8bit registers called B,C,D,E,H, and . All arithmetic operations use the accumulator as one of the operands and store the result bac! in the accumulator. All se"en registers can be used interchangeabl# for on-chip temporar# storage. There is one pseudo-register, $, %hich can be used inter changeabl# %ith the scratchpad registers. $ is, in effect, that particular b#te in memor# %hose address is currentl# contained in H and & contains the eight lo%-order bits of the address and H contains the six high-order bits'. Thus $ is a b#te in memor# and not a register( although instructions address $ as if it %ere a register, accesses to $ actuall# in"ol"e memor# references. The $ register is the onl# mechanism b# %hich data in memor# can be accessed.

#. $ddress tac%. The address stac! contains a )-bit stac! pointer and eight *+-bit address
registers pro"iding storage for eight addresses. These registers are not directl# accessible b# the programmer( rather the# are manipulated %ith control-transfer instructions. An# one of the eight address registers in the address stac! can ser"e as the program counter( the current program counter is specified b# the stac! pointer. The other se"en address registers permit storage for nesting of subroutines up to se"en le"els deep. The execution of a call instruction causes the next address register in turn to become the current program counter, and the return instruction causes the address register that last ser"ed as the program counter to again

become the program counter. The stac! %ill %rap around if subroutines are nested more than se"en le"els deep.

&. Fla's. The four flags in the 8,,8 are CA--., /E-0, 1234, and 5A-2T.. The# are used to
reflect the status of the latest arithmetic or logical operation. An# of the flags can be used to alter program flo% through the use of the conditional 6ump, call, or return instructions. There is no direct mechanism for sa"ing or restoring flags, %hich places a se"ere burden on interrupt processing &see Appendix * for details'. The CA--. flag indicates if a carr#-out or borro%-in %as generated, thereb# pro"iding the abilit# to perform multiple-precision binar# arithmetic. The /E-0 flag indicates %hether or not the result is 7ero. This pro"ides the abilit# to compare the t%o "alues for e8ualit#. The 1234 flag reflects the setting of the leftmost bit of the result. The presence of this flag creates the illusion that the 8,,8 is able to handle signed numbers. Ho%e"er, there is no facilit# for detecting signed o"erflo% on additions and subtractions. 9urthermore, comparing signed numbers b# subtracting them and then testing the 1234 flag %ill not gi"e the correct result if the subtraction resulted in signed o"erflo%. This o"ersight %as not corrected until the 8,8:. The 5A-2T. flag indicates if the result is e"en or odd parit#. This permits testing for transmission errors, an ob"iousl# useful function for a C-T terminal.

C. Instruction Set 4he -''- instructions are designed 5or moving or modi5ying -*bit operands. Operands are either contained in the instruction itsel5 9immediate operand;" contained in a scratchpad register 9register operand;" or contained in the M register 9memory operand;. Since the M register can be used interchangeably /ith the scratchpad registers" there are only t/o distinct operand*addressing modes E immediate and register. 4ypical instruction 5ormats 5or these modes are sho/n in @igure $.

Fi'ure 1. T(pical 8008 and 8080 instruction )ormats. 4he instruction set consists o5 scratchpad*register instructions" accumulator*speci5ic instructions" trans5er*o5*control instructions" input/output instructions" and processor* control instructions. 4he scratchpad*register instructions modi5y the contents o5 the M register or any scratchpad register. 4his can consist o5 moving data bet/een any t/o registers" moving immediate data into a register" or incrementing or decrementing the contents o5 a register. 4he incrementing and decrementing instructions /ere not in !omputer 4erminal?s speci5ied instruction setD they /ere added by Intel to provide 5or loop control" thereby ma0ing the processor more general*purpose. Most o5 the accumulator speci5ic instructions per5orm operations bet/een the accumulator and a speci5ied operand. 4he operand can be any one o5 the scratchpad registers" including M" or it can be immediate data. 4he operations are add" add*/ith* carry" subtract" subtract*/ith*borro/" logical 3&6" logical OR" logical e=clusive*OR" and compare. @urthermore" there are 5our unit*rotate instructions that operate on the accumulator. 4hese instructions per5orm either an -* or ,*bit rotate 9the !3RRF 5lag acts as a ninth bit; in either the le5t or right direction. 4rans5er*o5*control instructions consist o5 Gumps" calls" and returns. 3ny o5 the trans5ers can be unconditional" or can be conditional based on the setting o5 any one o5 the 5our 5lags. Ma0ing calls and returns conditional /as done to preserve the symmetry /ith Gumps and 5or no other reason. 3 short one*byte 5orm o5 call is also provided" /hich /ill be discussed later under interrupts. ach o5 the Gump and call instructions 9/ith the e=ception o5 the one*byte call; speci5ies an absolute code address in the second and third byte o5 the instruction. 4he second byte contains the eight lo/*order bits o5 the address" and the third byte contains the si= high* order bits. 4his inverted storage" /hich /as to haunt all processors evolved 5rom the -''-" /as a result o5 compatibility /ith the 6atapoint bit*serial processor" /hich processes addresses 5rom lo/ bit to high bit. 4his inverted storage did have a virtue in those early days /hen ).+ by - memory chips /ere popularH it allo/ed all memory chips to select a byte and latch it 5or output /hile /aiting 5or the si= high*order bits /hich selected the chip. 4his speeded up memory access. 4here are eight input instructions and )( output instructions" /hich altogether use up %) opcodes. ach o5 these instructions trans5ers a byte o5 data bet/een the accumulator and a designated I/O port. 4he processor*control instructions are halt and no*op. <alt puts the processor into a /aiting state. 4he processor /ill remain in that state until an interrupt occurs. &o*op is

actually one o5 the move instructionsD speci5ically" it moves the contents o5 the accumulator into the accumulator" thereby having no net e55ect 9move instructions do not alter 5lag settings;. . Interrupts Interrupt processing /as not a re>uirement o5 the -''-. <ence only the most primitive mechanism conceivable*not incrementing the program counter*/as provided. Such a mechanism permits an interrupting device to Gam an instruction into the processor?s instruction stream. 4his is accomplished by having the interrupting device" instead o5 memory" respond to the instruction 5etchD since the program counter isn?t incremented" the instruction in memory that doesn?t get 5etched /on?t be s0ipped. 4he instruction typically supplied by the interrupting device is a call" so that an interrupt service routine can be entered and then the main program can be resumed a5ter interrupt processing is complete 9a Gump instruction /ould result in the loss o5 the main program return address;. 4o simpli5y the interrupting device?s tas0 o5 generating an instruction" the -''instruction set provides eight one*byte subroutine calls" each to a 5i=ed location in memory. 4here are no instructions provided 5or disabling the interrupt mechanism" and so this 5unction must be realized /ith e=ternal hard/are. More important" there are no instructions 5or conveniently saving the registers and 5lags /hen an interrupt occurs. I*. Objectives and Constraints o) t"e 8080 By $,2% the technology had advanced 5rom p*MOS to n*MOS 5or memory 5abrication. 3s an engineering e=ercise it /as decided to use the -''- layout mas0s /ith the n*MOS process to obtain a 5aster -''-. 35ter a short study" it /as determined that a ne/ layout /as re>uired" so it /as decided to enhance the processor at the same time" and to utilize the ne/ ('*pin pac0age made practical by high*volume calculator chips. 4he result /as the -'-' processor. 4he -'-' /as the 5irst processor designed speci5ically 5or the microprocessor mar0et. It /as constrained to include all the -''- instructions but not necessarily /ith the same encodings. 4his meant that user?s so5t/are /ould be portable but the actual ROM chips containing the programs /ould have to be replaced. 4he main obGective o5 the -'-' /as to obtain a $'H$ improvement in throughput" eliminate many o5 the -''- shortcomings that had by then become apparent" and provide ne/ processing capabilities not 5ound in the -''-. 4hese included a commitment to $+*bit data types mainly 5or address computations" B!6 arithmetic" enhanced operand*addressing modes" and improved interrupt capabilities. &o/ that memory costs had come do/n and processing speed /as approaching 44:" larger memory spaces /ere appearing more practical. <ence another goal /as to be able to address directly more than $+A bytes. Symmetry /as not a goal" because the bene5its to be gained 5rom ma0ing the e=tensions symmetric /ould not

Gusti5y the resulting increase in chip size and opcode space. *. T"e 8080 Instruction- et !rocessor 4he -'-' architecture is an unsymmetrical e=tension o5 the -''-. 4he byte*handling 5acilities have been augmented /ith a limited number o5 $+*bit 5acilities. 4he memory space gre/ to +(A bytes and the stac0 /as made virtually unlimited. #arious alternatives 5or the -'-' /ere considered. 4he simplest involved merely adding a memory stac0 and stac0 instructions to the -''-. 3n intermediate position /as to augment the above /ith $+*bit arithmetic 5acilities that can be used 5or e=plicit address manipulations as /ell as $+*bit data manipulations. 4he most di55icult alternative /as a symmetric e=tension /hich replaced the one*byte M*register instructions /ith three*byte generalized memory*access instructions. 4he last t/o bytes o5 these instructions contained t/o address*mode bits speci5ying indirect addressing and inde=ing 9using <: as an inde= register; and a $(*bit displacement. 3lthough this /ould have been a more versatile addressing mechanism" it /ould have resulted in signi5icant code e=pansion on e=isting -''- programs. @urthermore" the logic necessary to implement this solution /ould have precluded the ability to implement $+*bit arithmeticD such arithmetic /ould not be needed 5or address manipulations under this enhanced addressing 5acility but /ould still be desirable 5or data manipulations. @or these reasons" the intermediate position /as 5inally ta0en. A. Memory and I/O Structure 4he -'-' can address up to +(A bytes o5 memory" a 5our5old increase over the -''- 9the $(*bit address stac0 o5 the -''- /as eliminated;. 4he address bus o5 the -'-' is $+ bits /ide" in contrast to eight bits 5or the -''-" so an entire address can be sent do/n the bus in one memory cycle. 3lthough the data handling 5acilities o5 the -'-' are primarily byte*oriented 9the -''- /as e=clusively byte*oriented;" certain operations permit t/o consecutive bytes o5 memory to be treated as a single data item. 4he t/o bytes are called a /ord. 4he data bus o5 the -'-' is only eight bits /ide" and hence /ord accesses re>uire an e=tra memory cycle. 4he most signi5icant eight bits o5 a /ord are located at the higher memory address. 4his results in the same 0ind o5 inverted storage already noted in trans5er instructions o5 the -''-. 4he -'-' e=tends the %)*port capacity o5 the -''- to ).+ input ports and ).+ output ports. In this instance" the -'-' is actually more symmetrical than the -''-. :i0e the -''-" all o5 the ports are directly addressable by the instruction set. B. Register Structure

4he -'-' processor contains a 5ile o5 seven -*bit general registers" a $+*bit program counter 9P!; and stac0 pointer 9SP;" and 5ive $*bit 5lags. 3 comparison bet/een the -''and -'-' register sets is sho/n in @igure ).

Fi'ure #. Comparison o) 8008 and 8080 re'isters 1. +eneral ,e'isters. The 8,8, registers are the same se"en 8-bit registers that %ere in the
8,,8 scratchpad-namel# A,B,C, D,E,H, and . 2n order to incorporate *:-bit data facilities in the 8,8,, certain instructions operate on the register pairs BC, DE, and H . The se"en registers can be used interchangeabl# for on-chip temporar# storage. The three register pairs are used for address manipulations, but their roles are not interchangeable( there is an 8,8, instruction that allo%s operations on DE and not BC, and there are address modes that access memor# indirectl# through BC or. DE but not H . As in the 8,,8, the A register has a uni8ue role in arithmetic and logical operations; it ser"es as one of the operands and is the receptacle for the result. The H register again has its special role of pointing to the pseudo-register $.

#. tac% !ointer and !ro'ram Counter. The 8,8, has a single program counter instead of
the floating program counter of the 8,,8. The program counter is *: bits &t%o bits more than the 8,,8<s program counter', thereb# permitting an address space of :+=. The stac! is contained in memor# instead of on the chip, %hich remo"es the restriction of onl# se"en le"els of nested subroutines. The entries on the stac! are *: bits %ide. The *:-bit stac! pointer is used to locate the stac! in memor#. The execution of a call instruction causes the contents of the program counter to be pushed onto the stac!, and the return instruction causes the last stac! entr# to be popped into the program counter. The stac! pointer %as chosen to run >do%nhill> &%ith the stac! ad"ancing to%ard lo%er memor#' to simplif# indexing into the stac! from the user<s program &positi"e indexing' and to simplif# displa#ing the contents of the stac! from a front panel. ?nli!e the 8,,8, the stac! pointer is directl# accessible to the programmer. 9urthermore, the stac! itself is directl# accessible, and instructions are pro"ided that permit the programmer to push and pop his o%n *:-bit items onto the stac!.

&. Fla's. A fifth flag, A?@2 2A-. CA--., augments the 8,,8 flag set to form the flag set of the
8,8,. The A?@2 2A-. CA--. flag indicates if a carr# %as generated out of the four lo%-order bits. This flag, in con6unction %ith a decimal-ad6ust instruction, pro"ides the abilit# to perform pac!ed BCD addition &see Appendix A for details'. This facilit# can be traced bac! to the +,,+ processor. The A?@2 2A-. CA--. flag has no purpose other than for BCD arithmetic, and hence the conditional transfer instructions %ere not expanded to include tests on the A?@2 2A-. CA--. flag. 2t %as proposed too late in the design that the 5A-2T. flag should double as an 0BE-9 0C flag. Although this feature didn<t ma!e it into the 8,8,, it did sho% up t%o #ears later in /ilog<s /8,.

C. Instruction Set 4he -'-' includes the entire -''- instruction set as a subset" 4he added instructions provide some ne/ operand*addressing modes and some 5acilities 5or manipulating $+*bit data. 4hese e=tensions have introduced a good deal o5 asymmetry. 4ypical instruction 5ormats are sho/n in @igure $

4he only means that the -''- had 5or accessing operands in memory /as via the M register. 4he -'-' has certain instructions that access memory by speci5ying the memory address 9direct addressing; and also certain instructions that access memory by speci5ying a pair o5 general registers in /hich the memory address is contained 9indirect addressing;. In addition" the -'-' includes the register and immediate operand*addressing modes o5 the -''-. 3 $+*bit immediate mode is also included. 4he added instructions can be classi5ied as load/store instructions" register*pair instructions" <:*speci5ic instructions" accumulator*adGust instructions" carry instructions" e=panded I/O instructions" and interrupt instructions. 4he load/store instructions load and store the accumulator register and the <: register pair using the direct and indirect addressing mode. Both modes can be used 5or the accumulator" but due to chip size constraints" only the direct mode /as implemented 5or <:. 4he register*pair instructions provide 5or the manipulation o5 $+*bit data items. Speci5ically" register pairs can be loaded /ith $+*bit immediate data" incremented" decremented" added to <:" pushed on the stac0" or popped o55 the stac0. @urthermore" the 5lag settings themselves can be pushed and popped" thereby simpli5ying saving the environment /hen interrupts occur 9this /as not possible in the -''-;. 4he <:*speci5ic instructions include 5acilities 5or trans5erring <: to the program counter or to the stac0 pointer" and e=changing <: /ith 6 or /ith the top entry on the stac0. 4he last o5 these instructions /as included to provide a mechanism 5or 9$; removing a subroutine return address 5rom the stac0 so that passed parameters can be discarded or 9); burying a result*to*be*returned under the return address" 4his became the longest instruction in the -'-' 9. memory cycles;D its implementation precluded the inclusion o5 several other instructions that /ere already proposed 5or the processor. 4/o accumulator*adGust instructions are provided. One complements each bit in the accumulator and the other modi5ies the accumulator so that it contains the correct decimal result a5ter a pac0ed B!6 addition is per5ormed. 4he carry instructions provide 5or setting or complementing the !3RRF 5lag. &o instruction is provided 5or clearing the !3RRF 5lag. Because o5 the /ay the !3RRF 5lag semantics are de5ined" the !3RRF 5lag can be cleared simply by ORing or 3&6ing the accumulator /ith itsel5. 4he e=panded I/O instructions permit trans5erring the contents o5 any one o5 ).+ -*bit ports either to or 5rom the accumulator. 4he port number is e=plicitly contained in the instructionD hence" the instruction is t/o bytes long. 4he e>uivalent -''- instruction is only one byte long. 4his is the only instance in /hich an -'-' instruction re>uires a di55erent number o5 bytes than its -''- counterpart. 4he motivation 5or doing this /as more to 5ree up %) opcodes than to increase the number o5 I/O ports.

4he -'-' has the identical interrupt mechanism the -''- has" but in addition" it has instructions 5or enabling or disabling the interrupt mechanism. 4his 5eature" along /ith the ability to push and pop the processor 5lags" made the interrupt mechanism practical. *I. 808- Objectives and Constraints In $,2+" technology advances allo/ed Intel to consider enhancing its -'-'. 4he obGective /as to come out /ith a processor set utilizing a single po/er supply and re>uiring 5e/er chips 9the -'-' re>uired a separate oscillator chip and system controller chip to ma0e it usable;. 4he ne/ processor" called the -'-." /as constrained to be compatible /ith the -'-' at the machine*code level. 4his meant that the only e=tension to the instruction set could be in the t/elve unused opcodes o5 the -'-'. 4he -'-. turned out to be architecturally not much more than a repac0aging o5 the -'-'. 4he maGor di55erences /ere in such areas as an on*chip oscillator" po/er*on reset" vectored interrupts" decoded control lines" a serial I/O port" and a single po/er supply. 4/o ne/ instructions" RIM and SIM" /ere added to handle the serial port and interrupt mas0. Several other instructions that had been contemplated /ere not made available because o5 the so5t/are rami5ications and the compatibility constraints they /ould place on the 5orthcoming -'-+. *II. Objectives and Constraints o) 8086 4he ne/ Intel -'-+ microprocessor /as designed to provide an order o5 magnitude increase in processing throughput over the older -'-'. 4he processor /as to be assembly* language*level*compatible /ith the -'-' so that e=isting -'-' so5t/are could be reassembled and correctly e=ecuted on the -'-+. 4o allo/ 5or this" the -'-' register set and instruction set appear as logical subsets o5 the -'-+ registers and instructions. By utilizing a general*register structure architecture" Intel could capitalize on its e=perience /ith the -'-' to obtain a processor /ith a higher degree o5 sophistication. Strict -'-' compatibility" ho/ever" /as not attempted" especially in areas /here it /ould compromise the 5inal design. 4he goals o5 the -'-+ architectural design /ere to provide symmetric e=tensions o5 e=isting -'-' 5eatures" and to add processing capabilities not 5ound in the -'-'. 4hese 5eatures included $+*bit arithmetic" signed -* and $+*bit arithmetic 9including multiply and divide;" e55icient interruptible byte*string operations" improved bit*manipulation 5acilities" and mechanisms to provide 5or re*entrant code" position*independent code" and dynamically relocatable programs. By no/ memory had become very ine=pensive and microprocessors /ere being used in applications that re>uired large amounts o5 code and/or data. 4hus another design goal

/as to be able to address directly more than +(0 bytes and support multiprocessor con5igurations. *III. T"e 8086 Instruction- et !rocessor 4he -'-+ processor architecture is described in terms o5 its memory structure" register structure" instruction set" and e=ternal inter5ace. 4he -'-+ memory structure includes up to one megabyte o5 memory space and up to +(A input/output ports. 4he register structure includes three 5iles o5 registers. @our $+*bit general registers can participate interchangeably in arithmetic and logic operations" t/o $+*bit pointer and t/o $+*bit inde= registers are used 5or address calculations" and 5our $+*bit segment registers allo/ e=tended addressing capabilities. &ine 5lags record the processor state and control its operation. 4he instruction set supports a /ide range o5 addressing modes and provides operations 5or data trans5er" signed and unsigned -* and $+*bit arithmetic" logicals" string manipulations" control trans5er" and processor control. 4he e=ternal inter5ace includes a reset se>uence" interrupts" and a multiprocessor*synchronization and resource*sharing 5acility. A. Memory Structure 4he -'-+ memory structure consists o5 t/o components*the memory space and the input/output space. 3ll instruction code and operands reside in the memory space. Peripheral and I/O devices ordinarily reside in the I/O space" e=cept in the case o5 memory*mapped devices. 1. Memor( pace. The 8,8: memor# is a se8uence of up to * million 8-bit b#tes, a
considerable increase o"er the :+= b#tes in the 8,8,. An# t%o consecuti"e b#tes ma# be paired together to form a *:-bit %ord. 1uch %ords ma# be located at odd or e"en b#te addresses. The data bus of the 8,8: is *: bits %ide, so, unli!e the 8,8,, a %ord can be accessed in one memor# c#cle &ho%e"er, %ords located at odd b#te addresses still re8uire t%o memor# c#cles'. As in the 8,8,, the most significant 8 bits of a %ord are located in the b#te %ith the higher memor# address. 1ince the 8,8: processor performs *:-bit arithmetic, the address ob6ects it manipulates are *: bits in length. 1ince a *:-bit 8uantit# can address onl# :+= b#tes, additional mechanisms are re8uired to build addresses in a megab#te memor# space. The 8,8: memor# ma# be concei"ed of as an arbitrar# number of segments, each at most :+= b#tes in si7e. Each segment begins at an address %hich is e"enl# di"isible b# *: &i.e., the lo%-order + bits of a segment<s address are 7ero'. At an# gi"en moment the contents of four of these segments are immediatel# addressable. These four segments, called the current code segment, the current data segment, the current stac! segment, and the current extra segment, need not be uni8ue and ma# o"erlap. The highorder *: bits of the address of each current segment are held in a dedicated *:-bit segment register. 2n the degenerate case %here all four segments start at the same address, namel# address ,, %e ha"e an 8,8, memor# structure. B#tes or %ords %ithin a segment are addressed b# using *:-bit offset addresses %ithin the :+= b#te segment. A A,-bit ph#sical address is constructed b# adding the *:-bit offset address to the

contents of a *:-bit segment register %ith + lo%-order 7ero bits appended, as illustrated in 9igure ).

Fi'ure &. $ddressin' one million b(tes re.uires a #0-bit memor( address. T"is #0bit address is constructed b( o))settin' t"e e))ective address )our bits to t"e ri'"t o) t"e se'ment address/ )illin' in t"e )our lo0-order bits o) t"e se'ment address 0it 1eroes/ and t"en addin' t"e t0o. #arious alternatives 5or e=tending the -'-' address space /ere considered. One such alternative consisted o5 appending - rather than ( lo/*order zero bits to the contents o5 a segment register" thereby providing a )(*bit physical address capable o5 addressing up to $+ megabytes o5 memory. 4his /as reGected 5or the 5ollo/ing reasonsH Segments /ould be 5orced to start on ).+*byte boundaries" resulting in e=cessive memory 5ragmentation. 4he ( additional pins that /ould he re>uired on the chip /ere not available.

It /as 5elt that a $*megabyte address space /as su55icient. #. Input2Output pace. 2n contrast to the AD: 2E0 ports in the 8,8,, the 8,8: pro"ides :+=
addressable input or output ports. ?nli!e the memor#, the 2E0 space is addressed as if it %ere a single segment, %ithout the use of segment registers. 2nputEoutput ph#sical addresses are in fact A, bits in length, but the high-order + bits are al%a#s 7ero. The first AD: ports are directl# addressable &address in the instruction', %hereas all :+= ports are indirectl# addressable &address in register'. 1uch indirect addressing %as pro"ided to permit consecuti"e ports to he accessed in a program loop. 5orts ma# be 8 or *: bits in si7e, and *:-bit ports ma# he located at odd or e"en addresses.

B. Register Structure 4he -'-+ processor contains three 5iles o5 5our $+*bit registers and a 5ile o5 nine $*bit 5lags. 4he three 5iles o5 registers are the general*register 5ile" the pointer* and inde=* register 5ile" and the segment*register 5ile. 4here is a $+*bit instruction pointer 9called the program counter in the earlier processors; /hich is not directly accessible to the programmerD rather" it is manipulated /ith control trans5er instructions. 4he -'-+ register set is a superset o5 the -'-' registers" as sho/n in @igures ( and .. !orresponding registers in the -'-' and -'-+ do not necessarily have the same names" thereby permitting the -'-+ to use a more meaning5ul set o5 names.

Fi'ure 3. T"e 8080 re'isters as a subset o) t"e 8086 re'isters.

Fi'ure -. T"e 8086 re'ister structure. 1/ +eneral-,e'ister File. The A@-B@-C@-D@ register set is called the general-register file, or
H group &for reasons that %ill be apparent belo%'. The general registers can participate interchangeabl# in the arithmetic and logical operations of the 8,8:. 1ome of the other 8,8: operations &such as the string operations' dedicate certain of the general registers to specific

uses. These uses are indicated b# the mnemonic phrases >accumulator,> >base,> >count,> and >data> in 9igure D. The general registers ha"e a propert# that distinguishes them from the other registers-their upper and lo%er hal"es are separatel# addressable. Thus, the general registers can be thought of as t%o files of four 8-bit registers-the H &high-order' file and the &lo%-order' file.

#. !ointer- and Inde4-,e'ister File. The 15-B5-12-D2 register set is called the pointer- and
index-register file, or the 5 and 2 groups. The registers in this file generall# contain offset addresses used for addressing %ithin a segment. i!e the general registers, the pointer and index registers can participate interchangeabl# in the *:-bit arithmetic and logical operations of the 8,8:, thereb# pro"iding a means to perform address computations. These registers pla# a ma6or role in effecti"e address computations, as described in the section on 0perand Addressing belo% &1ec. B222. C. *.'. There is one main difference bet%een the registers in this file, %hich results in di"iding the file into t%o subfiles, the 5 or pointer group &15,B5' and the 2 or index group &12,D2'. The difference is that the pointers are b# default assumed to contain offset addresses %ithin the current stac! segment, and the indexes are b# default generall# assumed to contain offset addresses %ithin the current data segment. The mnemonic phrases >stac! pointer,> >base pointer,> >source index,> and >destination index> are mnemonics associated %ith these registers< names, as sho%n in 9igure D.

&. e'ment-,e'ister File. The C1-D1-11-E1 register set is called the segment-register file, or
1 group. The segment registers pla# an important role in the memor# addressing mechanism of the processor. These registers are similar in that the# are used in all memor# address computations &see 1ec. B222. A. of this chapter'. The segment registers names ha"e the associated mnemonic phrases >code,> >data,> >stac!,> and >extra as sho%n in 9igure D. The contents of the C1 register define the current code segment. All instruction fetches are ta!en to be relati"e to C1, using the instruction pointer &25' as an offset. The contents of the D1 register define the current data segment. 3enerall#, all data references except those in"ol"ing B5 or 15 are ta!en b# default to be relati"e to D1. The contents of the 11 register define the current stac! segment. All data references %hich explicitl# or implicitl# in"ol"e 15 or B5 are ta!en b# default to be relati"e to 11. This includes all push and pop operations, interrupts, and return operations. The contents of the E1 register define the current extra segment. The extra segment has no specific use, although it is usuall# treated as an additional data segment %hich can be specified in an instruction b# using a special default-segment-o"erride prefix. 2n general, the default segment register for the t%o t#pes of data references &D1 and 11' can be o"erriden. B# preceding the instruction %ith a special one-b#te prefix, the reference can be forced to be relati"e to one of the other three segment registers. This prefix, as %ell as other prefixes described later, has a uni8ue encoding that permits it to be distinguished from the opcodes. 5rograms %hich do not load or manipulate the segment registers are said to be d#namicall# relocatable. 1uch a program ma# be interrupted, mo"ed in memor# to a ne% location, and restarted %ith ne% segment-register "alues. At first a set of eight segment registers %as proposed along %ith a field in a program-status %ord specif#ing %hich segment register %as currentl# C1, %hich %as currentl# D1, and %hich %as currentl# 11. The other fi"e all ser"ed as extra segment registers. 1uch a scheme %ould ha"e resulted in "irtuall# no thrashing of segment register contents( start addresses of all needed segments %ould be loaded initiall# into one of the eight segment registers, and the roles of the "arious segment registers %ould "ar# d#namicall# during program execution. Concern o"er the si7e of the resulting processor chip forced the number of segment

registers to be reduced to the minimum number necessar#, namel# four. Cith this minimum number, each segment register could be dedicated to a particular t#pe of segment &code, data, stac!, extra', and the specif#ing field- in the program status %ord %as no longer needed.

3. Fla'-,e'ister File. The A9-C9-D9-29-09-59-19-T9-/9 register set is called the flag-register

file or 9 group. The flags in this group are all one bit in si7e and are used to record processor status information and to control processor operation. The flag registers< names ha"e the follo%ing associated mnemonic phrases;

3@ !@ 6@ I@ O@ P@ S@ 4@ I@

3u=iliary carry !arry 6irection Interrupt enable Over5lo/ Parity Sign 4rap Iero

4he 3@" !@" P " S@" and I@ 5lags retain their 5amiliar -'-' semantics" generally re5lecting the status o5 the latest arithmetic or logical operation. 4he O@ 5lag Goins this group" re5lecting the signed arithmetic over5lo/ condition. 4he 6@" I@" and 4@ 5lags are used to control certain aspects o5 the processor. 4he 6@ 5lag controls the direction o5 the string manipulations 9auto*incrementing or auto*decrementing;. 4he I@ 5lag enables or disables e=ternal interrupts. 4he 4@ 5lag puts the processor into a single*step mode 5or program debugging. More detail is given on each o5 these three 5lags later in the chapter. C. Instruction Set 4he -'-+ instruction set*/hile including most o5 the -'-' set as a subset*has more /ays to address operands and more po/er in every area. It is designed to implement bloc0* structured languages e55iciently. &early all instructions operate on either -* or $+*bit operands. 4here are 5our classes o5 data trans5er. 3ll 5our arithmetic operations are available. 3n additional logic instruction" test" is included. 3lso ne/ are byte* and /ord* string manipulations and intersegment trans5ers. 1. Operand $ddressin'. The 8,8: instruction set pro"ides man# more %a#s to address
operands than %ere pro"ided b# the 8,8,. T%o-operand operations generall# allo% either a register or memor# to ser"e as one operand &called the first operand', and either a register or a constant %ithin the instruction to ser"e as the other &called the second operand'. T#pical formats for t%o-operand operations are sho%n in 9igure : &second operand is a register' and 9igure F &second operand is a constant'. The result of a t%o-operand operation ma# be directed to either of the source operands, %ith the exception, of course, of in-line immediate constants. 1ingleoperand operations generall# allo% either a register or a memor# to ser"e as the operand. A t#pical one- operand format is sho%n in 9igure 8. Birtuall# all 8,8: operators ma# specif# 8- or *:-bit operands.

Fi'ure 6. T(pical )ormat o) 8086 t0o-operand operation/ 0"en second operand is a re'ister.

Fi'ure 5. T(pical )ormat o) 8086 t0o-operand operation/ 0"en second operand is a constant 6immediate data7.

Fi'ure 8. T(pical )ormat o) 8086 one-operand operation. Memory operands. An instruction ma# address an operand residing in memor# in one of four
%a#s as determined b# the mod and rim fields in the instruction &see Table A'. Direct *:-bit offset address 2ndirect through a base register &B5 or B@', optionall# %ith an 8- or *:-bit displacement 2ndirect through an index register &12 or D2', optionall# %ith an 8- or *:-bit displacement 2ndirect through the sum of a base register and an index register, optionall# %ith an 8- or *:-bit displacement The general register, B@, and the pointer register, B5, ma# ser"e as base registers. Chen the base register E@ is used %ithout an index register, the operand b# default resides in the current data segment. Chen the base register B5 is used %ithout an index register, the operand b# default resides in the current stac! segment. Chen both base and index registers are used, the operand b# default resides in the segment determined b# the base register. Chen an index register alone is used, the operand b# default resides in the current data segment. Auto-incrementing and auto-decrementing address modes %ere not included in general, since it %as felt that their use is mainl# oriented to%ards string processing. These modes %ere included on the string primiti"e instructions.

Register operands. The four *:-bit general registers and the four *:-bit pointer and index
registers ma# ser"e interchangeabl# as operands in *:-bit operations. Three exceptions to note

are multipl#, di"ide, and the string operations, all of %hich use the A@ register implicitl#. The eight 8-bit registers of the H group ma# ser"e interchangeabl# in 8-bit operations. Again, multipl#, di"ide, and the string operations use A implicitl#. Table ) sho%s the register selection as determined b# the rEm field &first operand' or reg field &second operand' in the instruction.

Immediate operands. All t%o-operand operations except multipl#, di"ide, and the string
operations allo% one source operand to appear %ithin the instruction as immediate data represented in A<s complement form. 1ixteen-bit immediate operands ha"ing a high-order b#te %hich is the sign extension of the lo%-order b#te ma# be abbre"iated to 8 bits.

Addressing mode usage. The addressing modes permit registers B@ and B5 to ser"e as base
registers and registers 12 and D2 as index registers. 5ossible use of this for language implementation is discussed belo%.

Simple variables and arrays: A simple "ariable is accessed %ith the direct address
mode. An arra# element is accessed %ith the indirect address mode utili7ing the sum of the register 12 &%here 12 contains the index into the arra#' and displacement &%here displacement is the offset of the arra# in its segment'.

Based variables: A based "ariable is located at a memor# address pointed at b# some

other "ariable. 2f the contents of the pointer "ariable %ere placed in B@, the indirect addressing mode utili7ing B@ %ould access the based "ariable. 2f the based "ariable %ere an arra# and the index into the arra# %ere placed in 12, the indirect addressing mode utili7ing the sum of the register B@ and register 12 %ould access elements of the arra#.

Stack marker: $ar!ing a stac! permits efficient implementation of bloc!-structured

languages and pro"ides an efficient address mechanism for reentrant procedures. -egister B5 can be used as a stac! mar!er pointer to the beginning of an acti"ation record in the stac!. The indirect address mode utili7ing the sums of the base register B5 and a displacement &%here displacement is the offset of a local "ariable in the acti"ation record' %ill access the "ariable declared in the currentl# acti"e bloc!. The indirect address mode utili7ing the sum of the base register B5, index register 12 &%here 12 contains the index in an arra#', and displacement &%here displacement is the offset of the arra# in the acti"ation record' %ill access an element of the arra#. -egister D2 can be used in the same manner as 12 so that t%o arra# elements can be accessed concurrentl#.

Example: An example of a procedure-calling se8uence on the 8,8: illustrates the

interaction of the addressing modes and acti"ation records. (CA $.5-0C &A 5HA, BETA' 5?1H A 5HA (pass parameters b# pushing them on the stac! 5?1H BETA CA $.5-0C (call the procedure (5-0CED?-E $.5-0C &A, B' $.5-0C; (entr# point 5?1H B5 (sa"e pre"ious B5 "alue $0B B5,15 (ma!e B5 point at ne% record 1?B 15, 0CA 1 (allocate local storage on stac! (... for reentrant procedures &stac! ad"ances to%ards lo%er memor#' (bod# of procedure

$0B 15,B5 (deallocate local storage 505 B5 (restore pre"ious B5 -ET + (return and discard + b#tes of parameters

7pon entry to the procedure MFPRO! its parameters are addressable /ith positive o55sets 5rom BP 9the stac0 gro/s to/ards lo/er memory addresses;. Since usually less than $)- bytes o5 parameters are passed" only an -*bit signed displacement 5rom BP is needed. Similarly" local variables to MFPRO! are addressable /ith negative o55sets 5rom BP. 3gain" economy o5 instruction size is realized by using -*bit signed displacements. 3 special return instruction discards
the parameters pushed on the stac!.

Table 2 Determining 8086 Offset Address of a Memory Operand

68se T"is Table 9"en mod : 11; Ot"er0ise 8se Table &.7 4his table applies to the 5irst operand onlyD the second operand can never be a memory operand. mod speci5ies ho/ disp*lo and disp*hi are used to de5ine a displacement as 5ollo/sH mod J ''H 6ISPJ' 9disp*lo and disp*hi are absent; mod J '$H 6ISPJdisp*lo sign e=tended 9disp*hi is absent; mod J $'H 6ISP J disp*hi"disp*lo r/m speci5ies /hich base and inde= register contents are to be added to the displacement to 5orm the operand o55set address as 5ollo/sH r/m J '''H O@@S r/m J ''$H O@@S r/m J '$'H O@@S r/m J '$$H O@@S r/m J $''H O@@S r/m J $'$H O@@S r/m J $$'H O@@S r/m J $$$H O@@S 4 J 9BK; L 9SI; L 6ISP 9indirect address mode; 4 J 9BK; L 96I; L 6ISP 9indirect address mode; 4 J 9BP; L 9SI; L 6ISP 9indirect address mode; 4 J 9BP; L 96I; L 6ISP 9indirect address mode; 4J 9SI; L 6ISP 9indirect address mode; 4J 96I; L 6ISP 9indirect address mode; 4 J 9BP; L 6ISP 9indirect address mode; 4 J 9BK; L 6ISP 9indirect address mode;

4he 5ollo/ing special case is an e=ception to the above rules I5 modJ'' and r/mJ$'' then O@@S 4 J 6ISP*<I" 6ISP*:O 9direct address mode;

Table & <eterminin' 8086 ,e'ister Operand 97se 4his 4able When mod J $$D Other/ise 7se 4able ).; @irst operand r/m '''H ''$H '$'H '$$H $''H $'$H $$'H $$$H -*bit 3: !: 6: B: 3< !< 6< B< $+*bit 3K !K 6K BK SP BP SI 6I Second operand reg '''H ''$H '$'H '$$H $''H $'$H $$'H $$$H -*bit 3: !: 6: B: 3< !< 6< B< $+*bit 3K !K 6K BK SP BP SI 6I

#. <ata Trans)ers. 9our classes of data transfer operations ma# be distinguished; generalpurpose, accumulator-specific, address-ob6ect transfers, and flag transfers. The general-purpose data transfer operations are mo"e, push, pop, and exchange. 3enerall#, these operations are a"ailable for all t#pes of operands. The accumulator-specific transfers include input and output and the translate operations. The first AD: ports can be addressed directl#, 6ust as the# %ere addressed in the 8,8,. Ho%e"er, the 8,8: also permits ports to be addressed indirectl# through a register &D@'. This latter facilit# allo%s :+= ports to be addressed. 9urthermore, the 8,8: ports ma# be 8 or *: bits %ide, %hereas the 8,8, onl# permitted 8-bit-%ide ports. The translate operation performs a table-loo!up b#te translation. Ce %ill see the useful ness of this operation belo%, %hen it is combined %ith string operations. The address-ob6ect transfers G load effecti"e address and load pointer G are an 8,8: facilit# not present in the 8,8,. A pointer is a pair of *:-bit "alues specif#ing a segment start address and an offset address( it is used to gain access to the full megab#te of memor#. The load pointer operations pro"ide a means of loading a segment start address into a segment register and an offset address into a general or pointer register in a single operation. The load effecti"e address operation pro"ides access to the offset address of an operand, as opposed to the "alue of the operand itself. The flag transfers pro"ide access to the collection of flags for such operations as push, pop, load, and store. A similar facilit# for pushing and popping flags %as pro"ided in the 8,8,( the load and store flags facilit# is ne% in the 8,8:.

2t should he noted that the load and store operations in"ol"e onl# those flags that existed in the 8,8,. This is part of the concessions made for 8,8, compatibilit# &%ithout these operations it %ould ta!e nine 8,8: b#tes to perform exactl# an 8,8, 5?1H 51C or 505 51C'.

&. $rit"metics. Chereas the 8,8, pro"ided for onl# 8-bit addition and subtraction of unsigned
numbers, the 8,8: pro"ides all four basic mathematical functions on 8- and *:-bit signed and unsigned numbers. 1tandard A<s complement representation of signed "alues is used. 1ufficient conditional transfers are pro"ided to allo% both signed and unsigned comparisons. The 09 flag allo%s detection of the signed o"erflo% condition. Consideration %as gi"en to pro"iding separate operations for signed addition and subtraction %hich %ould automaticall# trap on signed o"erflo% &signed o"erflo% is an exception condition, %hereas unsigned o"erflo% is not'. Ho%e"er, lac! of room in the opcode space prohibited this. As a compromise, a one-b#te trap-on-o"erflo% instruction %as included to ma!e testing for signed o"erflo% less painful. The 8,8, pro"ided a correction operation to allo% addition to be performed directl# on pac!ed binar#-coded representations of decimal digits. 2n the 8,8:, correction operations are pro"ided to allo% arithmetic to be performed directl# on unpac!ed representations of decimal digits &e.g., A1C22' or on pac!ed decimal representations.

Multiply and divide. Both signed and unsigned multipl# and di"ide operations are pro"ided.
$ultipl# produces a double-length product &*: bits for 8-bit multipl#, )A bits for *:-bit multipl#', %hile di"ide returns a single-length 8uotient and a single-length remainder from a double-length di"idend and single-length di"isor. 1ign extension operations allo% one to construct the doublelength di"idend needed for signed di"ision. A 8uotient o"erflo% &e.g., that caused b# di"iding b# 7ero' %ill automaticall# interrupt the processor.

Decimal instructions. 5ac!ed BCD operations are pro"ided in the form of accumulatorad6ustment instructions. T%o such instructions are pro"ided-one for an ad6ustment follo%ing an addition and one follo%ing a subtraction. The addition ad6ustment is identical to the 8,8, DAA instruction( the subtraction ad6ustment is defined similarl#. 5ac!ed multipl# and di"ide ad6ustments are not pro"ided, because the cross terms generated ma!e it impossible to reco"er the decimal result %ithout additional processor facilities &see Appendix A for details'. ?npac!ed BCD operations are also pro"ided in the form of accumulator ad6ust instructions &A1C22 is a special case of unpac!ed BCD'. 9our such instructions are pro"ided, one each for ad6ustments in"ol"ing addition, subtraction, multiplication, and di"ision. The addition and subtraction ad6ustments are similar to the corresponding pac!ed BCD ad6ustments except that the AH register is updated if an ad6ustment on A is re8uired. ?nli!e pac!ed BCD, unpac!ed BCD b#te multiplication does not generate cross terms, so multiplication ad6ustment consists of con"erting the binar# "alue in the A register into BCD digits in AH and A ( the di"ide ad6ustment does the re"erse. 4ote that ad6ustments for addition, subtraction, and multiplication are performed follo%ing the arithmetic operation( di"ision ad6ustment is performed prior to a di"ision operation. 1ee Appendix A for more details on unpac!ed BCD ad6ustments.

3. =o'icals. The standard logical operations A4D, 0-, @0-, and 40T are carr#-o"ers from the
8,8,. Additionall#, the 8,8: pro"ides a logical TE1T for specific bits. This consists of a logical A4D instruction %hich sets the flags but does not store the result, thereb# not destro#ing either operand.

The four unit-rotate instructions in the 8,8, are augmented %ith four unit-shift instructions in the 8,8:. 9urthermore, the 8,8: pro"ides multi-bit shifts and rotates including an arithmetic right shift.

-. trin' Manipulation. The 8,8: pro"ides a group of *-b#te instructions %hich perform
"arious primiti"e operations for the manipulation of b#te or %ord strings &se8uences of b#tes or %ords'. These primiti"e operations can be performed repeatedl# in hard%are b# preceding the instruction %ith a special prefix. The single-operation forms ma# be combined to form complex string operations in tight soft%are loops %ith repetition pro"ided b# special iteration operations. The 8,8, did not pro"ide an# string-manipulation facilities.

ard!are operation control. All primiti"e string operations use the 12 register to address the source operands, %hich are assumed to be in the current data segment. The D2 register is used to address the destination operands, %hich reside in the current extra segment. The operand pointers are incremented or decremented &depending on the setting of the D9 flag' after each operation, once for b#te operations and t%ice for %ord operations.
An# of the primiti"e string operation instructions ma# be preceded %ith a *-b#te prefix indicating that the operation is to be repeated until the operation count in C@ is satisfied, The test for completion is made prior to each repetition of the operation. Thus, an initial operation count of 7ero %ill cause 7ero executions of the primiti"e operation. The repeat prefix b#te also designates a "alue to compare %ith the /9 flag. 2f the primiti"e operation is one %hich affects the /9 flag and the /9 flag is une8ual to the designated "alue after an# execution of the primiti"e operation, the repetition is terminated. This permits the scan operation to ser"e as a scan-%hile or a scan-until. During the execution of a repeated primiti"e operation the operand pointer registers &12 and D2' and the operation count register &C@' are updated after each repetition, %hereas the instruction pointer %ill retain the offset address of the repeat prefix b#te &assuming it immediatel# precedes the string operation instruction'. Thus, an interrupted repeated operation %ill be correctl# resumed %hen control returns from the interrupting tas!.

"rimitive string operations. 9i"e primiti"e string operations are pro"ided;

$0B1 mo"es a string element &b#te or %ord' from the source operand to the destination operand. As a repeated operation, this pro"ides for mo"ing a string from one location in memor# to another. C$51 subtracts the string element at the destination operand from the string element at the source operand and affects the flags but does not return the result. As a repeated operation this pro"ides for comparing t%o strings. Cith the appropriate repeat prefix it is possible to compare t%o strings and determine after %hich string element the t%o strings become une8ual, thereb# establishing an ordering bet%een the strings. 1CA1 subtracts the string element at the destination operand from A &or A@ for %ord strings' and affects the flags but does not return the result. As a repeated operation this pro"ides for scanning for the occurrence of, or departure from, a gi"en "alue in the string. 0D1 loads a string element from the source operand into A &or A@ for %ord strings'. This operation ordinaril# %ould not be repeated.

1T01 stores a string element from A &or A@ for %ord strings' into the destination operand. As a repeated operation this pro"ides for filling a string %ith a gi"en "alue.

So#t!are operation control. The repeat prefix pro"ides for rapid iteration in a hard%arerepeated string operation. 2teration-control operations pro"ide this same control for implementing soft%are loops to perform complex string operations. These iteration operations pro"ide the same operation count update, operation completion test, and /9 flag tests that the repeat prefix pro"ides. The iteration-control transfer operations perform leading- and trailing-decision loop control. The destinations of iteration-control transfers must be %ithin a AD:-b#te range centered about the instruction. 9our iteration-control transfer operations are pro"ided; 005 decrements the C@ &>count>' register b# * and transfers if C@ is not ,. 005E decrements the C@ register b# * and transfers if C@ is not , and the /9 flag is set &loop %hile e8ual', 0054E decrements the C@ register b# * and transfers if C@ is not , and the /9 flag is cleared &loop %hile not e8ual'. HC@/ transfers if the C@ register is ,. This is used for s!ipping o"er a loop %hen the initial count is ,. B# combining the primiti"e string operations and iteration- control operations %ith other operations, it is possible to build sophisticated #et efficient string manipulation routines. 0ne instruction that is particularl# useful in this context is the translate operation( it permits a b#te fetched from one string to be translated before being stored in a second string, or before being operated upon in some other fashion. The translation is performed b# using the "alue in the A register to index into a table pointed at b# the B@ register. The translated "alue obtained from the table then replaces the "alue initiall# in the A register. As an example of use of the primiti"e string operations and iteration-control operations to implement a complex string operation, consider the follo%ing application; An input dri"er must translate a buffer of EBCD2C characters into A1C22 and transfer characters until one of se"eral different EBCD2C control characters is encountered. The transferred A1C22 string is to be terminated %ith an E0T character. To accomplish this, 12 is initiali7ed to point to the beginning of the EBCD2C buffer, D2 is initiali7ed to point to the beginning of the buffer to recei"e the A1C22 characters, B@ is made to point to an EBCD2C-to-A1C22 translation table, and C@ is initiali7ed to contain the length of the EBCD2C buffer &possibl# empt#'. The translation table contains the A1C22 e8ui"alent for each EBCD2C character, perhaps %ith A1C22 nulls for illegal characters. The E0T code is placed into those entries in the table corresponding to the desired EBCD2C stop characters. The 8,8: instruction se8uence to implement this example is the follo%ing;

HC@/ Empt# 4ext; 0D1 Ebcbuf (fetch next EBCD2C character @ AT Table (translate it to A1C22 C$5 A , E0T (test for E0T

1T01 Ascbuf (transfer A1C22 character 0054E 4ext (continue if not E0T Empt#; 4he body o5 this loop re>uires Gust seven bytes o5 code. 6. Trans)er o) Control. Transfer-of-control instructions &6umps, calls, returns' in the 8,8: are
of t%o basic "arieties; intrasegment transfers, %hich transfer control %ithin the current code segment b# specif#ing a ne% "alue for 25, and intersegment transfers, %hich transfer control to an arbitrar# code segment b# specif#ing a ne% "alue for both C1 and 25. 9urthermore, both direct and indirect transfers are supported. Direct transfers specif# the destination of the transfer &the ne% "alue of 25 and possibl# C1' in the instruction( indirect transfers ma!e use of the standard addressing modes, as described pre"iousl#, to locate an operand %hich specifies the destination of the transfer. B# contrast, the 8,8, pro"ides onl# direct intrasegment transfers. 9acilities for position-independent code and coding efficienc# not found in the 8,8, ha"e been introduced in the 8,8:. 2ntrasegment direct calls and 6umps specif# a self-relati"e direct displacement, thus allo%ing position-independent code. A shortened 6ump instruction is a"ailable for transfers %ithin a AD:-b#te range centered about the instruction, thus allo%ing for code compaction. -eturns ma# optionall# ad6ust the 15 register so as to discard stac!ed parameters, thereb# ma!ing parameter passing more efficient. This is a more complete solution to the problem than the 8,8, instruction %hich exchanged the contents of the H %ith the top of the stac!. The 8,8, pro"ided conditional 6umps useful for determining relations bet%een unsigned numbers. The 8,8: augments these %ith conditional 6umps for determining relations bet%een signed numbers. Table + sho%s the conditional 6umps as a function of flag settings. The seldom-used conditional calls and returns pro"ided b# the 8,8, ha"e not been incorporated into the 8,8:.

Table 3 8086 Conditional >umps as a Function o) Fla' ettin's Mump on @lag settings

N73: . . . . . . . . . . . . . . . . . . . . . . . .I@ J $ &O4 N73: . . . . . . . . . . . . . . . . . . . I@ J ' : SS 4<3& . . . . . . . . . . . . . . . . . . . .9S@ =or O@; J $ OR 34 R 4<3& . . . . . . . . . . . . . . . 99S@ =or O@; or I@; J ' : SS 4<3& OR N73: . . . . . . . . . 99S@ =or O@; or I@; J $ OR 34 R 4<3& OR N73: . . . . .9S@ =or O@; J ' B :OW . . . . . . . . . . . . . . . . . . . . . . . !@J$ 3BO# . . . . . . . . . . . . . . . . . . . . . . . 9!@ or I@; J ' B :OW OR N73: . . . . . . . . . . . . .9!@ or I@; J $ 3BO# OR N73: . . . . . . . . . . . . .!@ J ' P3RI4F # & . . . . . . . . . . . . . . . . . P@ J $ P3RI4F O66 . . . . . . . . . . . . . . . . . . P@ J ' O# R@:OW . . . . . . . . . . . . . . . . . . . O@ J $ &O O# R@:OW . . . . . . . . . . . . . . . .O@ J ' SIO& . . . . . . . . . . . . . . . . . . . . . . . . . .S@J$

&O SIO& . . . . . . . . . . . . . . . . . . . . . ..S@J'

5. ?4ternal Inter)ace. The 8,8: processor pro"ides both common and uncommon interfaces
to external e8uipment. The t%o "arieties of interrupts, mas!able and non-mas!able, are not uncommon, nor is single-step diagnostic capabilit#. $ore unusual is the abilit# to escape to an external processor to perform speciali7ed operations. Also uncommon is the hard%are mechanism to control access to shared resources in a multiple-processor configuration.

Interrupts. The 8,8, interrupt mechanism %as general enough to permit the interrupting de"ice
to suppl# an# operation to be executed out of se8uence %hen an interrupt occurs. Ho%e"er, the onl# operation that had an# utilit# for interrupt processing %as the *-b#te subroutine call. This b#te consists of D bits of opcode and ) bits identif#ing one of eight interrupt subroutines residing at eight fixed locations in memor#. 2f the unnecessar# generali7ation %as remo"ed, the interrupting de"ice %ould not ha"e to pro"ide the opcode and all 8 bits could be used to identif# the interrupt subroutine. 9urthermore, if the 8 bits %ere used to index a table of subroutine addresses, the actual subroutine could reside an#%here in memor#. This is the e"olutionar# process that led to the design of the 8,8: interrupt mechanism. 2nterrupts result in a transfer of control to a ne% location in a ne% code segment. A AD:-element table &interrupt transfer "ector' containing pointers to these interrupt ser"ice code locations resides at the beginning of memor#. Each element is four b#tes in si7e, containing an offset address and the high-order *:-bits of the start address of the ser"ice code segment. Each element of this table corresponds to an interrupt t#pe, these t#pes being numbered , to ADD. All interrupts perform a transfer b# pushing the current flag setting onto the stac! and then performing an indirect call &of the intersegment "ariet#' through the interrupt transfer "ector. The 8,8: processor recogni7es t%o "arieties of external interrupt-the non-mas!able interrupt and the mas!able interrupt. A pin is pro"ided for each "ariet#. 5rogram execution control ma# be transferred b# means of operations similar in effect to that of external interrupts. A generali7ed A-b#te instruction is pro"ided that generates an interrupt of an# t#pe( the t#pe is specified in the second b#te. A special *-b#te instruction to generate an interrupt of one particular t#pe is also pro"ided. 1uch an instruction %ould he re8uired b# a soft%are debugger so that brea!points can be >planted> on *-b#te instructions %ithout o"er%riting, e"en temporaril#, the next instruction. And finall#, an interrupt return instruction is pro"ided %hich pops and restores the sa"ed flag settings in addition to performing the normal subroutine return function.

Single step. Chen the T9 flag register is set, the processor generates an interrupt after the
execution of each instruction. During interrupt transfer se8uences caused b# an# t#pe of interrupt, the T9 flag is cleared after the push-flags step of the interrupt se8uence. 4o instructions are pro"ided for setting or clearing T9 directl#. -ather, the flag-register file image sa"ed on the stac! b# a pre"ious interrupt operation must be modified so that the subse8uent interrupt return

operation restores T9 set. This allo%s a diagnostic tas! to single-step through a tas! under test %hile still executing normall# itself.

External$processor sync%roni&ation. 2nstructions are included that permit the 8,8: to utili7e an
external processor to perform an# speciali7ed operations &e.g., exponentiation' not implemented on the 8,8:. Consideration %as gi"en to the abilit# to perform the speciali7ed operations either "ia the external processor or through soft%are routines, %ithout ha"ing to recompile the code. The external processor %ould ha"e the abilit# to monitor the 8,8: bus and constantl# be a%are of the current instruction being executed. 2n particular, the external processor could detect the special instruction E1CA5E and then perform the necessar# actions. 2n order for the external processor to !no% the A,-bit address of the operand for the instruction, the 8,8: %ill react to the E1CA5E instruction b# performing a read &but ignoring the result' from the operand address specified, thereb# placing the address on the bus for the external processor to see. Before doing such a dumm# read, the 8,8: %ill ha"e to %ait for the external processor to be read#. The >test> pin on the 8,8: processor is used to pro"ide this s#nchroni7ation. The 8,8: instruction CA2T accomplishes the %ait. 2f the external processor is not a"ailable, the speciali7ed operations could be performed b# soft%are subroutines. To in"o!e the subroutines, an interrupt-generating instruction %ould be executed. The subroutine needs to be passed the specific speciali7ed-operation opcode and address of the operand. This information %ould be contained in an in-line data b#te &or b#tes' follo%ing the interrupt-generating instruction. The same number of b#tes are re8uired to issue a speciali7ed operation instruction to the external processor or to in"o!e the soft%are subroutines, as illustrated in 9igure I. Thus the compiler could generate ob6ect code that could be used either %a#. The actual determination of %hich %a# the speciali7ed operations %ere carried out could be made at load time and the ob6ect code modified b# the loader accordingl#.

Fi'ure @. ?4ample o) e4ecutin' speciali1ed instructions in 8086. S%aring resources !it% parallel processors. 2n multiple-processor s#stems %ith shared
resources it is necessar# to pro"ide mechanisms to enforce controlled access to those resources. 1uch mechanisms, %hile generall# pro"ided through soft%are operating s#stems, re8uire hard%are assistance. A sufficient mechanism for accomplishing this is a loc!ed exchange &also !no%n as test-and-set-loc!'. The 8,8: pro"ides a special *-b#te prefix %hich ma# precede an# instruction. This prefix causes the processor to assert its bus-loc! signal for the duration of the operation caused b# the instruction. 2t is assumed that external hard%are, upon receipt of that signal, %ill prohibit bus access for other bus masters during the period of its assertion.

The instruction most useful in this context is an exchange register %ith memor#. A simple soft%are loc! ma# be implemented %ith the follo%ing code se8uences;

Chec!; $0B A ,* (set A to * &implies loc!ed' 0C= @CH3 1ema,A (test and set loc! TE1T A ,A (set flags based on A H4/ Chec! (retr# if loc! alread# set J (critical region $0B 1ema,, (clear the loc! %hen done IA. ummar( and Conclusions 14he -''- begat the -'-'" and the -'-' begat the -'-." and the -'-. begat the -'-+.1 6uring the si= years in /hich the -''- evolved into the -'-+" the processor under/ent changes in many areas" as depicted by the conceptual diagram o5 @igure $'. !omparisons in per5ormance and technology are sho/n in 4ables . and +. 4he era o5 the -''- through the -'-+ is architecturally notable 5or its role in e=ploiting technology and capabilities" thereby lo/ering computing costs by over three orders o5 magnitude. By removing a dominant hurdle that has inhibited the computer industry E the necessity to conserve e=pensive processors E the ne/ era has permitted system designers to concentrate on solving the 5undamental problems o5 the applications themselves.

Fi'ure 10. 8008-8086 evolution. Table - !er)ormance Comparison -''register*register trans5er $).. -'-' 9) M<z; ) -'-+ 9- M<z; '.).

Gump register*immediate operation subroutine call increment 9$+*bit; addition 9$+*bit; trans5er 9$+*bit;

). )' ).' 2. ).

. %.. , ).. . )

'.-2. '.. ).. '.). '.%2. '.).

3ll times are given in microseconds. Table 6 Tec"nolo'( Comparison -''Silicon gate technology P*channel enhancement load device -'-' &*channel enhancement load device -'-. &*channel depletion load device -'-+ Scaled &* channel 9<MOS; depletion load device .*- M<z % ns ) pG )'"'''Q )..

!loc0 rate Min gate delay B @' J @$ J $ 4ypical speed* po/er product 3ppro=imate number o5 transistorsP 3verage transistor density 9mil) per transistor;

'..*'.- M<z %' ns C $'' pG )"''' -.(

)*% M<z $. ns C (' pG (".'' 2..

%*. M<z . ns $' pG +".'' ..2

B @astest inverter 5unction available /ith /orst*case processing. C :inear*mode enhancement load. Q 4his is ),"''' transistors i5 all ROM and P:3 available placement sites are counted. P Oate e>uivalent can be estimates by dividing by %. A. ,e)erences Bylins0y" O." 1<ere !omes the Second !omputer Revolution"1 'ortune( &ovember $,2..

@aggin" @." M. Shima" M. . <o55" Mr." <. @eeney" and S. Mazor" 14he M!S*(H 3n :SI Micro !omputer System"1 IEEE Region ) *on#. +,-.( pp. -*$$. <o55" M. ." Mr." 14he &e/ :SI !omponents"1 )t% Annual IEEE *omp. Soc. /ut. *on#( $,2). Intel -'-' Microcomputer Systems 7ser?s Manual" September $,2.. Intel M!S*- 7ser?s Manual" 3pril $,2. Intel M!S*(' 7ser?s Manual" %d ed." March $,2+. Intel M!S*-. 7ser?s Manual" March $,22. Intel M!S*-+ 7ser?s Manual" Muly $,2-. Morse" S. PH 14he -'-+ Primer"1 <ayden Boo0 !o." &e/ For0" $,-'. Morse" S. P." W. B. Pohlman" and B. W. Ravenel" 14he Intel -'-+ Micropocessor 3 $+* Bit volution o5 the -'-'"1 *omputer( Mune $,2-" pp. $-*)2. Shima" M." @. @aggin" and S. Mazor" 13n &*!hannel -*Bit Single !hip Microprocessor"1 IEEE Int. Solid$State *ircuits *on#( @ebruary $,2(" pp. .+*.2. #adasz" :. :." 3. S. Orove" 4. 3. Ro/e" and O. . Moore" 1Silicon Oate 4echnology"1 IEEE Spectrum( October $,+," pp. )2*%..
APP !DI" # $A%I!& A!D ' $TO'I!& ()A&$ I! T* 8008

Interrupt routines must leave all processor 5lags and registers unaltered so as not to contaminate the processing that /as interrupted. 4his is most simply done by having the interrupt routine save all 5lags and registers on entry and restore them prior to e=iting. 4he -''-" unli0e its successors" has no instruction 5or directly saving or restoring 5lags. 4hus -''- interrupt routines that alter 5lags 9practically every routine does; must conditionally test each 5lag to obtain its value and then save that value. Since there are no instructions 5or directly setting or clearing 5lags" the 5lag values must be restored by e=ecuting code that /ill put the 5lags in the saved state. 4he -''- 5lags can be restored very e55iciently i5 they are saved in the 5ollo/ing 5ormat in a byte in memory. Most signi5icant bit J bit 2 bit 2 J original value o5 !3RRF bit + J original value o5 SIO& bit . J original value o5 SIO&

bit ( J ' bit % J ' bit ) J complement o5 original value o5 I RO bit $ J complement o5 original value o5 I RO bit ' J complement o5 original value o5 P3RI4F With the in5ormation saved in the above 5ormat in a byte called @:3OS" the 5ollo/ing t/o instructions /ill restore all the saved 5lag valuesH DA 9 A31 (load sa"ed flags into accumulator ADD A (add the accumulator to itself 4his instruction se>uence loads the saved 5lags into the accumulator and then doubles the value" thereby moving each bit one position to the le5t. 4his causes each 5lag to be set to its original value" 5or the 5ollo/ing reasonsH 4he original value o5 the !3RRF 5lag" being in the le5tmost bit" /ill be moved out o5 the accumulator and /ind up in the !3RRF 5lag. 4he original value o5 the SIO& 5lag" being in bit +" /ill /ind up in bit 2 and /ill become the sign o5 the result. 4he ne/ value o5 the SIO& 5lag /ill re5lect this sign. 4he complement o5 the original value o5 the P3RI4F 5lag /ill /ind up in bit $" and it alone /ill determine the parity o5 the result 9all other bits in the result are paired up and have no net e55ect on parity;. 4he ne/ setting o5 the P3RI4F 5lag /ill be the complement o5 this bit 9the 5lag denotes even parity; and there5ore /ill ta0e on the original value o5 the P3RI4F 5lag. Whenever the I RO 5lag is $" the SIO& 5lag must be ' 9zero is a positive t/o?s* complement number; and the P3RI4F 5lag must be $ 9zero has even parity;. 4hus an original I RO 5lag value o5 $ /ill cause all bits o5 @:3OS" /ith the possible e=ception o5 bit 2" to be '. 35ter the 366 instruction is e=ecuted" all bits o5 the result /ill be ' and the ne/ value o5 the I RO 5lag /ill there5ore be $. 3n original I RO 5lag value o5 ' /ill cause t/o bits in @:3OS to be $ and /ill /ind up in the result as /ell. 4he ne/ value o5 the I RO 5lag /ill there5ore be '. 4he above algorithm relies on the 5act that 5lag values are al/ays consistent" i.e." that the SIO& 5lag cannot be a $ /hen the I RO 5lag is a $. 4his is al/ays true in the -''-" since the 5lags come up in a consistent state /henever the processor is reset and 5lags can only be modi5ied by instructions /hich al/ays leave the 5lags in a consistent state. 4he -'-' and its derivatives allo/ the programmer to modi5y the 5lags in an arbitrary manner by popping a value o5 his choice o55 the stac0 and into the 5lags. 4hus the above algorithm /ill not /or0 on those processors. 3 code se>uence 5or saving the 5lags in the re>uired 5ormat is as 5ollo/sH

$B2 A,, (mo"e 7ero in accumulator H4C * (6ump if CA--. not set 0-A 8,H (0- accumulator %ith 8, hex &set bit F' *; H/ ) (6ump if /E-0 set &and 1234 not set and 5A-2T. set' 0-A ,:H (0- accumulator %ith ,: hex &set bits * and A' H$ A ( 6ump if negati"e &1234 set' 0-A :,H (0- accumulator %ith :, hex &set bits D and :' A; H5E ) (6ump if parit# e"en &5A-2T. set' 0-A ,*H (0- accumulator %ith ,* hex &set bit ,' ); 1TA 9 A31 (store accumulator in 9 A31 $!!?B<IA # <?CIM$= $,ITCM?TIC A. "acked B*D $. 3ddition. &umbers can be represented as a se>uence o5 decimal digits by using a (*bit binary encoding o5 the digits and pac0ing these encodings t/o to a byte. Such a representation is called pac0ed B!6 9unpac0ed B!6 /ould contain only one digit per byte;. In order to preserve this decimal interpretation in per5orming binary addition on pac0ed B!6 numbers" the value + must be added to each digit o5 the sum /henever 9$; the resulting digit is greater than , or 9); a carry occurs out o5 this digit as a result o5 the addition. 4his is because the (*bit encoding contains si= more combinations than there are decimal digits. !onsider the 5ollo/ing e=amples 9numbers are /ritten in he=adecimal instead o5 binary 5or convenience;.
+ample #, 8#-.2

d) L L $

d$ . 6 + %

d' $ ) % %

names o5 digit positions pac0ed B!6 augend pac0ed B!6 addend adGustment because d$ R , pac0ed B!6 sum

?4ample #: #8D 1@ d) d$ ) d' names o5 digit positions pac0ed B!6 augend

L L

$ ( (

, $ + 2

pac0ed B!6 addend carry occurs out o5 d' adGustment 5or carry pac0ed B!6 sum

In order to be able to ma0e such adGustments" carries out o5 either digit position must be recorded during the addition operation. 4he (''(" -'-'" -'-." and -'-+ use the !3RRF and 37KI:I3RF !3RRF 5lag to record carries out o5 the le5tmost and rightmost digits respectively. 3ll o5 these processors provide an instruction 5or per5orming the adGustments. @urthermore" they all contain an add*/ith*carry instruction to 5acilitate the addition o5 numbers containing more than t/o digits. ). Subtraction. Subtraction o5 pac0ed B!6 numbers can be per5ormed in a similar manner. <o/ever" none o5 the Intel processors prior to the -'-+ provides an instruction 5or per5orming decimal adGustment 5ollo/ing a subtraction 9Iilog?s I*-'" introduced t/o years be5ore the -'-+" also has such an instruction;. On processors /ithout the subtract adGustment instruction" subtraction o5 pac0ed B!6 numbers can be accomplished by generating the ten?s complement o5 the subtrahend and adding. %. Multiplication. Multiplication o5 pac0ed B!6 numbers could also be adGusted to give the correct decimal result i5 the out*o5*digit carries occurring during the multiplication /ere recorded. 4he result o5 multiplying t/o one*byte operands is t/o bytes long 95our digits;" and out*o5*digit carries can occur on any o5 the three lo/*order digits" all o5 /hich /ould have to be recorded. @urthermore" the carries out o5 any digit are no longer restricted to unity" and so counters rather than 5lags /ould be re>uired to record the carries. 4his is illustrated in the 5ollo/ing e=ample 9numbers are /ritten in he=adecimal instead o5 binary 5or convenience;. ?4ample &: @3 E 6& d% S % % L L L ( $ 2 , + + + ! d) d$ , + B % + + + . d' ( % ! ! names o5 digit positions pac0ed B!6 multiplicand pac0ed B!6 multiplier carry occurs out o5 d$ carry occurs out o5 d$" three out o5 d) carry occurs out o5 d$ adGustment 5or... . . .above si=... ... carries carry occurs out o5 dl and out o5 d)

L . L . L . L .

+ ) + ,

+ B B ! + ) ! ! + )

adGustment 5or above t/o carries carry occurs out o5 d) adGustment 5or above carry adGustment because d' is greater than , adGustment because d$ is greater than , ) pac0ed B!6 product

4he preceding e=ample illustrates t/o 5acts. @irst" pac0ed B!6 multiplication adGustments are possible i5 the necessary out*o5*digit carry in5ormation is recorded by the multiply instruction. Second" the 5acilities needed in the processor to record this in5ormation and apply the correction are non*trivial. 3nother approach to determining the out*o5*digit carries is to analyze the multiplication process on a digit*by*digit basis as 5ollo/sH :et =$ and =) be pac0ed B!6 digits in multiplicand. :et y$ and y) be pac0ed B!6 digits in multiplier. Binary value o5 multiplicand J $+ S=$ L =) Binary value o5 multiplier J $+ S y$ L y) Binary value o5 product J ).+ S =$Sy$ L $+ S 9=$Sy) L =)Sy$; L=)Sy) J =$Sy$ in most signi5icant byte" =)sy) in least signi5icant byte" 9=$Sy) L =)Sy$; straddling both bytes I5 there are no cross terms 9i.e." either =$ or y) is zero and either =) or y$ is zero;" the number o5 out*o5*digit carries generated by the =$ S y$ term is simply the most signi5icant digit in the most signi5icant byte o5 the productD similarly the number o5 out* o5*digit carries generated by the =) S y) term is simply the most signi5icant digit in the least signi5icant byte o5 the product. 4his is illustrated in the 5ollo/ing e=ample 9numbers are /ritten in he=adecimal instead o5 binary 5or convenience;. ?4ample 3: @0 E #0 d% d) S $ ' ) d$ , ) ' ' d' ' ' ' names o5 digit positions pac0ed B!6 multiplier pac0ed B!6 multiplier

'

'

4he most signi5icant digit o5 the most signi5icant byte is $" indicating that there /as one out*o5*digit carry 5rom the lo/*order digit /hen the ,S) term /as 5ormed" 3dGustment is to add + to that digit. $ L $ ) + ' ' ' adGustment ' pac0ed B!6 product

4hus" in the absence o5 cross terms" the number o5 out*o5*digit carries that occur during a multiplication can be determined by e=amining the binary product. 4he cross terms" /hen present" overshado/ the out*o5*digit carry in5ormation in the product" thereby ma0ing the use o5 some other mechanism to record the carries essential. &one o5 the Intel processors incorporates such a mechanism. 9Prior to the -'-+" multiplication itsel5 /as not even supported.; Once it /as decided not to support pac0ed B!6 multiplication in the processors" no attempt /as made to even analyze pac0ed B!6 division. B. 0npacked B*D 7npac0ed B!6 representation o5 numbers consists o5 storing the encoded digits in the lo/*order 5our bits o5 consecutive bytes. 3n 3S!II string o5 digits is a special case o5 unpac0ed B!6 /ith the high*order 5our bits o5 each byte containing '$$'. 3rithmetic operations on numbers represented as unpac0ed B!6 digit strings can be 5ormulated in terms o5 more primitive B!6 operations on single*digit 9t/o digits 5or dividends and t/o digits 5or products; unpac0ed B!6 numbers. $. 3ddition and Subtraction. Primitive unpac0ed additions and subtractions 5ollo/ the same adGustment procedures as pac0ed additions and subtractions. ). Multiplication. Primitive unpac0ed multiplication involves multiplying a one*digit 9one*byte; unpac0ed multiplicand by a one*digit 9one*byte; unpac0ed multiplier to yield a t/o*digit 9t/o*byte; unpac0ed product. I5 the high*order 5our bits o5 the multiplicand and multiplier are zeros 9instead o5 don?t*cares;" each /ill represent the same value interpreted as a binary number or as a B!6 number. 3 binary multiplication /ill yield a t/o*byte product in /hich the high*order byte is zero. 4he lo/*order byte o5 this product /ill have the correct value /hen interpreted as a binary number and can be adGusted to a t/o*byte B!6 number as 5ollo/sH <igh*order byte J 9binary product;/$' :o/*order byte J binary product modulo $'

4his is illustrated in the 5ollo/ing e=ample 9numbers are /ritten in he=adecimal instead o5 binary 5or convenience;. ?4ample -: 5 E d$ ' ' ) ) ' ' ) ' ' d' 2 . % % 3 % % 3 . names o5 digit positions unpac0ed B!6 multiplicand unpac0ed B!6 multiplier binary product binary product adGustment 5or high*order byte 9divide by $'; unpac0ed B!6 product 9high*order byte; binary product adGustment 5or lo/*order byte 9modulo $'; unpac0ed B!6 product 9lo/*order byte;

%. 6ivision. Primitive unpac0ed division involves dividing a t/o*digit 9t/o*byte; unpac0ed dividend by a one*digit 9one*byte; unpac0ed divisor to yield a one*digit 9one* byte; unpac0ed >uotient and a one*digit 9one*byte; unpac0ed remainder. I5 the high*order 5our bits in each byte o5 the dividend are zeros 9instead o5 don?t*cares;" the dividend can be adGusted to a one*byte binary number as 5ollo/sH Binary dividend J $' S high*order byte L lo/*order byte I5 the high*order 5our bits o5 the divisor are zero" the divisor /ill represent the same value interpreted as a binary number or as a B!6 number. 3 binary division o5 the adGusted 9binary; dividend and B!6 divisor /ill yield a one*byte >uotient and a one*byte remainder" each representing the same value interpreted as a binary number or as a B!6 number. 4his is illustrated in the 5ollo/ing e=ample 9numbers are /ritten in he=adecimal instead o5 binary 5or convenience;. ?4ample 6: 3-26 d$ ' ' ) ' ' ' d' ( . 6 + 2 % names o5 digit positions unpac0ed B!6 dividend 9high*order byte; unpac0ed B!6 dividend 9lo/*order byte; adGusted dividend 9( S $' L .; unpac0ed B!6 divisor unpac0ed B!6 >uotient unpac0ed B!6 remainder

(. 3dGustment Instructions. 4he -'-+ processor provides 5our adGustment instructions 5or use in per5orming primitive unpac0ed B!6 arithmetic*one 5or addition" one 5or subtraction" one 5or multiplication" and one 5or division. 4he addition and subtraction adGustments are per5ormed on a binary sum or di55erence assumed to be le5t in the one*byte 3: register. 4o 5acilitate multi*digit arithmetic" /henever 3: is altered by the addition or subtraction adGustments" the adGustments /ill also do the 5ollo/ingH set the !3RRF 5lag 9this 5acilitates multi*digit unpac0ed additions and subtractions; consider the one*byte 3< register to contain the ne=t most signi5icant digit and increment or decrement it as appropriate 9this permits the addition adGustment to be used in a multi* digit unpac0ed multiplication; 4he multiplication adGustment assumes that 3: contains a binary product and places the t/o*digit unpac0ed B!6 e>uivalent in 3< and 3:. 4he division adGustment assumes that 3< and 3: contain a t/o*digit unpac0ed B!6 dividend and places the binary e>uivalent in 3< and 3:. 4he 5ollo/ing algorithms sho/ ho/ the adGustment instructions can be used to per5orm multi*digit unpac0ed arithmetic. 3ddition :et augend J aT&U aT&* $U . . . aT)U aT$U :et addend J bT&U bT&* $U . . . bKAL bK*L
et sum M cK4L cK4-*L . . . cKAL cK*L , N 9!3RRF;

6O i J $ to & 9aTiU; V 93:; 93:; L 9bTiU; V 93:; /here L denotes add*/ith*carry add*adGust 93:; V 93K; 93:; V 9cTiU; Subtraction :et minuend J aT&U aT&* $U . . . aT)U aT$U :et subtrahend J bT&U bT& $U . . . bT)U billU :et di55erence J cT&U cT&*$U . . . cT)U cT$U ' V 9!3RRF; 6O i J $ to & 9aTiU; V 93:; 93:; * 9bTiU; V 93:; /here * denotes subtract*/ith*borro/

subtract*adGust 93:; V 93K; 93:; V 9cTiU; Multiplication :et multiplicand J aT&U aT&* $U . . . aT)U aT$U :et multiplier J b :et product J cT&L $U cT&U . . . cT)U cT$U 9b; 3&6 O@< V 9b; ' V 9cT$U; 6O i J $ to & 9aTiU; 3&6 O@< V 93:; 93:; S 9b; V 93K; multiply*adGust 93:; V 93K; 93:; L 9cTiU; V 93:; add*adGust 93:; V 93K; 93:; V 9cTiU; 93<; V 9cTiL $U; 6ivision :et dividend J aT&U aT&* $U . . . aT)U aT$U :et divisor J b :et >uotient J cT&U cT&*$U . . . cT)U cT$U 9b; and O<@ V 9b; ' V 93R; 6O i J & to $ 9aTiU; 3&6 O@< V 93:; divide*adGust 93K; V 93:; 93:; / 9b; V 93:; /ith remainder going into
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