Chapter

1
What We Will Learn
In this chapter, we will learn the following:

1. Definitions of system and embedded system. 2. Classification of embedded systems into three types. 3. Skills needed in designing an embedded system. he processing !nit "s# of the embedded system 1. Processor in an Embedded System $ processor is an important !nit in the embedded system hardware. $ microcontroller is an integrated chip that has the processor, memory and se%eral other hardware !nits in it& these form the microcomp!ter part of the embedded system. $n embedded processor is a processor with special feat!res that allow it to be embedded into a system. $ digital signal processor (DSP) is a processor meant for applications that process digital signals. '(or e)ample, filtering, noise cancellation, echo elimination, compression and encryption*. 2. Commonly !sed microprocessors, microcontrollers and DS+s in the small,, medi!m,and large, scale embedded systems. 3. $ recently introd!ced technology that additionally incorporates the application-specific system processors "ASSPs# in the embedded systems. -. .!ltiple processors in a system.

1. /mbedded system power source(s) and the need for controlled power,dissipation. 2. /mbedded system Clock oscillator circ!it and clocking !nit. It lets a processor e)ec!te and process instr!ctions. 3. Real time clock (RTC) timers and %ario!s timing needs of the system. -. Reset circuit and watc!dog timer. 0. System memories. 'In the second part of Chapter 2, we will learn the system memories in detail*. 1. System Inp!t 2!tp!t ""# # ports, serial 3ni%ersal $synchrono!s 4ecei%er and ransmitter ($ART) and other ports, m!ltiple)ers and dem!ltiple)ers and interfacing b!ses. ' hese will be dealt with in detail in Chapter 3*. 5. Interr!pt 6andler ' he latter part of Chapter - has the details*. 7. Interfacing !nits, D$C "Digital to $nalog Con%erter# !sing +8. "+!lse 8idth .od!lation#, $DC "$nalog to Digital Con%erter#, 9/D and 9CD display !nits, keypad and keyboard, p!lse dialer, modem and transcei%er :. 6ardware re;!ired for e)emplary embedded systems. Different le%els of lang!ages that are !sed to de%elop the embedded software for a system 'Chapter 0 details the high,le%el programming aspects, <C= and <C>>= lang!age str!ct!res and the application of these for coding embedded software*. 1. System de%ice dri%ers, de%ice management and m!ltitasking !sing an operating system "2S# and real time operating system "4 2S#. '4 2S "s# are dealt with in detail in Chapters : and 1?, and case st!dies !sing 4 2Ss in Chapter 11*. 2. Software tools in system designing. 3. Software tools re;!ired in si) e)emplary cases. -. +rogramming models for software designing. 'Software designing models are detailed in Chapter 1*. %&emplary applications of each type of embedded system. Designing an embedded system on a @9SI chip. 1. /mbedded SoC "System on Chip# and AS"C "$pplication Specific Integrated Circ!it# and e)amples of their applications. hese !se "i# $pplication Specific Instr!ction +rocessor "$SI+#, "ii# Intellect!al +roperty "I+# core, "iii# (ield +rogrammable Aate $rrays "(+A$# core with single or m!ltiple processor !nits on an $SIC chip. 2. Smart card an e)ample of the !nits of an embedded system on a chip "SoC#.

$ system is a way of working, organiBing or doing one or many tasks according to a fi)ed plan, program, or set of r!les. $ system is also an arrangement in which all its !nits assemble and work together according to the plan or program. 9et !s e)amine the following two e)amples. Consider a watch. It is a time-display system. Its parts are its hardware, needles and battery with the bea!tif!l dial, chassis and strap. These parts organize to show the real time e%ery second and contin!o!sly !pdate the time e%ery second. he system,program !pdates the display !sing three needles after each second. It follows a set of rules. Some of these r!les are as follows: "i# $ll needles mo%e clockwise only. "ii# $ thin and long needle rotates e%ery second s!ch that it ret!rns to same position after a min!te. "iii# $ long needle rotates e%ery min!te s!ch that it ret!rns to same position after an ho!r. "i%# $ short needle rotates e%ery ho!r s!ch that it ret!rns to same position after twel%e ho!rs. "%# $ll three needles ret!rn to the same inclinations after twel%e ho!rs each day. Consider a washing machine. It is an automatic clothes-washing system. he important hard, ware parts incl!de its stat!s display panel, the switches and dials for !ser,defined programming, a motor to rotate or spin, its power s!pply and control !nit, an inner water,le%el sensor, a solenoid %al%e for letting water in and another %al%e for letting water drain o!t. These parts organize to wash clothes a!tomatically according to a program preset by a !ser. The system-program is to wash the dirty clothes placed in a tank, which rotates or spins in pre,programmed steps and stages. It follows a set of rules. Some of these r!les are as follows: "i# (ollow the steps strictly in the following se;!ence. Step I: 8ash by spinning the motor according to a programmed period. Step II: 4inse in fresh water after draining o!t the dirty water, and rinse a second time if the system is not programmed in water,sa%ing mode. Step III: $fter draining o!t the water completely, spin fast the motor for a programmed period for drying by centrif!ging o!t water from the clothes. Step I@: Show the wash,o%er stat!s by a blinking display. So!nd the alarm for a min!te to signal that the wash cycle is complete. "ii# $t each step, display the process stage of the system. "iii# In case of an interr!ption, e)ec!te only the remaining part of the program, starting from the position when the process was interr!pted. here can be no repeti, tion from Step I !nless the !ser resets the system by inserting another set of clothes and resets the program.

$ comp!ter is a system that has the following or more components. 1. $ microprocessor 2. $ large memory comprising the following two kinds: "a# +rimary memory "semiconductor memories , 4$., 42. and fast accessible caches# "b# Secondary memory "magnetic memory located in hard disks, diskettes and cartridge tapes and optical memory in CD,42.# 3. Inp!t !nits like keyboard, mo!se, digitiBer, scanner, etc. -. 2!tp!t !nits like %ideo monitor, printer, etc. 0. Cetworking !nits like /thernet card, front,end processor,based dri%ers, etc.

1. ID2 !nits like a modem, fa) c!m modem, etc. An embedded system is one t!at !as computer-!ardware wit! software embedded in it as one of its most important component' It is a dedicated comp!ter,based system for an application"s# or prod!ct. It may be either an independent system or a part of a larger system. $s its software !s!ally embeds in 42. "4ead 2nly .emory# it does not need secondary memories as in a comp!ter. $n embedded system has three main components: 1. It has hardware. (ig!re 1.1 shows the !nits in the hardware of an embedded system. 2. It has main application software. he application software may perform conc!rrently the series of tasks or m!ltiple tasks. 3. It has a real time operating system "4 2S# that s!per%ises the application software and pro%ides a mechanism to let the processor r!n a process as per sched!ling and do the conte)t, switch between the %ario!s processes "tasks#. 4 2S defines the way the system works. It organiBes access to a reso!rce in se;!ence of the series of tasks of the system. It sched!les their working and e)ec!tion by following a plan to control the latencies and to meet the deadlines. '9atency refers to the waiting period between r!nning the codes of a task and the instance at which the need for the task arises.* It sets the r!les d!ring the e)ec!tion of the application software. $ small,scale embedded system may not need an 4 2S. $n embedded system has software designed to keep in %iew three constraints: "i# a%ailable system, memory, "ii# a%ailable processor speed and "iii# the need to limit power dissipation when r!nning the system contin!o!sly in cycles of wait for e%ents, r!n, stop and wake,!p. here are se%eral definitions of embedded systems gi%en in books p!blished recently. Ai%en below is a series of definitions from others in the field: 8ayne 8olf a!thor of Computers as Components Principles of Embedded Computing System esign!" E8hat is an embedded computing systemF 9oosely defined, it is any de%ice that incl!des a programmable comp!ter b!t is not itself intended to be a general,p!rpose comp!terG and Ea fa) ma, chine or a clock b!ilt from a microprocessor is an embedded comp!ting systemG. odd D. .orton a!thor of Embedded #icrocontrollers : EEmbedded Systems are electronic systems that contain a microprocessor or microcontroller, b!t we do not think of them as comp!ters , the comp!ter is hidden or embedded in the system.G Da%id /. Simon a!thor of $n Embedded Software Primer: E+eople !se the term embedded system to mean any comp!ter system hidden in any of these prod!cts.G im 8ilmsh!rst a!thor of $n Introduction to the esign of Small Scale Embedded System with e%amples from PIC& '(C)* and +',C()-(' #icrocontrollers : "1# E$n embedded system is a system whose principal f!nction is not comp!tational, b!t which is controlled by a comp!ter embedded within it. he comp!ter is likely to be a microprocessor or microcontroller. he word embedded implies that it lies inside the o%erall system, hidden from %iew, forming an integral part of greater wholeG. "2# E$n embedded system is a microcontroller,based, software,dri%en, reliable, real time control system, a!, tonomo!s, or h!man, or network,interacti%e, operating on di%erse physical %ariables and in di%erse en%ironments, and sold into a competiti%e and cost,conscio!s marketG.

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8e can classify embedded systems into three types as follows. 'Section 1.0 will gi%e e)amples of each type later*: 1. Small Scale Embedded Systems: hese systems are designed with a single 7, or 11,bit microcontroller& they ha%e little hardware and software comple)ities and in%ol%e board,le%el design. hey may e%en be battery operated. 8hen de%eloping embedded software for these, an editor, assembler and cross assembler, specific to the microcontroller or processor !sed, are the main programming tools. 3s!ally, <C= is !sed for de%eloping these systems. <C= program compilation is done into the assembly, and e)ec!table codes are then appropriately located in the system memory. he software has to fit within the memory a%ailable and keep in %iew the need to limit power dissipation when system is r!nning contin!o!sly. 2. Medium Scale Embedded Systems: hese systems are !s!ally designed with a single or few 11, or 32,bit microcontrollers or DS+s or 4ed!ced Instr!ction Set Comp!ters "4ISCs#. hese ha%e both hardware and software comple)ities. (or comple) software design, there are the following programming tools: 4 2S, So!rce code engineering tool, Sim!lator, Deb!gger and Integrated De%elopment /n%ironment "ID/#. Software tools also pro%ide the sol!tions to the

hardware comple)ities. $n assembler is of little !se as a programming tool. hese systems may also employ the readily a%ailable $SS+s and I+s "e)plained later# for the %ario!s f!nctionsLfor e)ample, for the b!s interfacing, encrypting, deciphering, discrete cosine transformation and in%erse transformation, C+DI+ protocol stacking and network connecting f!nctions. '$SS+s and I+s may also ha%e to be appropriately config!red by the system software before being integrated into the system,b!s.* 3. Sophisticated Embedded Systems: Sophisticated embedded systems ha%e enormo!s hardware and software comple)ities and may need scalable processors or config!rable processors and programmable logic arrays. hey are !sed for c!tting edge applications that need hardware and software co,design and integration in the final system& howe%er, they are constrained by the processing speeds a%ailable in their hardware !nits. Certain software f!nctions s!ch as encryption and deciphering algorithms, discrete cosine transformation and in%erse transformation algorithms, C+DI+ protocol stacking and network dri%er f!nctions are implemented in the hardware to obtain additional speeds by sa%ing time. Some of the f!nctions of the hardware reso!rces in the system are also implemented by the software. De%elopment tools for these systems may not be readily a%ailable at a reasonable cost or may not be a%ailable at all. In some cases, a compiler or retargetable compiler might ha%e to be de%eloped for these. '$ retargetable compiler is one that config!res according to the gi%en target config!ration in a system.*

M II

$n embedded system designer has to de%elop a prod!ct !sing the a%ailable tools within the gi%en specifications, cost and time frame. 'Chapters 5 and 12 will co%er the design aspects of embedded systems. See also Section 1.0.* 1. S.ills for Small Scale Embedded System esigner! $!thor im 8ilmsh!rst in the book referred abo%e "see page -#, has said that the following skills are needed in the indi%id!al or team that is de%eloping a small,scale system: E(!ll !nderstanding of microcontrollers with a basic knowledge of comp!ter architect!re, digital electronic design, software engineering, data comm!nication, control engineering, motors and act!ators, sensors and meas!rements, analog electronic design and IC design and man!fact!reG. Specific skills will be needed in specific sit!ations. (or e)ample, control engineering knowledge will be needed for design of control systems and analog electronic design knowledge will be needed when designing the system interfaces. Oasic aspects of the following topics will be described in this book to prepare the designer who already has a good knowledge of the microprocessor or microcontroller to be !sed. "i# Comp!ter architect!re and organiBation. "ii# .emories. "iii# .emory allocation. "i%# Interfacing the memories. "%# O!rning "a term !sed for porting# the e)ec!table machine codes in +42. or 42. "Section 2.3.1#. "%i# 3se of decoders and dem!ltiple)ers. "%ii# Direct memory accesses. "%iii# +orts. "i)# De%ice dri%ers in assembly. ")# Simple and sophisticated b!ses. ")i# imers. ")ii# Interr!pt ser%icing mechanism. ")iii# C programming elements. ")i%# .emory optimiBation. ")%# Selection of hardware and microcontroller. ")%i# 3se of IC/ "In,Circ!it, /m!lators#, cross,assemblers and testing e;!ipment. ")%ii# Deb!gging the software and hardware b!gs by !sing test %ectors. Oasic knowledge in the other areasLdata comm!nication, control engineering, motors and act!ators, sensors and meas!rements, analog electronic design and IC design and man!fact!reLcan be obtained from the standard te)tbooks a%ailable.

$ designer interested in small,scale embedded systems may not need at all concepts of interr!pt latencies and deadlines and their handling, the 4 2S programming tools described in Chapters : and 1? and program designing models gi%en in Chapter 1. 2. S.ills for #edium Scale Embedded System esigner! <C= programming and 4 2S , programming and program modeling skills are a m!st to design a medi!m,scale embedded, system. Pnowledge of the following becomes critical. "i# asks and their sched!ling by 4 2S. "ii# Cooperati%e and preempti%e sched!ling. "iii# Inter processor comm!nication f!nctions. "i%# 3se of shared data, and programming the critical sections and re,entrant f!nctions. "%# 3se of semaphores, mailbo)es, ;!e!es, sockets and pipes. "%i# 6andling of interr!pt,latencies and meeting task deadlines. "%ii# 3se of %ario!s 4 2S f!nctions. "%iii# 3se of physical and %irt!al de%ice dri%ers. '4efer to Chapters 7 to 1? for detailed descriptions of these se%en along with e)amples and to Chapter 11 to learn their !se with the help of case st!dies.* $ designer m!st ha%e access to an 4 2S programming tool with $pplication +rogramming Interfaces "$+Is# for the specific microcontroller to be !sed. Sol!tions to %ario!s f!nctions like memory, allocation, timers, de%ice dri%ers and interr!pt handing mechanism are readily a%ailable as the $+Is of the 4 2S. he designer needs to know only the hardware organiBation and !se of these $+Is. he microcontroller or processor then represents a small system element for the designer and a little knowledge may s!ffice. 3. S.ills for Sophisticated Embedded System esigner! $ team is needed to co,design and sol%e the high le%el comple)ities of the hardware and software design. $n embedded system hardware engineer sho!ld ha%e f!ll skills in hardware !nits and basic knowledge of <C=, 4 2S and other programming tools. Software engineer sho!ld ha%e basic knowledge in hardware and a thoro!gh knowledge of <C=, 4 2S and other programming tools. $ final optim!m design sol!tion is then obtained by system integration.

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$ processor is the heart of the embedded system. (or an embedded system designer, knowledge of microprocessors and microcontrollers is a prere;!isite. In the following e)planations, too, it has been pres!med that the reader has a thoro!gh !nderstanding of microprocessors or microcontrollers. ' he reader may refer to a standard te)t or the te)ts listed in the <4eferences= at the end of this book for an in,depth !nderstanding of microprocessors, microprocessors and DS+s that are incorporated in em, bedded system design.*

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$ processor has two essential !nits: +rogram (low Control 3nit "C3# and /)ec!tion 3nit "/3#. he C3 incl!des a fetch !nit for fetching instr!ctions from the memory. he /3 has circ!its that imple, ment the instr!ctions pertaining to data transfer operations and data con%ersion from one form to another. he /3 incl!des the $rithmetic and 9ogical 3nit "$93# and also the circ!its that e)ec!te instr!ctions for a program control task, say, halt, interr!pt, or R!mp to another set of instr!ctions. It can also e)ec!te instr!ctions for a call or branch to another program and for a call to a f!nction. $ processor r!ns the cycles of fetch and e)ec!te. he instr!ctions, defined in the processor in, str!ction set, are e)ec!ted in the se;!ence that they are fetched from the memory. $ processor is

mostly in the form of an IC chip& alternati%ely, it co!ld be in core form in an $SIC or at a SoC. Core means a part of the f!nctional circ!it on the @9SI chip. $n embedded system processor chip or core can be one of the following" 1. Aeneral +!rpose +rocessor "A++#: a. .icroprocessor. '4efer to Section 1.2.2.* b. .icrocontroller. '4efer to Section 1.2.3.* c . /mbedded +rocessor. '4efer to Section 1.2.-.* d. Digital Signal +rocessor "DS+#. '4efer to Section 1.2.0.* e. .edia +rocessor. '4efer to $ppendi) / Section /.1.* 2. $pplication Specific System +rocessor "$SS+# as additional processor '4efer to Section 1.2.1.* 3. .!ltiprocessor system !sing Aeneral +!rpose processors "A++s# and $pplication Specific Instr!ction +rocessors "$SI+s# '4efer to Section 1.2.5.* -. A++ core "s# or $SI+ core "s# integrated into either an $pplication Specific Integrated Circ!it "$SIC#, or a /ery 0arge Scale Integrated Circuit "@9SI# circ!it or an (+A$ core integrated with processor !nit"s# in a @9SI "$SIC# chip. '4efer to Section 1.1.* (or a system designer, the following are important considerations when selecting a processor: 1. Instr!ction set. 2. .a)im!m bits in an operand "7 or 11 or 32# in a single arithmetic or logical operation. 3. Clock fre;!ency in .6B and processing speed in .illion Instr!ctions +er Second "("PS#. '4efer to $ppendi) O for an alternate metric D!yrystone for processing performance.* -. +rocessor ability to sol%e the comple) algorithms !sed in meeting the deadlines for their processing.

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he C+3 is a !nit that centrally fetches and processes a set of general,p!rpose instr!ctions. he C+3 instr!ction set "Section 2.-# incl!des instr!ctions for data transfer operations, $01 operations, stac. operations, input and output "ID2# operations and program control, se2uencing and super3ising opera, tions. he general p!rpose instr!ction set "refer to $ppendi) $, Section $.1# is always specific to a specific C+3. $ny C+3 m!st possess the following basic f!nctional !nits. 1. $ control !nit to fetch and control the se;!ential processing of a gi%en command or instr!ction and for comm!nicating with the rest of the system. 2. $n $93 for the arithmetic and logical operations on the bytes or words. It may be capable of processing 7, 11, 32 or 1- bit words at an instant.

$ microprocessor is a single /0SI chip that has a CP1 and may also ha3e some other units "for e)amples, caches, floating point processing arithmetic unit, pipelining and super-scaling units # that are additionally present and that res!lt in faster processing of instr!ctions. '4efer to Section 2.1.* he earlier generation microprocessor=s fetch,and,e)ec!te cycle was g!ided by clock fre;!ency of the order of T1 .6B. +rocessors now operate at clock fre;!ency of 2 A6B. 'Intel released a 2 A6B processor on $!g!st 20, 2??1. his also marked the twentieth anni%ersary of the introd!ction of the IO. +C. Intel released 3 A6B +enti!m - on $pril 1-, 2??3.* Since early 2??2, a few highly sophisti, cated embedded systems "for e)amples, Abps transcei%er and encryption engine# ha%e incorporated the A6U processor. 'Abps means Aiga bit per second. ranscei%er means a transmitting c!m recei%, ing circ!it with appropriate processing and controls, for e)ample, for b!s,collisions.* 2ne e)ample of an older generation microprocessor is Intel 7?70. It is an 7,bit processor. $nother is Intel 7?71 or 7?77, which is a 11,bit processor. Intel '(%'+ (also referred as %'+4 processors are the 56-bit successors of '('+. ' he % here means e)tended 7?71 for 32 bits.* /)amples of 32,bit proces, sors in 7?)71 series are Intel 7?371 and 7?-71. .ostly, the IO. +Cs !se 7?%71 series of processors and the embedded systems incorporated inside the +C for specific tasks "like graphic accelerator, disk controllers, network interface card# !se these microprocessors. $n e)ample of the new generation 32, and 1-,bit microprocessor is the classic Pentium series of processors from Intel. hese ha%e s!perscalar architect!re 'Section 2.1*. hey also possess powerf!l $93s and (loating +oint +rocessing 3nits "(9+3s# ' able 2.1*. $n e)ample of the !se of +enti!m III operating at 1 A6B clock fre;!ency in an embedded system is the </ncryption /ngine=. his gi%es encrypted data at the rate of ?.-1- Abps. able 1.1.lists the important microprocessors !sed in the embedded systems. he microprocessors are among the following streams of families:
JI Stream
Stream 1 Stream 2 Stream 3 Stream -

he microprocessors from Streams 1 and 2 ha%e Complicated Instr!ction Set Comp!ter "CISC# architect!re 'Section $.1*. .icroprocessors form Streams 3 and - ha%e 4ed!ced Instr!ction Set Comp!ter "4ISC# architect!re 'Section $.1.-*. $n 4ISC processor pro%ides speedy processing of the instr!ctions, each in a single clock,cycle. (!rther, besides the greatly enhanced capabilities mentioned abo%e, V there is great enhancement of the speed by which an instr!ction from a set is processed. h!mb Instr!ction set is a new ind!stry standard that also gi%es a red!ced code density in

a 4ISC processor. ' he concepts of architect!re feat!res of the processor in an embedded system, C"SC and

R"SC processors and processor instr!ction,set will be e)plained later in $ppendices $ and O.* R"SCs are used w!en t!e system needs to perform intensi)e computation for e&ample in a speec! process- ing system' 6ow does a system designer select a microprocessorF his will be e)plained in Section 2.2. " H N # H

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W!st as a microprocessor is the most essential part of a comp!ting system, a microcontroller is the most essential component of a control or comm!nication circ!it. A microcontroller is a single-c!ip *+S" unit (also called ,microcomputer-) w!ic! t!oug! !a)ing limited computational capabilities possesses en!anced input-output capabilities and a number of on-c!ip functional units. '4efer to Section 1.3 for %ario!s f!nctional !nits.* .icrocontrollers are partic!larly s!ited for !se in embedded systems for real,time control applications with on-chip program memory and de%ices. (ig!re 1.2 shows the f!nctional circ!its present "in solid bo!ndary bo)es# in a microcontroller. It also shows the application,specific !nits "in dashed bo!ndary bo)es# in a specific %ersion of a gi%en microcontroller family. $ few of the latest microcontrollers also ha%e high comp!tational and s!perscalar processing capabilities. '(or the meaning of s!perscalar architect!re, refer to Section 2.1.* $ppendi) C gi%es the comparati%e f!nctionalities of select microcontroller representati%es from these families. Important microcontroller chips for embedded systems are !s!ally among the following fi%e streams of families gi%en in able 1.2.
JI Stream
Stream 1 Stream 2 Stream 3 Stream Stream 0Q

2ther pop!lar microcontrollers are as follows. "i# 6itachi 67) family and S!per6 5))). "ii# .its!bishi 5-?, 55??, .11C and .32C families. "iii# Cational Semicond!ctor C2+7 and C411 D11C. "i%# oshiba 9CS :??S "%# e)as Instr!ments .S+ -3? for low %oltage battery based system. "%i# Sams!ng S$.7. "%ii# Uiglog U7? and eU7? K 7?)71 .icrocontroller %ersions "typically 7?177 eight bit processor or 7?371 si)teen bit processor# with each, there
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are the 1- kO memory, 3 timers and 2 D.$ channels.

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4efer Sections 1.2.- and O.1

(ig!re 1.3 shows commonly !sed microcontrollers in the small,, medi!m, and large,scale embed, ded systems. In Section C.1 "refer to ables C.1.1 to C.1.3 therein# those feat!res will be described that ha%e to be considered by a system designer before choosing a microcontroller as a processing !nit.

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(or fast, precise and intensi%e calc!lations and for comple) real time applications, the microcontrollers and microprocessors mentioned abo%e do not s!ffice. $n electronics warfare system, for e)ample, an $d%anced 8arning and Control System "$8$CS#, which also associates tracking radar, is an e)am, ple of a comple) real,time system. Special microprocessors and microcontrollers, often called embed,

ded processors, are re;!ired.8hen a microcontroller or microprocessor is specially designed s!ch that it has the following capabilities, then the term embedded processor is preferred instead of microcontroller or microprocessor. 1. (ast conte)t switching and th!s lower latencies of the tasks in comple) real time applications. '4efer to Section -.1* 2. $tomic $93 operations and th!s no shared data problem. he latter occ!rs d!e to an incomplete $93 "non,atomic# operation when an operand of a larger n!mber of bits is placed in two or fo!r registers. '4efer to Section 2.1.* 3. 4ISC core for fast, more precise and intensi%e calc!lations by the embedded software. Calc!lations for real time image processing and for aerodynamics are two e)amples where there is a need for fast, precise and intensi%e calc!lations and fast conte)t,switching. Important embedded processor chips for embedded systems belong to the following two streams of families. Y Stream 1: $4. family $4. 5Q and $4. :Q Y Stream 2: Intel family i:1?.

$ppendi) O describes $4. family processors. hese are a%ailable in single chip C+3 %ersion as well in file %ersion for embedding on a @9SI chip or for a SoC sol!tion for the embedded system. 4efer to Section 1.1.
Intel family i:1? microcontrollers are also called embedded processors, as these possess the re, ;!ired feat!res incl!ding CISC and 4ISC "Section $.1.-#. In one of the %ersions, these also ha%e a -, channel D.$ controller "Section 2.1#. $n 7?:1? incl!des an 7,channel, 2-7,%ector programmable interr!pt controller.

Y Stream 3: $.D family 2:?0?.

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W!st as a microprocessor is the most essential !nit of a comp!ting system, a digital signal processor "DS+# is an essential !nit of an embedded system for a large n!mber of applications needing process, ing of signals. /)emplary applications are in image processing, m!ltimedia, a!dio, %ideo, 6D @, DS+ modem and telecomm!nication processing systems. DS+s also find !se in systems for recogniBing an image pattern or a DC$ se;!ence fast. $ppendi) D describes in detail the embedded system DS+s. he DS+ as a A++ is a single chip @9SI !nit. It possesses the comp!tational capabilities of a microprocessor and also has a .!ltiply and $cc!m!late ".$C# !nit"s#. Cowadays, a typical DS+ has a 11 ) 32 .$C !nit. $ DS+ pro%ides fast, discrete,time, signal,processing instr!ctions. It has @ery 9arge Instr!ction 8ord "@9I8# processing capabilities& it processes Single Instr!ction .!ltiple Data "SI.D# instr!c, tions fast& it processes Discrete Cosine ransformations "DC # and in%erse DC "IDC # f!nctions fast. he latter are a m!st for fast e)ec!tion of the algorithms for signal analysing, coding, filtering, noise cancellation, echo,elimination, compressing and decompressing, etc. Important DS+s for the embedded systems are from three streams as gi%en in able 1.3.
JI SN Stream
Stream 1 Stream 2 Stream 3

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(or e)ample, .S32?C12ZZ for fi)ed point DS+ at clock speed of 2?? .6B. 4efer to Section D.- for a detailed description.
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9ately a new class of embedded systems has emerged. Systems additionally incorporates the $pplica, tion Specific System processor $SS+ chip"s# or core "s# in its design. hese ha%e been recently become a%ailable. $ss!me that there is an embedded system for real,time %ideo processing. 4eal,time processing need in embedded systems arises for digital tele%ision, high definition @ decoders, set,!p bo)es, D@D "Digital @ideo Disc# players, 8eb phones, %ideo,conferencing and other systems. he process, ing needs a %ideo compression and decompression system, which incorporates an .+/A 2 or .+/A - standard. '.+/A stands for .otion +ict!re /)pert Aro!p.* .+/A 2 or .+/A - compression of signals is done before storing or transmitting& decompression is done before retrie%ing or recei%ing these signals. (or .+/A compression algorithms, if a A++ embedded software is r!n, separate DS+"s# are re;!ired to achie%e real,time processing. $n $SS+ that is dedicated to these specific tasks

alone pro%ides a faster sol!tion. he $SS+ is config!red and interfaced with the rest of the embedded system. $ss!me that there is an embedded system that interconnects !sing a specific protocol the system !nits thro!gh a specific b!s architect!re to another system. $lso, ass!me that there is a need for s!itable encryption and decryption. ' he o!tp!t bit stream encryption protects the messages or design from passing to an !nknown e)ternal entity.* (or these tasks, besides embedding the software, it may also be necessary to embed some 4 2S feat!res. 'Section 1.-.1*. If the software alone is !sed for the abo%e tasks, it may take a longer time than a hardwired sol!tion for application,specific processing. $n $SS+ chip pro%ides s!ch a sol!tion. (or e)ample, an $SS+ chip 'from i2Chip "http:DD www.i2Chip.com#* has a C+, 3D+, I+, $4+, and /thernet 1?D1?? .$C ".edia $ccess Control# hardwired logic incl!ded into it. he chip from i2Chip, 831??$, is a !ni;!e hardwired Internet con, necti%ity sol!tion. .!ch needed C+DI+ stack processing software for networking tasks is th!s a%ail, able as a hardwired sol!tion. his gi%es o!tp!t fi%e times faster than a software sol!tion !sing the system=s A++. It is also an 4 2S,less sol!tion. 3sing the same microcontroller in the embedded system to which this $SS+ chip interfaces, /thernet connecti%ity can be added. '(or terms C+, 3D+, I+, $4+, /thernet 1?D1?? and .$C, refer to a s!itable reference book on comp!ter networking. 4efer to Internet and 7eb Technologies by 8a9:amal& Tata #c;raw-,ill& 6((6& to !nderstand the meaning of each bit in these protocols.* $nother $SS+ e)ample is <Serial,to,/thernet Con%erter= "II.51??#. It does real,time data process, ing by a hardware protocol stack. It needs no change in the application software or firmware and pro%ides the economical and smallest 4 2S sol!tion.

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In an embedded system, se%eral processors may be needed to e)ec!te an algorithm fast and within a strict dead line. (or e)ample, in real,time %ideo processing, the n!mber of .$C operations needed per second may be more than is possible from one DS+ !nit. $n embedded system then may ha%e to incorporate two or more processors r!nning in synchroniBation. In a cell,phone, a n!mber of tasks ha%e to be performed: "a# Speech signal,compression and cod, ing. "b# Dialing. "c# .od!lating and ransmitting. "d# Demod!lating and 4ecei%ing. "e# Signal decod, ing and decompression. "f# Peypad interface and display interface handling. "g# Short .essage Ser%, ice "S.S# protocol,based messaging. "h# S.S message display. (or all these tasks, a single processor does not s!ffice. S!itably synchroniBed m!ltiple processors are re;!ired. Consider a %ideo conferencing system. In this system, a ;!arter common intermediate formatL [!arter,CI(#Lis !sed. Image pi)el is R!st 1-- ) 151 as against 020 ) 120 pi)els in a %ideo pict!re on @. /%en then, samples of the image ha%e to be taken at a rate of 1-- ) 151 ) 3? \ 51?32? pi)els per second and ha%e to be processed by compression before transmission on a telecomm!nication or @irt!al +ri%ate Cetwork "@+C#. 'Cote: he n!mber of frames sho!ld be 20 or 3? per second "as per the standard adopted# for real,time displays and in motion pict!res and between 10 and 1? for %ideo conferencing.* $ single DS+,based embedded system does not s!ffice to get real,time images. 8ealtime 3ideo processing and multimedia applications most often need a multiprocessor unit in the

embedded system. '$ .edia processor, described in $ppendi) /, is an alternate sol!tion in place of !se of m!ltiprocessors for real time %ideo processing.* S H . D H

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.ost systems ha%e a power supply of their own. he s!pply has a specific operation range or a range of %oltages. @ario!s !nits in an embedded system operate in one of the following fo!r operation ranges: "i# 0.?@ > ?.20@ "ii# 3.3@ > ?.3@ "iii# 2.? > ?.2@ "i%# 1.0@ > ?.2@ $dditionally, a 12@ > ?.2@ s!pply is needed for a flash "a memory form !sed in systems like latest digital cameras# or /lectrically /rasable and +rogrammable 4ead 2nly memory "//+42.# when present in the microcontroller of an embedded system and for 4S232C serial Interfaces "Section 2#. '9ately, flash memory needed s!pply %oltages are 0@ or less.* @oltage is applied on the chips of an embedded system as follows. he flow of %oltage and the connections depend on the n!mber of s!pply pins pro%ided within the processor pl!s the pins in the associated chips and circ!its. he pins are in pairs, consisting of the s!pply in and the gro!nd line. he following points ha%e to be taken care of while connecting the s!pply rails "lines#: 1. $ processor may ha%e more than two pins of @DD and @SS. his distrib!tes the power in

all the sections and red!ces interference between sections. here sho!ld be a separate radio fre;!ency interference bypassing capacitor as close as possible to each pair of @DD and @SS pins in the system processor as well as in other !nits.

2. S!pply sho!ld separately power the "a# e)ternal ID2 dri%ing ports "b# timers and "c# clock and reset circ!its. Clock and reset circ!its "Sections 1.3.2 and 1.3.3# need to be specially designed to be free from any radio fre;!ency interference. $n ID2 de%ice may dissipate more power than the other internal !nits of the processor. $ timer may dissipate a constant power e%en in 7ait state. 6ence, these three circ!its are powered separately. 3. (rom the s!pply, there sho!ld be separate interconnections for pairs of @DD and @SS

pins, analog gro!nd, analog reference and analog inp!t %oltage lines, the $DC !nit digital gro!nd and other analog parts in the system. $n $DC needs stringent noise,free s!pply inp!ts.

Certain systems do not ha%e a power so!rce of their own: they connect to an e)ternal power supply or are powered by the !se of c!arge pumps. "1# Cetwork Interface Card "CIC# and Araphic $ccelera, tor are e)amples of embedded systems that do not ha%e their own power s!pply and connect to +C power,s!pply lines. "2# $ charge p!mp consists of a diode in the series followed by a charging capacitor. he diode gets forward bias inp!t from an e)ternal signal& for e)ample, from an 4 S signal

in the case of the mo!se !sed with a comp!ter. Charge p!mps bring the power from a non,s!pply line. 'Cinepins C2. port has a signal called 4e;!est o Send "4 S#. It is an acti%e low signal. .ost of the time it is in inacti%e state logic <1= "T0@#. he charge p!mp inside the mo!se !ses it to store the charge when the mo!se is in an idle state& the p!mp dissipates the power when the mo!se is !sed*. $ reg!lator circ!it getting inp!t from this capacitor gi%es the re;!ired %oltage s!pply. $ charge p!mp in a contact, less smart card !ses the radiations from a host machine when inserted into that 'Section 1.1.1*. 9ow %oltage systems are b!ilt !sing 9@C.2S "9ow @oltage C.2S# gates and 9@ 9 "9ow @oltage 9#. 3se of 3.3@, 2.0@, 1.7@ and 1.0 @olt systems and I2 "Inp!t,2!tp!t# Interfaces other than the con%entional 0@ systems res!lts in significantly red!ced power,cons!mption and can be ad%antageo!sly !sed in the following cases: "a# In portable or hand,held de%ices s!ch as a cell!lar phone 'Compared to 0@, a C.2S circ!it power dissipation red!ces by half, T"3.3D0#2, in 3.3@ operation. his also increases the time

inter%als needed for recharging the battery by a factor of two*. "b# In a system with smaller o%erall geometry,

the low %oltage system processors and I2 circ!its generate lesser heat and th!s can be packed into a smaller space. here is generally an in%erse relationship between the propagation delay in the gates and operational %oltage. herefore, the 0@,system processor and !nits are also !sed in most systems. $n embedded system may need to be r!n contin!o!sly, witho!t being switched off& the system design, therefore, is constrained by the need to limit power dissipation while it is r!nning. otal power cons!mption by the system in r!nning, waiting and idle states sho!ld also be limited. he current needed at any instant in the processor of an embedded system depends on the state and mode of the processor. he following are the typical %al!es in si) states of the processor. "i# 0? m$ when only the processor is r!nning:that is, the processor is e)ec!ting instr!ctions. "ii# 50 m$ when the processor pl!s the e)ternal memories and chips are in r!nning: state: that is, fetching and e)ec!tion are both in progress. "iii# 10m$ when only the processor is in stop state: that is, fetching and e)ec!tion ha%e both stopped and the clock has been disabled from all str!ct!ral !nits of the processor. "i%# 10 m$ when the processor pl!s the e)ternal memories and chips are in stop state: that is, fetching and e)ec!tion ha%e both stopped and the clock disabled from all system !nits. "%# 0 m$ when only the processor is in waiting state: that is, fetching and e)ec!tion ha%e both stopped b!t the clock has not been disabled from the str!ct!ral !nits of the processor, s!ch as timers. "%i# 1? m$ when the processor, the e)ternal memories and the chips are in waiting state. 8aiting state now means that fetching and e)ec!tion ha%e both stopped& b!t the clock has not been disabled from the str!ct!ral !nits of the processor and the e)ternal I2 !nits and dynamic 4$.s refreshing also has not stopped. An embedded system !as to perform tasks continuously from power-up and may also be left in power-#. state/ t!erefore power sa)ing during e&ecution is important $ microcontroller !sed in the embedded system m!st pro%ide for e)ec!ting 7ait and Stop instr!ctions and operation in power, down mode. 2ne way to do this is to cle%erly incorporate into the software the 7ait and Stop instr!ctions. $nother is to operate the system at the lowest %oltage le%els in the idle state by selecting power,down mode in that state. ]et another method is to disable !se of certain str!ct!ral !nits of the processorL for e)ample, cachesLwhen not necessary and to keep in disconnected state those str!ct!re !nits that are not needed d!ring a partic!lar software,portion e)ec!tion, for e)ample timers or I2 !nits. In a

C.2S circ!it, power dissipates only at the instance of change in inp!t. herefore, !nnecessary glitches and fre;!ent inp!t changes increase power dissipation. @9SI circ!it designs ha%e a !ni;!e way of a%oiding power dissipation. $ circ!it design is made s!ch that it eliminates all remo%able glitches, thereby eliminating any fre;!ent inp!t changes. !ote 1 he processor goes into a stop state when it recei%es a Stop instr!ction. he stop state also occ!rs in the following conditions: "1# 2n disabling the clock inp!ts to the processor. "2# 2n stopping the e)ternal clock circ!it f!nctions. "3# 2n the processor operating in a!to,sh!tdown mode. 8hen in stop state, the processor disconnects with the b!ses. 'O!ses become in tri,state.* he stop state can change to a r!nning state. he transition to the r!nning state is either beca!se of a !ser interr!pt or beca!se of the periodically occ!rring wake,!p interr!pts. !ote 2 he processor goes into a waiting state either on recei%ing "i# an instr!ction for 7ait, which slows or disables the clock inp!ts to some of the processor !nits incl!ding $93, or "ii# when an e)ternal clock,circ!it becomes non,f!nctional. he timers are still operating in the waiting state. he waiting state changes to the r!nning state when either "i# an interr!pt occ!rs or "ii# a reset signals. !ote 3 +ower dissipation red!ces typically by 2.0 m8 per 1?? k6B red!ced clock rate. So red!ction from 7??? k6B to 1?? k6B red!ces power dissipation by abo!t 2?? m8, which is nearly similar to when the clock is non,f!nctional. '4emember, total power dissipated "energy re;!ired# may not re, d!ce. his is beca!se on red!cing the clock rate the comp!tations will take a longer time at the lower clock rate and the total energy re;!ired e;!als the power dissipation per second m!ltiplied by the time.* he power 20 m8 is typically the resid!al dissipation needed to operate the timers and few other !nits. Oy operating the clock at lower fre;!ency or d!ring the power,down mode of the processor, the ad%antages are as follows: "i# 6eat generation red!ces. "ii# 4adio fre;!ency interference also then red!ces d!e to the red!ced power dissipation within the gates. '4adiated 4( "4adio (re;!ency# power depends on the 4( c!rrent inside a gate, which red!ces d!e to increase in <2C= state resistance between the drain and channel when there is red!ced heat generation.* 9ately, a new technology is the !se of clock manager circ!its in conR!nction with oscillator circ!its. It is !sed in sophisticated embedded systems on chips "SoCs#. wo to si)teen synchrono!s clocks are created by the combination of clock do!blers and clock di%iders "by 2# . (!rther, incoming clock signals at the b!s may be di%ided first and then m!ltiplied before being applied to a fast operation circ!it. his red!ces the power cons!mption between gates. he clock manager circ!it is config!red for the smart deli%ery of the appropriate fre;!ency clock to each section of the circ!it being managed d!ring real,time processing. 'Cote: $ sophisticated technologyL phased delay loc.ed loops<has to be !sed. 8hen !sing the common logic gates of co!nters, there are contin!o!sly %arying delays at the gates "say, for e)ample, 1? ns pl!s min!s 2 ns#. he synchrono!s clocks cannot be designed by !sing the co!nters alone.* H ? 1 H # I 2 " ?> 1 ? 1 " H

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After t!e power supply t!e clock is t!e ne&t important unit of a system. $ processor needs a cloc" oscillator circ!it. he clock controls the %ario!s clocking re;!irements of the C+3, of the system timers and the C+3 machine cycles. he machine cycles are for "i# fetching the codes and data from memory and then decoding and e)ec!ting at the processor, and "ii# transferring the res!lts to memory. he cloc. controls the time for e)ec!ting an instr!ction. he clock circ!it !ses either a crystal "e)ternal to the processor# or a ceramic resonator "internally associated with the processor# or an e)ternal oscillator IC attached to the processor. "a# he crystal resonator gi%es the highest stability in fre;!ency with temperat!re and drift in the circ!it. he crystal in association with an appropriate resistance in parallel and a pair of series capacitance at both pins resonates at the fre;!ency, which is either do!ble or single times the crystal,fre;!ency. (!rther, the crystal is kept as near as feasible to two pins of the processor. "b# he internal ceramic resonator, if a%ailable in a processor, sa%es the !se of the e)ternal crystal and gi%es a reasonable tho!gh not %ery highly stable fre;!ency. '$ typical drift of the ceramic resonator is abo!t ten min!tes per month compared to the typical drift of 1 or 0 min!tes per month of a crystal*. "c# he e)ternal IC,based clock oscillator has a significantly higher power dissipation compared to the internal processor,resonator. 6owe%er, it pro%ides a higher dri%ing capa, bility, which might be needed when the %ario!s circ!its of embedded system are conc!rrently dri%en. (or e)ample, a m!ltiprocessor system needs the clock circ!it, which sho!ld gi%e a high dri%ing capa, bility and enables control of all the processors conc!rrently. K D 7 H

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$ timer circ!it s!itably config!red is the system-clock, also called real,time clock "4 C#. $n 4 C is !sed by the sched!lers and for real,time programming. $n 4 C is designed as follows: $ss!me a processor generates a clock o!tp!t e%ery ?.0 ms. 8hen a system timer is config!red by a software instr!ction to iss!e timeo!t after 2?? inp!ts from the processor clock o!tp!ts, then there are 1???? interr!pts "ticks# each second. he 4 C ticking rate is then 1? k6B and it interr!pts e%ery 1?? ms. he 4 C is also !sed to obtain software,controlled delays and time,o!ts. .ore than one timer !sing the system clock "4 C# may be needed for the %ario!s timing and co!nting needs in a system. 4efer to Section 3.2 for a description of timers and co!nters.

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8eset means that the processor starts the processing of instr!ctions from a starting address. hat address is one that is set by defa!lt in the processor program co!nter "or instr!ction pointer and code segment registers in )71 processors# on a power,!p. (rom that address in memory, the fetching of program,instr!ctions starts following the reset of the processor. 'In certain processors, for e)ample, 176C11 and 6C12, there are two start,!p addresses. 2ne is as per power,!p reset %ector and other is as per reset %ector after the 8eset instr!ction or after a time,o!t "for e)ample from a watchdog timer#*. he reset circ!it acti%ates for a fi)ed period "a few clock cycles# and then deacti%ates. he proces, sor circ!it keeps the reset pin acti%e and then deacti%ates to let the program proceed from a defa!lt beginning address. he reset pin or the internal reset signal, if connected to the other !nits "for e)ample, ID2 interface or Serial Interface# in the system, is acti%ated again by the processor& it be, comes an o!tgoing pin to enforce reset state in other sister !nits of the system. 2n deacti%ation of the reset that s!cceeds the processor acti%ation, a program e)ec!tes from start,!p address. 4eset can be acti%ated by one of the following: 1. $n e)ternal reset circ!it that acti%ates on the power,!p, on switching,on reset of the system or on detection of a low %oltage "for e)ample ^ -.0@ when what is re;!ired is 0@ on the system s!pply rails#. his circ!it o!tp!t connects to a pin called the reset pin of the processor. his circ!it may be a simple 4C circ!it, an e)ternal IC circ!it or a c!stom,b!ilt IC. he e)amples of the ICs are .$Z 131- and .otorola .C 3-?1-. 2. Oy "a# software instr!ction or "b# time,o!t by a programmed timer known as watchdog timer "or on an internal signal called C2+ in 176C11 and 176C12 families# or "c# a clock monitor detecting a slowdown below certain threshold fre;!encies d!e to a fa!lt. he watchdog timer is a timing de%ice that resets the system after a predefined timeo!t. his time is !s!ally config!red and the watchdog timer is acti%ated within the first few clock cycles after power,!p. It has a n!mber of applications. In many embedded systems reset by a watchdog timer is %ery essential beca!se it helps in resc!ing the system if a fa!lt de%elops and the program gets st!ck. 2n restart, the system can f!nction normally. .ost microcontrollers ha%e on,chip watchdog timers. Consider a system controlling the temperat!re. $ss!me that when the program starts e)ec!ting, the sensor inp!ts work all right. 6owe%er, before the desired temperat!re is achie%ed, the sensor circ!it de%elops some fa!lt. he controller will contin!e deli%ering the c!rrent nonstop if the system is not reset. Consider another e)ample of a system for controlling a robot. $ss!me that the interfacing motor control circ!it in the robot arm de%elops a fa!lt d!ring the r!n. In s!ch cases, the robot arm may contin!e to mo%e !nless there is a watchdog timer control. 2therwise, the robot will break its own armH H " . H H D H H

In a system, there are %ario!s types of memories. (ig!re 1.- shows a chart for the %ario!s forms of memories that are present in systems. hese are as follows: "i# Internal 4$. of 201 or 012 bytes in a microcontroller for registers, temporary data and stack' "ii# Internal 42.D+42.D/+42. for abo!t - kO to 11 kO of program "in the case of microcontrollers#. "iii# /)ternal 4$. for the temporary data and stack "in most systems#. "i%# Internal caches "in the case of certain microprocessors#. "%# //+42. or flash "in many systems sa%ing the res!lts of processing in non%olatile memory: for e)ample, system stat!s periodically and digital,camera images, songs, or speeches after a s!itable format compression#. "%i# /)ternal 42. or +42. for embedding software "in almost all non, microcontroller,based systems#. "%ii# 4$. .emory b!ffers at the ports. "%iii# Caches "in s!perscaler microprocessors#. '4efer to Sections 2.1 and 2.3 for f!rther details of these.*

able 1.- gi%es the f!nctions assigned in the embedded systems to the memories. 42. or +42. or /+42. embeds the embedded software specific to the system.
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Storing $pplication programs from where the processor fetches the instr!ction codes. Storing codes for system booting, initialiBing, Initial inp!t data and Strings. Codes for 4 2S. +ointers "addresses# of %ario!s ser%ice ro!tines. Storing the %ariables d!ring program r!n and storing the stack. Storing inp!t or o!tp!t b!ffers, for e)ample, for speech or image. Storing non,%olatile res!lts of processing. Storing copies of instr!ctions and data in ad%ance from e)ternal memories and storing temporarily the res!lts d!ring fast processing.

4$. "Internal and /)ternal# and 4$. for b!ffer //+42. or (lash Caches

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he system gets inp!ts from physical de%ices "s!ch as, for e)ample, the key,b!ttons, sensors and transd!cer circ!its# thro!gh the inp!t ports. $ controller circ!it in a system gets the inp!ts from the sensor and transd!cer circ!its. $ recei%er of signals or a network card gets the inp!t from a comm!, nication system. '$ comm!nication system co!ld be a fa) or modem, a broadcasting ser%ice*. Signals from a network are also recei%ed at the ports. Consider the system in an $!tomatic Chocolate @ending .achine. It gets inp!ts from a port that collects the coins that a child inserts. +res!me that only a child wo!ld !se this wonder machineH Consider the system in a mobile phone. he !ser inp!ts the mobile n!mber thro!gh the b!ttons, directly or indirectly "thro!gh recall of the n!mber from its memory#. $ panel of b!ttons connects to the system thro!gh the inp!t port or ports. +rocessor identifies each inp!t port by its memory b!ffer address"es#, called port address"es#. W!st as a memory location holding a byte or word is identified by an address, each inp!t port is also identified by the address. T!e system gets t!e inputs by t!e read operations at t!e port addresses. T!e system !as output ports t!roug! w!ic! it sends output bytes to t!e real world' $n o!tp!t may be to an 9/D "9ight /mitting diode# or 9CD "9i;!id Crystal Display# panel. (or e)ample, a calc!lator or mobile phone system sends the o!tp!t,n!mbers or an S.S message to the 9CD display. $ system may send o!tp!t to a printer. $n o!tp!t may be to a comm!nication system or network. $ control system sends the o!tp!ts to alarms, act!ators, f!rnaces or boilers. $ robot is sent o!tp!t for its %ario!s motors. /ach o!tp!t port is identified by its memory,b!ffer address"es# "called port address#. he system sends t!e output by a write operation to t!e port address' here are also general,p!rpose ports for both the inp!t and o!tp!t "ID2# operations. (or e)ample, a mobile phone system sends o!tp!t as well as gets inp!t thro!gh a wireless comm!nication channel. /ach ID2 port is also identified by an address to which the read and write operations both take place. 4efer to Section 3.1 for the details regarding ports. here are two types of "0# ports1 Parallel and Serial. (rom a serial port, a system gets a serial stream of bits at an inp!t or sends a stream at an o!tp!t. (or e)ample, thro!gh a serial port, the system gets and sends the signals as the bits thro!gh a modem. $ serial port also facilitates long distance comm!nication and interconnections. $ serial port may be a Serial $ART port a Serial Sync!ronous port or some other Serial "nterfacing port. '3$4 stands for 3ni%ersal $synchrono!s 4ecei%er and ransmitter*. $ system port may get inp!ts from m!ltiple channels or may ha%e to send o!tp!t to m!ltiple channels. $ demultiple&er takes the inp!ts from %ario!s channels and transfers the inp!t from a select channel to the system. $ multiple&er takes the o!tp!t from the system and sends it to another system. $ system might ha%e to be connected to a n!mber of other de%ices and systems. (or networking the systems, there are different types of b!ses: for e)ample, I2C, C$C, 3SO, IS$, /IS$ and

+CI. '4efer to Sections 3.3, 3.- and $ppendi) ( for b!ses in detail.*
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$ system may possess a n!mber of de%ices and the system processor has to control and handle the re;!irements of each de%ice by r!nning an appropriate Interr!pt Ser%ice 4o!tine "IS4# for each. An interrupts-!andling mec!anism must e&ist in eac! system to !andle interrupts from )arious processes in t!e system1 for e)ample, to transfer data from a keyboard or a printer. '4efer to Chapter - for a detailed description of the interr!pts and their control "handling# mechanism in a system*. Important points regarding the interr!pts and their handling by programming are as follows: 1. here can be a n!mber of interr!pt so!rces and gro!ps of interr!pt so!rces in a processor. '4efer to Section -.0.* $n interr!pt may be a hardware signal that indicates the occ!rrence of an e%ent. '(or e)ample, a real,time clock contin!o!sly !pdates a %al!e at a specified memory address& the transition of that %al!e is an e%ent that ca!ses an interr!pt.* $n interr!pt may also occ!r thro!gh timers, thro!gh an interr!pting instr!ction of the processor program or thro!gh an error d!ring processing. he error may arise d!e to an illegal op,code fetch, a di%ision by Bero res!lt or an o%erflow or !nderflow d!ring an $93 operation. $n interr!pt can also arise thro!gh a software timer. $ software interr!pt may arise in an e)ceptional condition that may ha%e de%eloped while r!nning a program. 2. he system may prioritiBe the so!rces and ser%ice them accordingly 'Section -.1.0*. 3. Certain so!rces are not maskable and cannot be disabled. Some are defined to the highest priority d!ring processing. -. he processor=s c!rrent program has to di%ert to a ser%ice ro!tine to complete that task on the occ!rrence of the interr!pt. (or e)ample, if a key is pressed, then an IS4 reads the key and stores the key %al!e in the processor memory address. If a se;!ence of keys is pressed, for instance in a mobile phone, then an IS4 reads the keys and also calls a task to dial the mobile n!mber. 0. here is a programmable !nit on,chip for the interr!pt handling mechanism in a microcontroller. 1. he application program or sched!ler is e)pected to sched!le and control the r!nning of ro!tines for the interr!pts in a partic!lar application. he sched!ler always gi%es priority to the IS4s o%er the tasks of an application. " K " H N

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S!ppose a system needs to gi%e an analog o!tp!t of a control circ!it for a!tomation. he analog o!tp!t may be to a power system for a d.c. motor or f!rnace. $ Pulse 7idth #odulator "+8.# !nit in the microcontroller operates as follows: +!lse width is made proportional to the analog,o!tp!t needed. +8. inp!ts are from ???????? to 11111111 for an 7,bit D$C operation. he +8. !nit o!tp!ts to an e)ternal integrator and then pro%ides the desired analog o!tp!t. S!ppose an integrator circ!it "e)ternal to the microcontroller# gi%es an o!tp!t of 1.?2- @olt when the p!lse width is 0?M of the total p!lse time period, and 2.?-5@ when the width is 1??M. 8hen the width is made 20M by red!cing by half the %al!e in +8. o!tp!t control,register, the integrator o!tp!t will become ?.012 @olt.

Cow ass!me that the integrator operates with a d!al "pl!s,min!s# s!pply. $lso ass!me that when an integrator circ!it gi%es an o!tp!t of 1.?23 @olt, the p!lse width is 1??M of total p!lse time period and _1.?2- @olt when the width is ?M. 8hen the width is made 20M by red!cing by half the %al!e in an o!tp!t control register, the integrator o!tp!t will be ?.012 @olt& at 0?M the o!tp!t will be ?.? @olt. (rom this information, finding the form!lae to obtain con%erted bits for a gi%en +8. register bits ranging from ???????? to 11111111 in both the sit!ations is left as an e)ercise for the reader. he $DC in the system microcontroller can be !sed in many applications s!ch as Data $c;!isition System "D$S#, analog control system and %oice digitiBing system. S!ppose a system needs to read an analog inp!t from a sensor or transd!cer circ!it. If con%erted to bits by the $DC !nit in the system, then these bits, after processing, can also gi%e an o!tp!t. his pro%ides a control for a!tomation by a combined !se of $DC and D$C feat!res. he con%erted bits can be gi%en to the port meant for digital display. he bits may be transferred to a memory address, a serial port or a parallel port. $ processor may process the con%erted bits and generate a +!lse Code .od!lated "+C.# o!tp!t. +C. signals are !sed digitiBing the %oice in the digital format*. Important points abo!t the $DC are as follows: 1. /ither a single or d!al analog reference %oltage so!rce is re;!ired in the $DC. It sets either the analog inp!t=s !pper limit only or the lower and !pper limits both. (or a single reference so!rce, the lower limit is set to ?@ "gro!nd potential#. 8hen the analog inp!t e;!als the lower limit the $DC generates all bits as ?s, and when it e;!als the !pper limit it generates all bits as 1s. '$s an e)ample, s!ppose in an $DC the !pper limit or reference %oltage is set as 2.200 @olt. 9et the lower limit reference @oltage be ?.200@. Difference in the limits is 2 @olt. herefore, the resol!tion will be "2D201# @olt. If the 7,bit $DC analog,inp!t is ?.200@, the con%erted 7 bits will be ????????. 8hen the inp!t is "?.200@ > 1.???@# \ 1.200@, the bits will be 1???????. 8hen the analog inp!t is "?.200@ > ?.0?@#, the con%erted bits will be ?1??????. '(rom this information, finding a form!la to obtain con%erted bits for a gi%en analog inp!t \ % @olt is left as an e)ercise for the reader*. 2. $n $DC may be of eight, ten, twel%e or si)teen bits depending !pon the resol!tion needed for con%ersion. 3. he start of the con%ersion signal "S C# signal or inp!t initiates the con%ersion to 7 bits. In a system, an instr!ction or a timer signals the S C. -. here is an end of con%ersion "/2C# signal. In a system, a flag in a register is set to indicate the end of con%ersion and generate an interr!pt. 0. here is a con%ersion time limit in which the con%ersion is definite. 1. $ Sample and 6old "SD6# !nit is !sed to sample the inp!t for a fi)ed time and hold till con%ersion is o%er. $n $DC !nit in the embedded system microcontroller may ha%e m!lti,channels. It can then take the inp!ts in s!ccession from the %ario!s pins interconnected to different analog so!rces. Q Q # Q# K H Q# " K 7 H Q# H K # Q# >S

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A system re2uires an interfacing circuit and software to display t!e status or message for a line for multi-line displays or flas!ing displays' $n 9CD screen may show !p a m!lti,line display of charac, ters or also show a small graph or icon "called pictogram#. $ recent inno%ation in the mobile phone system t!rns the screen bl!e to indicate an incoming call. hird generation system phones ha%e both image and graphic displays. $n 9CD needs little power. It is powered by a s!pply or battery "a solar panel in the calc!lator#. 9CD is a diode that absorbs or emits light on application of 3 @ to - @ and 0? or 1? 6B %oltage,p!lses with c!rrents less than T0? m$. he p!lses are applied with the same polarity on crystal front and back plane for no light, or with opposite polarity for light. 6ere polarity at an instance means logic <1= or <?=*. $n 9SI "9ower Scale Integrated Circ!it# display,controller is often !sed in the case of matri) displays. (or indicating 2C stat!s of the system there may be an 9/D, which glows when it is 2C. $ flashing 9/D may indicate that a specific task is !nder completion or is r!nning. It may indicate a wait stat!s for a message. he 9/D is a diode that emits yellow, green, red "or infrared light in a remote controller#, on application of a forward %oltage of 1.1 to 2 @. $n 9/D needs c!rrent !p to 12 m$ abo%e 0 m$ "less in flashing display mode# and is m!ch brighter than the 9CD. herefore, for flashing display and for display limited to few digits, 9/Ds are !sed in a system. . ,^Q H K ,#Q " ,^Q H ,#Q

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T!e keypad or keyboard is an important de)ice for getting user inputs' T!e system must pro)ide t!e necessary interfacing and key-debouncing circuit as well as t!e software for t!e system to recei)e input from a set of keys or from a keyboard or keypad' $ keypad has !p to a ma)im!m of 32 keys. $ keyboard may ha%e 1?- or more keys. he keypad or keyboard may interface serially or as parallel to the processor directly thro!gh a parallel or serial port or thro!gh a controller. H K H .

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(or !ser connecti%ity thro!gh the telephone line, wireless or a network, a system pro%ides the neces, sary interfacing circ!it. It also pro%ides the software for p!lse dialing thro!gh the telephone line, for modem interconnection for fa), for Internet packets ro!ting, and for transmitting and connecting a 8$A "8ireless Aateway# or cell!lar system. $ transcei3er is a circuit that can transmit as well as recei3e byte streams.

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$ system may need linking to another instr!ment or system. he I/// -77 A+IO "Aeneral +!rpose Interface O!s# link is a standard b!s originally de%eloped by 6+ '6ewlett +ackard* that links the meas!ring and instr!mentation systems. he embedded system !sed in the instr!mentation systems !ses this interfacing standard.

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he b!ses and !nits in the embedded system hardware need to be linked and interfaced. 2ne way to do this is to incorporate a glue logic circuit. 'Instead of !sing indi%id!al gates, b!ffers and decoders, we !se the gl!e logic circ!it.* $ gl!e circ!it is a circ!it that is placed "gl!ed# for all the b!s logic actions between circ!its and between all chips and main chips "processors and memories#. he gl!e logic circ!it of an embedded system may be a circ!it for interconnecting the processor to e)ternal memo, ries so that the appropriate chip,select signals, according to the system memory, map each of the memory chips 'Section 2.0*. he gl!e logic circ!it also incl!des a circ!it to interconnect the parallel and serial ports to the peripherals. '4efer to Chapter 3 for more information on ports.* he gl!e circ!it simplifies the o%erall embedded system circ!it greatly. $n e)ample of the !se of the gl!e circ!it is to connect the processor, memories and the ports interfacing the 9CD display matri) and the keypad. +rogramming and config!ring one of the followings gi%es a gl!e circ!it. "i# +$9 "+rogrammable $rray 9ogic#. "ii# A$9 "Aeneric $rray 9ogic#. "iii# +9D "+rogrammable 9ogic De%ice#. "i%# C+9D "Combined +9D#. "%# (+A$. hese de%ices are config!rable and programmable by a system called de)ice programmer. +$9 has the $CD_24 logic arrays. +$9 implements only the combinational logic circ!it. A$9 is another array logic, an ad%anced %ersion of +$9, which pro%ides se;!ential circ!it implementation. It th!s pro%ides the latches, co!nters and register circ!its also. +9D is another logic de%ice that is programmable. $ 42. is also a +9D. C+9D is a combination circ!it integrated with a +9D. It is a logic de%ice for implementing mi)ed f!nctions, analog and digital. $ C+9D also helps in the control f!nctions and designing a +9C "+rogrammable 9ogic Controller#. (+A$ has a macro cell, which is a combination of gates and flip,flops. $n array has n!mber of macro cells. he links within the array or in between macro cells are f!sable by a de%ice programmer in these de%ices. ,K H , # ,Q -

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able 1.0 lists the hardware !nits that m!st be present in the embedded systems. Si) e)amples ha%e been chosen to represent systems of %arying sophistication. hese are:

Y $!tomatic chocolate %ending machine "Case st!dy for its programming has been gi%en in Section 11.1#, Y Data ac;!isition System, Y 4obot, Y .obile +hone, Y $dapti%e Cr!ise Control "$CC# system with car string stability "Case st!dy for its programming has been gi%en in Section 11.3# and Y @oice,+rocessor and Storage System "inp!t, compression, store, decompression, recording and replay#. 4emember, 4 Cs, imers, Idle,mode, +ower,down mode, 8atchdog timer and Serial I2 +ort, 3$4 port and gl!e,logic circ!it are needed practically in all the applications and ha%e, therefore, not listed in the able. he %al!es gi%en here refer to a typical system only.
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.od!lation Demod!lation Digital Signal +rocessing Instr!ctions

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need of 4$. is d!e to b!ffer memory 4$. for %oice inp!ts and o!tp!ts being processed O!ffer,memory for the speech signals > (or storing the %oice

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T!e software is the most important aspect, the brain of the embedded system.

JI J : > .I JI K 7J K J " $n embedded system processor and the system need software that is specific to a gi%en application of that system. he processor of the system processes the instr!ction codes and data. In the final stage, these are placed in the memory "42.# for all the tasks that ha%e to be e)ec!ted. he final stage software is also called 42. image. 8hyF W!st as an image is a !ni;!e se;!ence and arrangement of pi)els, embedded software is also a !ni;!e placement and arrangement of bytes for instr!ctions and data. /ach code or dat!m is a%ailable only in bits and byte"s# format. he system re;!ires bytes at each 42.,address, according to the tasks being e)ec!ted. $ machine implement-able software file is therefore li.e a table of address and bytes at each address of the system memory" he table has to be readied as a 42. image for the targeted hardware. (ig!re 1.0 shows the 42. image in a system memory. he image consists of the boot !p program, stack "s# address pointer"s#, program co!nter address pointer"s#, application tasks, IS4s "Section -.12#, 4 2S, inp!t data, and %ector addresses. '4efer to Section 2.0 for the details.*

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D!ring coding in this format, the programmer defines the addresses and the corresponding bytes or bits at each address. In config!ring some specific physical de%ice or s!bsystem, machine code,based coding is !sed. (or e)ample, in a transcei%er, placing certain machine code and bits can config!re it to transmit at specific .bps or Abps, !sing a specific b!s protocol and networking protocol. $nother e)ample is !sing certain codes for config!ring a control register with the processor. D!ring a specific code,section processing, the register can be config!red to enable or disable !se of its internal cache. 6owe%er, coding in mac!ine implement-able codes is done only in specific sit!ations: it is time consuming because t!e programmer must first understand the processor instr!ctions set and then memoriBe the instr!ctions and their machine codes.

K 7J " . K I \J J 8hen a programmer !nderstands the processor and its instr!ction set thoro!ghly, a program or a small specific part can be coded in the assembly language. $n e)emplary assembly lang!age program in $4. processor instr!ction set will be shown in /)ample gi%en in Section $.2. Coding in assembly lang!age is easy to learn for a designer who has gone thro!gh a microprocessor or microcontroller co!rse. Coding is e)tremely !sef!l for config!ring physical de%ices like ports, a line,display interface, $DC and D$C and reading into or transmitting from a b!ffer. hese codes can also be de%ice dri%er codes. 'Section -.1*. hey are !sef!l to r!n the processor or de%ice specific feat!res and pro%ide an optimal coding sol!tion. 0ac. of .nowledge of writing de3ice dri3er codes or codes that utilize the processor-specific features-in3o.ing codes in an embedded system design team can cost a lot" /endors may not only charge for the $PI but also charge intellectual property fees for each system shipped out of the company. o do all the coding in assembly language may, howe%er, be %ery time cons!ming. (!ll coding in assembly may be done only for a few simple, small,scale systems, s!ch as toys, a!tomatic chocolate %ending machine, robot or data ac;!isition system. (ig!re 1.1 shows the process of con%erting an assembly language program into the machine imple, ment,able software file and then finally obtaining a 42. image file. 1. $n assembler translates the assembly software into the machine codes !sing a step called assembling. 2. In the ne)t step, called lin.ing & a linker links these codes with the other re;!ired assembled codes. 9inking is necessary beca!se of the n!mber of codes to be linked for the final binary file. (or e)ample, there are the standard codes to program a delay task for which there is a reference in the assembly lang!age program. he codes for the delay m!st link with the assembled codes. he delay code is se;!ential from a certain beginning address. he assembly software code is also se;!ential from a certain beginning address. Ooth the codes ha%e to at the distinct addresses as well as a%ailable addresses in the system. 9inker links these. he linked file in binary for run

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on a comp!ter is commonly known as e)ec!table file or simply <.e)e= file. $fter linking, there has to be re,allocation of the se;!ences of placing the codes before act!ally placement of the codes in the memory. 3. In the ne)t step, the loader program performs the task of reallocating the codes after finding the physical 4$. addresses a%ailable at a gi%en instant. he loader is a part of the operating system and places codes into the memory after reading the <.e)e= file. his step is necessary beca!se the a%ailable memory addresses may not start from ?)????, and binary codes ha%e to be loaded at the different addresses d!ring the r!n. he loader finds the appropriate start address. In a comp!ter, the loader is !sed and it loads into a section of 4$. the program that is ready to r!n. -. he final step of the system design process is locating the codes as a 42. image and permanently placing them at the act!ally a%ailable addresses in the 42.. In embedded systems, there is no separate program to keep track of the a%ailable addresses at different times d!ring the r!nning, as in a comp!ter. he designer has to define the a%ailable addresses to load and create files for permanently locating the codes. $ program called locator reallocates the linked file and creates a file for permanent location of codes in a standard format. his format may be Intel 6e) file format or .otorola S,record format. '4efer to $ppendi) A for details.* . H . JI " H

0. 9astly, either "i# a laboratory system, called de)ice programmer takes as inp!t the 42. image file and finally burns the image into the +42. or /+42. or "ii# at a fo!ndry, a mask is created for the 42. of the embedded system from the image file. ' he process of placing the codes in

+42. or /+42. is also called b!rning.* #he mask created from the image gi%es the 42. in IC chip form. H K ? ? H NIS # H 1 1K ?, 1 ?, 1H . NIS K D H NIS ^ NISH

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o do all the coding in assembly language may be %ery time cons!ming in most cases. Software is therefore de%eloped in a high,le%el lang!age, <C= or <C>>= or <Wa%a=. .ost of the times, <C= is the preferred lang!age. '4efer to Sections 0.1, 0.7 and 0.: to !nderstand the ad%antages a%ailable in each and to Section 0.11 for the !se of <C= so!rce,code programming tools.* (or coding, there is little need to !nderstand assembly lang!age instr!ctions and the programmer does not ha%e to know the machine code for any instr!ction at all. he programmer needs to !nderstand only the hardware organiBation. $s an e)ample, consider the following problem: $dd 125, 2: and -? and print the s;!are root. $n e)emplary C lang!age program for all the processors is as follows: "i# = include >stdio"h? "ii# = include >math"h? "iii# 3oid main (3oid4 @ "i%# int i*& i6& i5& aA float res!lt& "%# i1 \ 125& i2 \ 2:& i3 \ -?& a B i* C i6 C i5A result B s2rt (a4A "%i# printf (result4AD It is e%ident, then, that coding for s;!are,root will need many lines of code and can be done only by an e)pert assembly lang!age programmer. o write the program in a high le%el lang!age is %ery simple compared to writing it in the assembly lang!age. <C= programs ha%e a feat!re that adds the assembly instr!ctions when !sing certain processor,specific feat!res and coding for the specific section, for e)ample, port de%ice dri%er. (ig!re 1.5 shows the different programming layers in a typical embedded

<C= software. '4efer to appropriate sections in Chapters 3 to 0.* hese layers are as follows. "i# +rocessor Commands. "ii# .ain (!nction. "iii# Interr!pt Ser%ice 4o!tine. "i%# .!ltiple tasks, say, 1 to C. "%# Pernel and Sched!ler. "%i# Standard library f!nctions, protocol f!nctions and stack allocation f!nctions. (ig!re 1.7 shows the process of con%erting a C program into the 42. image file. $ compiler generates the obRect codes. he compiler assembles the codes according to the processor instr!ction set and other specifications. he <C= compiler for embedded systems m!st, as a final step of compi, lation, !se a code-optimizer . It optimiBes the codes before linking. $fter compilation, the lin.er links the obRect codes with other needed codes. (or e)ample, the linker incl!des the codes for the f!nctions, printf and s;rt codes. Codes for de%ice management and dri%er "de%ice control codes# also link at this stage: for e)ample, printer de%ice management and dri%er codes. $fter linking, the other steps for creating a file for 42. image are the same as shown earlier in (ig!re 1.1.

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In an embedded system, there are a n!mber of physical de3ices. /)emplary physical de%ices are keyboard, display, disk, parallel port and network,card.

$n inno3ati3e concept is use of 3irtual de3ices during programming" $ 3irt!al de%ice e)ample is a file "for reading and writing the stream of bytes or words# or a pipe "for b!ffering a stream of bytes#. he term %irt!al de%ice follows from the analogy that R!st as a keyboard gi%es an inp!t to the processor on a read, a file also gi%es an inp!t to the processor. he processor gi%es an o!tp!t to a printer on a write. Similarly, the processor writes an o!tp!t to the file. .ost often, an embedded system is de, signed to perform m!ltiple f!nctions and has to control m!ltiple physical and %irt!al de%ices. $ de$ice for the p!rpose of control, handling, reading and writing actions can be taken as consist, ing of three components. "i# Control 4egister or 8ord _ It stores the bits that, on setting or resetting by a de%ice dri%er, control the de%ice actions. "ii# Stat!s 4egister or 8ord _ It pro%ides the flags "bits# to show the de%ice stat!s. "iii# De%ice .echanism that controls the de%ice actions. here may be inp!t data b!ffers and o!tp!t data b!ffers at a de%ice. De%ice action may be to get inp!t into or send o!tp!t from the b!ffer. "The control registers& input data buffers& output data buffers and status registers form part of the de3ice hardware"# $ de$ice dri$er is software for controlling, recei%ing and sending a byte or a stream of bytes from or to a de%ice. In case of physical de%ices, a dri%er !ses the hardware stat!s flags and control register bits that are in set and reset states. In case of %irt!al de%ices also, a dri%er !ses the stat!s and control words and the bits that e)ist in set and reset states. ri3er controls three f!nctions "i# InitialiBing that is acti%ated by placing appropriate bits at the control register or word. "ii# Calling an IS4 on interr!pt or on setting a stat!s flag in the stat!s register and r!n "dri%e# the IS4 "also called Interr!pt 6andler 4o!tine#. "iii# 4esetting the stat!s flag after interr!pt ser%ice. $ dri%er may be designed for asynchrono!s operations "m!ltiple times !se by tasks one after another# or synchrono!s operations "conc!rrent !se by the tasks#. his is beca!se a de%ice may get acti%ated when an interr!pt arises and the de%ice dri%er ro!tine ser%ices that. 3sing 2perating System "2S# f!nctions, a de%ice dri%er coding can be made s!ch that the !nderly, ing hardware is hidden as m!ch as possible. $n $+I then defines the hardware separately. his makes the dri%er !sable when the de%ice hardware changes in a system. $ de%ice dri%er accesses a parallel port or serial port, keyboard, mo!se, disk, network, display, file, pipe and socket at specific addresses. $n 2S may also pro%ide e3ice dri3er codes for the system, port addresses and for the access mechanism "read, sa%e, write# for the de%ice hardware. e3ice #anagement software mod!les pro%ide codes for detecting the presence of de%ices, for initialiBing these and for testing the de%ices that are present. he mod!les may also incl!de software for allocating and registering port "in fact, it may be a register or memory# addresses for the %ario!s de%ices at distinctly different addresses, incl!ding codes for detecting any collision between these, if any. It ens!res that any de%ice accesses to one task at any gi%en instant. It takes into acco!nt that %irt!al de%ices may ha%e addresses that can be relocated by a locator "for +42.#. ' he act!al physi, cal or hardware de%ices ha%e predefined fi)ed addresses "the addresses are not relocated by the locator#*. $n 2S also pro%ides and e)ec!tes mod!les for managing de%ices that associate with an embedded system. he !nderlying principle is that at an instant, only one physical de%ice sho!ld get access to or from one task only. he 2S also pro%ides and manages the %irt!al de%ices like pipes and sockets 'Section 7.3*.

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.ost often, an embedded system is designed to perform sched!ling of m!ltiple f!nctions while con, trolling m!ltiple de%ices. $n embedded system program is therefore designed as a m!ltitasking system program. '4efer to Section 7.1 for definitions of the tas.s "f!nctions# and tas.-states.* In a m!ltitasking 2S, each process (tas.4 has a distinct memory allocation of its own and a tas. has one or more functions or procedures for a specific 9ob" $ tas. may share the memory (data4 with other tas.s" $ processor may process multiple tas.s separately or concurrently. he 2S software incl!des sched!ling feat!res for the processes "tasks, IS4s and De%ice Dri%ers# $n ES or 8TES has a .ernel. '4efer to Section :.2 for !nderstanding kernel f!nctions in detail.* The .ernelFs important function is to schedule the transition of a tas. from a ready state to a running state" It also sched!les the transition of a task from a blocked state to the r!nning state. he kernel may block a task to let a higher priority task be in r!nning state. 'It is called preempti%e sched!ling*. he .ernel coordinates the !se of the processor for the m!ltiple tasks that are in ready state at any instant, s!ch that only one task among many is in the r!nning state. his is so beca!se there is only one processor in the system. he kernel sched!les and dispatches a task to a different state than the present. '(or m!ltiprocessor systems, sched!ling and synchroniBation of %ario!s processors are also necessary*. he kernel controls the inter process "task# messaging and sharing of %ariables, ;!e!es and pipes. 4 2S f!nctions can th!s be highly comple). Chapters : to 11 will describe the 4 2S f!nctions in an embedded system. In an embedded system, 4 2S has to be scalable. Scaleable ES is one in which memory is optimiBed by ha%ing only that part of feat!res that are needed associate with the final system software. here are a n!mber of pop!lar and readily a%ailable 4 2Ss. Chapters : and 1? will describe these. Case st!dies employing these 4 2Ss will be taken !p in Chapter 11. ^ NH S K H K N.I H -

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(or writing C codes or assembly mnemonics !sing the keyboard of the +C for entering the program. $llows the entry, addition, deletion, insert, appending pre%io!sly written lines or files, merging record and files at the specific positions. Creates a so!rce file that stores the edited file. It also has an appropriate name 'pro%ided by the programmer*. (or e)pression,by,e)pression "line,by,line# translation to the machine e)ec!table 3ses the complete sets of the codes. It may also incl!de the codes, f!nctions and e)pressions from the library ro!tines. It creates a file called obRect file. (or translating the assembly mnemonics into binary opcodes "instr!ctions#, i.e., into an e)ec!table file called a binary file. It also creates a list file that can be printed. he list file has address, so!rce code "assembly lang!age mnemonic# and he)adecimal obRect codes. he file has addresses that adR!st d!ring the act!al r!n of the assembly lang!age program. (or con%erting obRect codes or e)ec!table codes for a processor to other codes for another processor and %ice %ersa. he cross,assembler assembles the assembly codes of target processor as the assembly codes of the processor of the +C !sed in the system de%elopment. 9ater, it pro%ides the obRect codes for the target processor. hese codes will be the ones act!ally needed in the finally de%eloped system. o sim!late all f!nctions of an embedded system circ!it incl!ding additional memory and peripherals. It is independent of a partic!lar target system. It also sim!lates the processes that will e)ec!te when the codes e)ec!te on the targeted partic!lar processor. (or so!rce code comprehension, na%igation and browsing, editing, deb!gging,

Interpreter codes. Compiler $ssembler

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/ngineering Software "disabling and enabling the C>> feat!res# and 4efer Chapters : and 1?. (or dynamically tracking the changes in any program %ariable. It tracks the changes in parameter. It demonstrates the se;!ences of m!ltiple processes "tasks, threads, ser%ice ro!tines# that e)ec!te. It also records the entire time history. race Scope o help in tracing the changes in the mod!les and tasks with time on the Z,a)is. $ list of actions also prod!ces the desired time scales and the e)pected times for different tasks. Software and hardware en%ironment that consists of sim!lators with editors, compilers, assemblers, 4 2S, deb!ggers, stethoscope, tracer, em!lators, logic analyBers, /+42. //+42. application codes= b!rners for the integrated de%elopment of a system.

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(or sim!lating, so!rce code engineering incl!ding compiling, deb!gging and, on a Orowser, s!mmariBing the complete stat!s of the final target system d!ring the de%elopment phase. 3ses cross,assembler o!tp!t and a memory allocation map and pro%ides the locator program o!tp!t. It is the final step of software design process for the embedded system.

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In comple) or m!ltiprocessor systems, there are different models that are employed d!ring the design processes of the embedded software and its 4 2S. he models are as following. "i# (inite State .achine "(S.#. "ii# +etrinet model. "iii# Control and Data flow graph. "i%# $cti%ity diagrams based 3.9 .odel. (or m!ltiprocessor systems, the following additional models are needed. "i# Synchro, no!s Data (low "SD(# Araph. "ii# imed +etri Cets and /)tended +redicateD ransition Cet. "iii# .!lti hread Araph ". A# System. hese models are e)plained in Chapter 1.

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/mbedded systems ha%e %ery di%ersified applications. $ few select application areas of embedded systems are elecom, Smart Cards, .issiles and Satellites, Comp!ter Cetworking, Digital Cons!mer /lectronics, and $!tomoti%e. (ig!re 1.: shows the applications of embedded systems in these areas.

$ few e)amples of small scale embedded system applications are as follows: Y $!tomatic Chocolate @ending .achine Y Stepper motor controllers for a robotics system Y 8ashing or cooking system Y .!ltitasking oys Y .icrocontroller,based single or m!lti,display digital panel meter for %oltage, c!rrent, resistance and fre;!ency Y Peyboard controller Y Serial port cards Y Comp!ter .o!se Y CD dri%e or 6ard Disk dri%e controller Y he peripheral controllers of a comp!ter, for e)ample, a C4 display controller, a keyboard controller, a D4$. controller, a D.$ controller, a printer,controller, a laser printer, controller, a 9$C controller, a disk dri%e controller Y (a) or photocopy or printer or scanner machine Y Digital diary Y 4emote "controller# of @ Y elephone with memory, display and other sophisticated feat!res Y .otor controls Systems , for e)ample, an acc!rate control of speed and position of d.c. motor, robot, and CCC machine& a!tomoti%e applications s!ch as a close loop engine control, a dynamic ride control, and an anti,lock braking system monitor Y /lectronic data ac;!isition and s!per%isory control system Y /lectronic instr!ments, s!ch as an ind!strial process controller Y /lectronic smart weight display system and an ind!strial moist!re recorder c!m controller Y Digital storage system for a signal wa%e form or /lectric or 8ater .eter 4eadings Y Spectr!m analyBer Y Oiomedical systems s!ch as an /CA 9CD display,c!m,recorder, a blood, cell recorder c!m analyBer, and a patient monitor system Some e)amples of medium scale embedded systems are as follows: Y Comp!ter networking systems, for e)ample, a ro!ter, a front,end processor in a ser%er, a switch, a bridge, a h!b and a gateway Y (or Internet appliances, there are n!mero!s application systems "i# $n intelligent operation, administration and maintenance ro!ter "I2$.4# in a distrib!ted network and "ii# .ail Client card to store e,mail and personal addresses and to smartly connect to a modem or ser%er Y /ntertainment systems _ s!ch as a %ideo game and a m!sic system Y Oanking systems for e)ample, Oank $ . and Credit card transactions Y Signal racking Systems for e)ample, an a!tomatic signal tracker and a target tracker Y Comm!nication systemss!ch as a mobile,comm!nication SI. card, a n!meric pager, a cell!lar phone, a cable @ terminal, and a ($Z transcei%er with or witho!t a graphic accelerator Y Image (iltering, Image +rocessing, +attern 4ecogniBer, Speech +rocessing and @ideo +rocessing Y $ system that connects a pocket +C or +D$ "+ersonal Digital $ssistant# to the a!tomobile dri%er mobile phone and a wireless recei%er. he system then connects to a remote ser%er for Internet or e,mail or to a remote comp!ter at an $S+ "application Ser%ice +ro%ider#. his system forms the backbone of m,commerce "mobile e,commerce# and mobile comp!ting.

Y $ personal information manager !sing frame b!ffers in hand,held de%ices Y hin Client '$ hin Client pro%ides disk,less nodes with remote boot capability*. $pplication of thin,clients accesses to a data center from a n!mber of nodes& in an Internet 9aboratory accesses to the Internet leased line thro!gh a remote Ser%er. Y /mbedded (irewallD 4o!ter !sing $4.5D i371 m!lti,processor and 32 .O of (lash 42.. he load balancing and two /thernet interfaces are its other important f!nctions. hese interfaces s!pport +++, C+DI+ and 3D+ protocols. Y DC$ Se;!ence and pattern storage card and DC$ pattern recogniBer /)amples of sophisticated embedded systems are as follows: Y /mbedded systems for wireless 9$C and for con%ergent technology de%ices Y /mbedded systems for real time %ideo and speech or m!ltimedia processing systems Y /mbedded Interface and Cetworking systems !sing high speed "-?? .6B pl!s#, !ltra high speed "1? Abps# and large bandwidth: 4o!ters, 9$Cs, switches and gateways, S$Cs "Storage $rea Cetworks#, 8$Cs "8ide $rea Cetworks#, @ideo, Interacti%e %ideo and broadband I+%1 "Internet +rotocol %ersion 1# Internet and other prod!cts Y Sec!rity prod!cts and 6igh,speed Cetwork sec!rity. Aigabit rate encryption rate prod!cts Y /mbedded sophisticated system for space lifeboat "C$S$=s Z,37 proRect# !nder de%elopment. It is for a resc!e lifeboat that will be !sed in the f!t!re with the ISS "International Space Station#. In an emergency, it will bring the astrona!ts and crewmembers back to the /arth from the ISS. 8ith a press of a b!tton this lifeboat will detach from ISS and tra%el back to /arth resisting all the climaticDatmospheric conditions and meeting e)act timing constraints. his will also be a fa!lt tolerant system.

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9ately, embedded systems are being designed on a single silicon chip, called System on chip (SoC4" SoC is a new design inno3ation for embedded systems. $n embedded processor is a part of the SoC @9SI circ!it. $ SoC may be embedded with the following components: m!ltiple processors, memo, ries, m!ltiple standard so!rce sol!tions, called I+ "Intellect!al +roperty# cores and other logic and analog !nits. $ SoC may also ha%e a network protocol embedded into it. It may also embed an encryption f!nction !nit. It can embed discrete cosine transforms for signal processing applications. It may embed (+A$ "(ield +rogrammable Aate $rray# cores 'Section 1.1.0*. (or a n!mber of applications, the A++ "microcontrollers, microprocessors or DS+s# cores may not s!ffice. (or sec!rity applications, killer applications, smart card, %ideo game, palm top comp!ter, cell, phone, mobile,Internet, hand,held embedded systems, Abps transcei%ers, Aigabits per second 9$C systems and satellite or missile systems, we need special processing !nits in a @9SI designed circ!it to f!nction as a processor. hese special !nits are called $pplication Specific Instr!ction +rocessors "$SI+#. (or an application, both the config!rable processors "called (+A$ c!m $SI+ processors# and non,config!rable processors "DS+ or .icroprocessor or .icrocontrollers# might be needed on a chip. 2ne e)ample of a killer application !sing m!ltiple $SI+s is high,definition tele%ision signals processing. '6igh definition means that the signals are processed for a noise,free, echo,canceled transmission, and for obtaining a flat high,resol!tion image "1:2? ) 1?2? pi)els# on the tele%ision screen.* $ cell,phone is another killer application. '$ killer application is one that is !sef!l to millions of !sers.*

4ecently, embedded SoCs ha%e been designed for f!nctioning as G$ chips . Consider an (+A$ with a large n!mber of gate arrays. Cow, !sing @9SI design techni;!es, we can config!re these arrays to process the specific tasks on an SoC. his gi%es an SoC as a DC$ chip. /ach set of arrays has a specific and distinct DC$ comple) str!ct!re. hese str!ct!res as well as the processor embeds on the DC$ chip.

1 .IJ H K H II-": (ig!re 1.1? shows an SoC that integrates two internal $SICs, two internal processors "$SI+s#, shared memories and peripheral interfaces on a common b!s. Oesides a processor and memories and digital circ!its with embedded software for specific application "s#, the SoC may possess analog circ!its as well*. $n e)emplary application of s!ch an $SIC embedded SoC is the cell,phone. 2ne $SI+ in it is config!red to process encoding and deciphering and another does the %oice compression. 2ne $SIC dials, mod!lates, demod!lates, interfaces the keyboard and m!ltiple line 9CD matri) displays, stores data inp!t and recalls data from memory. $SICs are designed !sing the @9SI design tools with proc, essor A++ or $SI+ and analog circ!its embedded into the design. he designing is done !sing the /lectronic Design $!tomation "/D$# tool. '(or design of $SIC digital circ!its, a <6igh 9e%el Design 9ang!age "6D9#= is !sed*.

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3sing @9SI tools, a processor itself can be designed. $ system specific processor "$SI+# is the one that does not !se the A++ "standard a%ailable CISC or 4ISC microprocessor or microcontroller or signal processor#. he processor on chip incorporates a section of the CISC or 4ISC instr!ction set. his specific processor may ha%e especially config!rable instr!ction,set for an application. $n $SI+ can also be config!rable. 3sing appropriate tools, an $SI+ can be designed and config!red for the instr!ctions needed in the following e)emplary f!nctions: DS+ f!nctions, controller signals processing f!nction, adapti%e filtering f!nctions and comm!nication protocol_implementing f!nctions. 2n a @9SI chip, an embedded $SI+ in a special system can be a !nit within an $SIC or SoC.

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2n a @9SI chip, there may be high,le%el components. hese are components that possess gate,le%el sophistication in circ!its abo%e that of the co!nter, register, m!ltiplier, floating point operation !nit and $93. $ standard so!rce sol!tion for synthesiBing a higher,le%el component by config!ring (+A$ core or a core of @9SI chip may be a%ailable as an Intellect!al +roperty, called "I+#. he copyright for the synthesiBed design of a higher,le%el component for gate,le%el implementation of an I+ is held by the designer or designing company. 2ne has to pay royalty for e%ery chip shipped. $n embedded system may incorporate an I+"s# . Y $n I+ may pro%ide hardwired implement,able design of a transform or of an encryption algorithm or a deciphering algorithm. Y $n I+ may pro%ide a design for adapti3e filtering of a signal. Y $n I+ may pro%ide f!ll design for implementing 6yper e)t ransfer +rotocol "6 +# or (ile ransfer +rotocol "( +# to transmit a web page or a file on the Internet. Y $n I+ may be designed for the +CI or 3SO b!s controller. 'Sections 3.3 and 3.-*

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$ Aeneral +!rpose +rocessor "A++# can be embedded on a @S9I chip. 4ecently, e)emplary A++s, called $4. 5 and $4. :, which embed onto a @9SI chip, ha%e been de%eloped by $4. and their enhancements by e)as Instr!ments. '4efer to http:Dwww.ti.comDscD docsDasicDmod!lesDarm5.htm and arm:.htm*. $n $4.,processor @9SI,architect!re is a%ailable either as a C+3 chip or for integrat, ing it into @9SI or SoC. ' he instr!ction set feat!res of the $4. is gi%en in Section $.1.* $4. pro%ides CISC f!nctionality with 4ISC architect!re at the core. $n application of $4. embed circ!it is IC/ 'Section 12.3.2*. IC/ is !sed for deb!gging an embedded system. /)emplary $4. : applica, tions are set!p bo)es, cable modems, and wireless de%ices s!ch as mobile handsets. $4.: 'Section 2.2.0* has a single cycle 11 ) 32 m!ltiply acc!m!late !nit. It operates at 2?? .6B. It !ses ?.10 mm AS3? C.2Ss. It has a fi%e,stage pipeline. It incorporates 4ISC. It integrates with a DS+ when designing an $SIC sol!tion ha%ing m!ltiprocessors= architect!re 'Section 1.3*. $n e)am, ple is its integration with DS+ with .S32?C00). $ lower capability b!t %ery pop!lar %ersion of $4.: is $4.5. It operates at 7? .6B clock. It !ses ?.17 mm based AS2? C.2Ss. 3sing $4.5, a large n!mber of embedded systems ha%e recently become a%ailable. 2ne recent application is in inte, grating the operating system 9in!) Pernel 2.2 and the de%ice dri%ers into an $SIC.

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$ new inno%ation is (ield +rogrammable Aate $rrays "(+A$# core with a single or m!ltiple processor !nits on chip. 2ne e)ample is Zilin) @irte),II +ro (+A$ ZC2@+120. 2ther e)ample is :? nm Spartan, 3 (+A$ released on $pril 1-, 2??3 by Zilin). '$n (+A$ consists of a large n!mber of programmable gates on a @9SI chip. here is a set of gates in each (+A$ cell, called <macro cell=. /ach cell has se%eral inp!ts and o!tp!ts. $ll cells interconnect like an array "matri)#. /ach interconnection is f!sible "detachable# !sing a (+A$ programming tool.* he interested reader can refer to the recent articles in <Zcell Wo!rnal= 2??2 and <Zcell Wo!rnal= 2??3. Consider the algorithms for the following: an SI.D instr!ction, (o!rier transform and its in%erse, D( or 9aplace transform and its in%erse, compression or decompression, encrypting or deciphering, a specific pattern,recognition "for recogniBing a signat!re or finger print or DC$ se;!ence#. 8e can config!re "f!se# an algorithm into the logic gates of the (+A$. It gi%es !s hardwired implementation for a processing !nit. It is specific to the needs of the embedded system. $n algorithm of the embed, ded software can implement in one of the (+A$ section and another algorithm in its other section. $n e)emplary latest SoC design is on the HC6/P*6) system" It has *6)*5+ logic cells in the IP;$ core with four IJ# PowerPCs. It has been %ery recently !sed for de%eloping embedded systems integrated with programmable logic. (or e)ample, there is a sol!tion reported for data sec!rity with encryption engine and data rate of 1.0 gigabits per second. 2ther e)emplary embedded systems inte, grated with logic arrays are DS+,enabled, real,time %ideo processing systems and line echo eliminators for the +!blic Switched elecomm!nication Cetworks "+S C# and packet switched networks. '$ packet is a !nit of a message or a flowing data s!ch that it can follow a programmable ro!te among the n!mber of optional open ro!tes a%ailable at an instance*.

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(ig!re 1.11 shows embedded,system hardware components on an SoC for a contact,less smart card. Its components are as follows: 'Section 11.- will describe a case st!dy of embedded software design.* Y $SI+ "$pplication Specific Instr!ction +rocessor# Y 4$. for temporary %ariables and stack Y 42. for application codes and 4 2S codes for sched!ling the tasks Y //+42. for storing !ser data, !ser address, !ser identification codes, card n!mber and e)piry date Y imer and Interr!pt controller Y $ carrier fre;!ency T11 .6B generating circ!it and $mplit!de Shifted Pey "$SP# .od!lator. $SP mod!lator gi%es 1?M e)cess amplit!de of carrier p!lses for bit <1= and 1?M less for bit <?=. $ load mod!lation s!b,carrier has one,si)teenth of this fre;!ency and mod!lates the 1s and ?s by Oinary +hase Shifted Peying "O+SP#. Y Interfacing circ!it for the ID2s Y Charge p!mp for deli%ering power to the antenna "of T0 mm range# for transmission and for system circ!its. he charge p!mp stores charge from recei%ed 4( "radio fre;!ency# at the card antenna hear its host in %icinity. ' he charge p!mp is a simple circ!it that consists of a diode and a high %al!e ferroelectrics material,based capacitor.*

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he embedded system is a sophisticated system consisting of se%eral hardware and software components, and its design may be se%eral times more comple) than that of a +C and the programs r!nning on a +C. Y he embedded system processor can be a general,p!rpose processor chosen from n!mber of families of processors, microcontrollers, embedded processors and digital signal processors "DS+s#. $lternati%ely, an application specific instr!ction processor "$SI+# may be designed for specific application on a @9SI chip. $n $SS+ may be additionally !sed for fast hardwired implementation of a certain part of the embedded software. $ sophisticated embedded system may !se a m!ltiprocessor !nit also. Y /mbedded system embeds "locates# a software image in the 42.. he image mostly consists of the following: "i# Ooot !p program. "ii# InitialiBation data. "iii# Strings for an initial screen, display or system state. "i%# +rograms for the m!ltiple tasks that the system performs. "%# 4 2S kernel.

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he embedded system needs a power so!rce and controlled and optimiBed power,dissipation from the total energy re;!irement for gi%en hardware and software. he charge p!mp pro%ides a power,s!pply,less system in certain embedded systems. he embedded system needs clock and reset circ!its. 3se of the clock manager is a recent inno%ation. he embedded system needs interfaces: Inp!t 2!tp!t "IE# ports, serial 1$8T and other pots to accept inp!ts and to send o!tp!ts by interacting with the peripherals, display !nits, keypad or keyboard. he embedded system may need b!s controllers for networking its b!ses with other systems. he embedded system needs timers and a watchdog timer for the system clock and for real, time program sched!ling and control. he embedded system needs an interrupt controlling unit" he embedded system may need $DC for taking analog inp!t from one or m!ltiple so!rces. It needs D$C !sing +8. for sending analog o!tp!t to motors, speakers, so!nd systems, etc. he embedded system may need an 9/D or 9CD display !nits, keypad and keyboard, p!lse dialer, modem, transmitter, m!ltiple)ers and dem!ltiple)ers. /mbedded software is !s!ally made in the high,le%el lang!ages C or C>> or Wa%a with certain feat!res added, enabled or disabled for programming. <C= and C>> also facilitates the incorporation of assembly lang!age codes. he embedded system most often needs a real,time operating system for real,time programming and sched!ling, de%ice dri%ers, de%ice management and m!ltitasking. here are a n!mber of software tools needed in the de%elopment and design phase of an embedded system. '4efer to able 1.5.* here are a large n!mber of applications and prod!cts that employ embedded systems. $ @9SI chip can embed I+s for the specific applications, besides the $SI+ or a A++ core. $ system,on,chip is the latest concept in embedded systems, for e)ample, a mobile phone. $ contact,less smart card is one s!ch application, the detail !nits of which were shown in (ig!re 1.11.

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Y System: $ way of working, organiBing or doing some task or series of tasks by following the fi)ed plan, program and set of r!les Y Embedded system: $ sophisticated system that has a comp!ter "hardware with application software and 4 2S embedded in it# as one of its components. $n embedded system is a dedicated comp!ter,based system for an application or prod!ct. Y Processor: $ processor implements a process or processes as per the command "instr!ction# gi%en to it. Y Process: $ program or task or thread that has a distinct memory allocation of its own and has one or more functions or procedures for specific 9ob" The process may share the memory (data4 with other tas.s" $ processor may run multiple processes separately or concurrently" Y #icrocontroller: $ !nit with a processor. .emory, timers, watchdog timer, interr!pt controller, $DC or +8., etc. are pro%ided as re;!ired by the application.

Y ;PP (;eneral-purpose processor4: $ processor from a n!mber of families of processors, microcontrollers, embedded processors and digital signal processors "DS+s# ha%ing a general, p!rpose instr!ction set and readily a%ailable compilers to enable programming in a high le%el lang!age. Y $SSP ($pplication Specific System Processor4: $ processing !nit for specific tasks, for e)ample, image compression, and that is integrated thro!gh the b!ses with the main processor in the embedded system. Y $SIP ($pplication specific Instruction processor4: $ processor designed for specific application on a @9SI chip. Y IP;$: hese are (ield +rogrammable Aate $rrays on a chip. he chip has a large n!mber of arrays with each element ha%ing f!sable links. /ach element of array consists of se%eral Z24, $CD, 24, m!ltiple)er, dem!ltiple)er and tristate gates. Oy appropriate programming of the f!sable links, a design of a comple) digital circ!it is created on the chip. Y 8egisters : hese are associated with the processor and temporarily store the %ariable %al!es from the memory and from the e)ec!tion !nit d!ring processing of an instr!ction "s#. Y Cloc.: (i)ed fre;!ency p!lses that an oscillator circ!it generates and that controls all operations d!ring processing and all timing references of the system. (re;!ency depends on the needs of the processor circ!it.$ processor, if it needs 1?? .6B clock then its minim!m instr!ction processing time is a reciprocal of it, which is 1? ns. Y 8eset: $ processor state in which the processor registers ac;!ire initial %al!es and from which starts an initial program& this program is !s!ally the one that also r!ns on power !p. Y 8eset circuit: $ circ!it to force reset state and that gets acti%ated for a short period on power !p. 8hen reset is acti%ated, the processor generates a reset signal for the other system !nits needing reset. Y #emory: his stores all the programs, inp!t data and o!tp!t data. he processor fetches instr!ctions from it to e)ec!te and gi%es the processed res!lts back to it as per the instr!ction. Y 8E#: $ read only memory that locates the following in its 42., embedded software, initial data and strings and operating system or 4 2S. Y 8$#: his is a 4andom $ccess 4ead and 8rite memory that the processor !ses to store programs and data that are %olatile and which disappear on power down or off. Y Cache: $ fast read and write on,chip !nit for the processor e)ec!tion !nit. It stores a copy of a page of instr!ctions and data. It has these fetched in ad%ance from the 42. and 4$. so that the processor does not ha%e to wait for instr!ction and data from e)ternal b!ses. Y Timer : $ !nit to pro%ide the time for the system clock and real,time operations and sched!ling. Y 7atchdog timer: $ timer the timeo!t from which resets the processor in case the program gets st!ck for an !ne)pected time. Y Interrupt controller: $ !nit that controls the processor operations arising o!t of an interr!pt from a so!rce. Y $ C: $ !nit that con%erts, as re;!ired, the analog inp!t between > and _ pins with respect to the reference %oltage "s# to digital 7 or 1? or 12 bits. Y P7#: +!lse width mod!lator to pro%ide a p!lse of width scaled to the analog o!tp!t desired. 2n integrating +8. o!tp!t, the D$C operation is achie%ed. Y $C: Digital bits "7 or 1? or 12# con%erted to analog signal scaled to a reference %oltage "s#.

Y Input Eutput (IE4 ports: he system gets the inp!ts and o!tp!ts from these. hro!gh these, the keypad or 9CD !nits attach to the system. Y 1$8T: 3ni%ersal $synchrono!s 4ecei%er and ransmitter. Y 0E : 9ight /mitting diodeLa diode that emits red, green, yellow or infrared light on forward biasing between 1.1@ to 2 @ and c!rrents between 7 , 10m$. .!lti,segment and m!lti,line 9/D !nits are !sed for bright display of digits, characters, charts and short messages. Y 0C : 9i;!id Crystal diodeLa diode that absorbs or emits light on application of 3 to - @ 0? or 1? 6B %oltage p!lses with c!rrents T 0? m$. .!lti,segment and m!lti,line 9CD !nits are !sed for a display of digits, characters, charts and short messages with %ery low power dissipation. Y #odem: $ circ!it to mod!late the o!tgoing bits into p!lses !s!ally !sed on the telephone line and to demod!late the incoming p!lses into bits for incoming messages. Y #ultiple%er: $ digital circ!it that has digital inp!ts from m!ltiple channels. It sends only one channel o!tp!t at a time. he channel at the o!tp!t has the same address as the channel address bits in its inp!t. Y emultiple%er : $ digital circ!it that has digital o!tp!ts at any instance in m!ltiple channels. he channel that is connected is the one that has the same address as the channel address bits in its inp!t. Y Compiler: $ program that, according to the processor specification, generates machine codes from the high le%el lang!age. he codes are called obRect codes. Y $ssembler: $ program that translates assembly lang!age software into the machine codes placed in a file called <.e)e= "e)ec!table# file. Y 0in.er: $ program that links the compiled codes with the other codes and pro%ides the inp!t for a loader or locator. Y 0oader! It is a program that reallocates the physical memory addresses for loading into the system 4$. memory. 4eallocation is necessary, as a%ailable memory may not start from ?)???? at a gi%en instant of processing in a comp!ter. he loader is a part of the 2S in a comp!ter. Y 0ocator: It is a program to reallocate the linked files of the program application and the 4 2S codes at the act!al addresses of the 42. memory. It creates a file in a standard format. (ile is called 42. image. Y e3ice Programmer: It takes the inp!ts from a file generated by the locator and b!rns the f!sable link to act!ally store the data and codes at the 42.. Y #as. and 8E# mas.: Created at a fo!ndry for fabrication of a chip. he 42. mask is created from the 42. image file. Y Physical e3ice: $ de%ice like a printer or keypad connected to the system port. Y /irtual e3ice: $ file or pipe that is programmed for opening and closing and for reading and writing, s!ch as a program for attaching and detaching a physical de%ice and for inp!t and o!tp!t. Y Pipe: $ data str!ct!re "or 3irtual de3ice# which is sent a byte stream from a data so!rce "for e)ample, a program str!ct!re# and which deli%ers the byte stream to the data sink "for e)ample, a printer#. Y Iile: $ data str!ct!re "or 3irtual de3ice# which sends the records "characters or words# to a data sink "for e)ample, a program str!ct!re# and which stores the data from the data so!rce "for e)ample, a program str!ct!re#. $ file in comp!ter may also be stored at the hard disk.

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e3ice ri3er: Interr!pt Ser%ice ro!tine Software, which r!ns after the programming of the control register "or word# of a peripheral de%ice "or %irt!al de%ice# and to let the de%ice get the inp!ts or o!tp!ts. It e)ec!tes on an interr!pt to or from the de%ice. e3ice manager: Software to manage m!ltiple de%ices and dri%ers. #ultitas.ing: +rocessing codes for the different tasks as directed by the sched!ler. :ernel: $ program with f!nctions for memory allocation and de,allocation, task sched!ling, inter,process comm!nication, effecti%e management of shared memory access by !sing the signals, e)ception "error# handling signals, semaphores, ;!e!es, mailbo)es, pipes and sockets 'See Section 7.3*, ID2 management, interr!pts control "6andler#, de%ice dri%ers and de%ice management. 8eal-time operating system : 2perating System software for real,time programming and sched!ling, process and memory manager, de%ice dri%ers, de%ice management and m!ltitasking. /0SI chip: $ %ery large,scale integrated circ!it made on silicon with T 1. transistors. System on Chip: $ system on a @9SI chip that has all of needed analog as wells as digital circ!its, for e)ample, in a mobile phone.

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1. Define a system. Cow define embedded system. 2. 8hat are the essential str!ct!ral !nits in "a# microprocessor "b# /mbedded processor "c# .icrocontroller "d# DS+ "e# $SI+ "f# $SI+F 9ist each of these. 3. 6ow does a DS+ differ from a general,p!rpose processor "A++#F 4efer Sections 1.2.0 and D.2. -. 8hat are the ad%antages and disad%antages of "a# a processor with only fi)ed,point arithmetic !nit and "b# a processor with additional floating,point arithmetic processing !nitF 0. $ new inno%ation is media processors 'Section /.1.* 4efer Sections 1.2.0, D.2 and /.1. 6ow does a media processor differ from a DS+F 1. /)plain the media processor !se in con%ergence technology embedded system like mobile phone with mail client, Internet connecti%ity and image,frame downloads. 5. Compare feat!res in an e)emplary family chip "or core# of each of the following: .icroprocessor, .icrocontroller, 4ISC +rocessor, Digital Signal +rocessor, $SS+, @ideo processor and media processor. 4efer Section 1.2 and $ppendices $ to /. 7. 8hy does late generation systems operate processor at low %oltages "^2 @# and I2 at "T3.3@#F :. 8hat are the techni;!es of power and energy management in a systemF 1?. 8hat is the ad%antage of r!nning a processor at red!ced clock speed in certain section of instr!ctions and at f!ll speed in other section of instr!ctionsF 11. 8hat is the ad%antage of the followingsF "a# Stop instr!ction "b# 8ait instr!ction "c# +rocessor idle mode operation "d# Cache,!se disable instr!ction "e# Cache with m!lti,ways and blocks in an embedded system. 12. 8hat do we mean by charge p!mpF 6ow does a charge p!mp s!pply power in an embedded system witho!t !sing the power s!pply linesF 13. 8hat do yo! mean by <real time= and <real time clock=F

1-. 10. 11. 15. 17. 1:. 2?. 21. 22. 23. 2-. 20. 21. 25. 27. 2:. 3?. 31. 32. 33. 3-.

8hat is the role of processor reset and system resetF /)plain the need of watchdog timer and reset after the watched time. 8hat is the role of 4$. in an embedded systemF 8hy do we need m!ltiple actions and m!ltiple controlling tasks for the de%ices in an embedded systemF /)plain it with an e)ample of the embedded system, a remote of color @. 8hen do we need m!ltitasking 2SF 8hen do we need an 4 2SF 8hy sho!ld be embedded system 4 2S be scalableF /)plain the terms I+ core, (+A$, C+9D, +9$ and +$9 8hat do yo! mean by System,on,Chip "SoC#F /)amine the designed table in [!estion 1.3 abo%e. 6ow will the definition of embedded system change with System,on,ChipF 8hat are the ad%antages offered by an (+A$ for designing an embedded systemF 8hat are the ad%antages offered by an $SIC for designing an embedded systemF 8hat are the ad%antages offered by an $SI+ for designing an embedded systemF 4eal time %ideo processing needs sophisticated embedded systems with hard real time constraints. 8hyF /)plain it. 8hy does a processor system always need an <Interr!pts 6andler "Interr!pt Controller#=F 8hat does role linker playF 8hy do we !se loader in a comp!ter system and locator in an embedded systemF 8hy does a program reside in 42. in the embedded systemF Define 42. image and e)plain each section of an 42. image in an e)emplary system. 8hen will yo! !se the compressed program and data in 42.F Ai%e fi%e e)amples of embedded systems ha%ing these in their 42. images. 8hen will yo! !se S4$. and when D4$.F /)plain yo!r replies. 8hat do we mean by the following: +hysical de%ice, @irt!al de%ice, +l!g and +lay de%ice, O!s self,powered de%ice, de%ice .anagement and De%ice Specific +rocessor.

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30. Search definitions of embedded system from books referred in <4eferences= and tab!late these with definitions in col!mn 1 and reference in col!mn 2. 31. Classify the embedded systems into small scale, medi!m scale and sophisticated systems. Cow, reclassify these embedded systems with and witho!t real,time "response time constrained# systems and gi%e 1? e)amples of each. 35. $n a!tomobile cr!ise control system is to be designed in a proRect. 8hat will be skills needed in the team of hardware and software engineersF 37. ake a %al!e, % \ 1.532?0?7?50177. It is s;!ared once again by a floating,point arithmetic processor !nit. Cow % is s;!ared by a 11,bit integer fi)ed point arithmetic processing !nit. 6ow does the res!lt differF 'Cote: (i)ed,point !nit will m!ltiply only 1532? with 1532?, di%ide the res!lt by 1???? and then again di%ide the res!lt by 1????.* 3:. Design fo!r col!mns table two e)amples of embedded systems in each row=s col!mns 2 and 3. Col!mn 1: the type of processor needed among the followings: .icroprocessor, .icrocontroller, /mbedded +rocessor, Digital Signal +rocessor, $SS+, @ideo,processor and .edia processor. Ai%e reasoning in col!mn -.

-?. 8hy does 2 a C.2S I2 circ!it power dissipation red!ces by compared to 0@, factor of half, T"3.3D0# , in I2 3.3@ operationF -1. 6ow m!ch shall be red!ction in power dissipation for a processor C.2S circ!it when @ red!ces from 0@ to 1.7@ operationF -2. 4efer Sections 1.3.0 and A.1 to A.3. 9ist %ario!s type of memories and application of each in the followings: 4obot, /lectronic smart weight display system, /CA 9CD display,c!m, recorder, 4o!ter, Digital Camera, Speech +rocessing, Smart Card, /mbedded (irewallD 4o!ter, .ail Client card, and ransrecei%er system with a collision control and Rabber control 'Collision control means transmission and reception when no other system on the network is !sing the network. Wabber control means control of contin!o!s streams of random data flowing on a network, which e%ent!ally chokes a network.* -3. ab!late hardware !nits needed in each of the system mentioned in [!estion -2 abo%e. --. Ai%e two e)amples of embedded systems, which need one or more of following !nits. "a# D$C "3sing a +8.# "b# $DC "c# 9CD display "d# 9/D Displays "e# Peypad "f# +!lse Dialer "g# .odem "h# ranscei%er "i# A+IO "I/// -77# 9ink -0. $n $DC is a 1?,bit $DCF It has reference %oltages, @ref, \ ?.?@ and @ ref> \ 1.?23@.

8hat will be the $DC o!tp!ts when inp!ts are "a# _ ?.012 @ "b# > ?.012 @ and "c# >2?-5@F 8hat shall be $DC o!tp!ts in three sit!ations when "i# @ref, \ ?.012 @ and @ ref> \ 1.?23@ "ii# @ref, \ 1.?2@ and @ \ 2.?-5@ and "ii# @ \ ,1.?2- @ and @ \ >2.?-5@.
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-1. 4efer Sections 1.-, 0.1, 0.7 and 0.:. ab!late the ad%antages and disad%antages of !sing coding lang!age as following: "a# (inal .achine Implementable "b# $9+ "$ssembly 9ang!age +rogramming "c# <C= "d# C>> "e# Wa%a -5. 9ist the software tools needed in designing each of the /mbedded System e)amples in [!estion -2. -7. W!stify the importance of de%ice dri%ers in an embedded system. 4efer to Section 1.-.0 and -.1.3. -:. Cost of designing an embedded system may be tho!sands of times the cost of its processor and hardware !nits. /)plain this statement. 0?. (+A$ "(ield +rogrammable Aate $rrays# core integrated with a single or m!ltiple processor !nits on chip and (+S9IC "(ield +rogrammable System 9e%el Integrated Circ!its# are recent no%el inno%ations. 6ow do these help in the design of sophisticated embedded systems for real time %ideo processingF