CHAPTER5 IMPLIMENTATION AND SIMULATION RESULT

5.1HOW TO SIMULATE AND IMPLIMENT RC6 ALCORITHM?

We have implemented cryptography in Xilinx 9.2i edition software.We have seen how to make a program in Xilinx now we will see the results. And we will also come to know that how to give inputs and how to check test bench and see output. R ! schematic shows a functional digital circuit having inputs and outputs. section. est bench waveform is used to check whethre our digital circuit works perfectly or not.for that specific steps must be followed as described in this

5.2 TESTING METHODOLOGY

our design should be tested by developing a testbench that " #$% Reads in plaintext" user&supplied keys" and expected ciphertext from a file. #2% 'ses the key scheduler to take the user&supplied keys and generate the round keys. #(% )end the appropriate the control signals" plaintext" and round keys to the encryptor and decryptor. #*% ests to ensure that the ciphertext is correctly generated and that the plaintext from the decryptor matches the plaintext to the encryptor. +f discrepancies occur between the expected results and actual results" errors should be reported.
1) 2) 3) ") ') A diagram showing the logical hierarchy of your modules including module names and brief descriptions of what each module does. Detailed block diagrams for the encryptor and decryptor, which show registers, functional units, multiplexers, control signals, etc. tate transition graphs or A ! charts for the finite state machines that control your encryptor and decryptor. #$D% code for your encryptor, decryptor, key scheduler, and testbench. &his code should be commented well. (re)synthesis simulation results for the modules from part '. *nclude comments and annotated wa+eform for ease of interpretation of results. Also indicate whether or not results are correct and any known bugs.

5.3 ABOUT RTL SCHEMETIC

1) Afte !"e!#$%& '(%te) '*!!e''f*++(, RTL '!"e-.t$! !.% /e 0$e1e2 f 3- PROCESSES4 5IEW RTL SCHEMATIC .It '"31' 2$&$t.+ !$ !*$t $%6*t .%2 3*t6*t 2$.& .- f3 RC6 ENCRYPTION .+&3 $t"-.

2) RTL '!"e-.t$! 3f 2e! (6t3

Afte !"e!#$%& '(%te) '*!!e''f*++(, RTL '!"e-.t$! !.% /e 0$e1e2 f 3- PROCESSES4 5IEW RTL SCHEMATIC .It '"31' 2$&$t.+ !$ !*$t $%6*t .%2 3*t6*t 2$.& .- f3 RC6 DECRYPTION .+&3 $t"-.

) ,-$.& for giving the inputs we change from synthesis and implementation to behavioral simulation and add a new source by right clicking on pro/ect name

) ,- 2.& then the screen appears as shown below . in that screen select a test bench waveform and write the name we wan to give to test bench .

) ,- (.& then in clock input window select single clock and give clock high and low time as $0ns and all other parameters as shown below.

) ,- *.& +n fig below we can see how to give inputs to encryptor .inputs are given after delay of 20ns staring from 10ns and giving $2 bit input after every 20ns. $2 bit round keys are also given as shown and a start3e signal is made high so that program takes inputs.

) ,- 1.&+n fig below we can see the output test bench of encryptor the cipher text is available after $400ns. he cipher text is available after ready3e signal goes high.this cipher text is given to decryptor

) ,- 2.&)imilarly output of encryptor is given to decryptor after same time delay as in encryptor and start signal and round keys are also given

) ,- 5.&When simulation is done we can see output of decryptor as shown below. he plain text which was given in encryptor is obtained in decryptor output.

SYNTHESIS REPORT 7OR ENCRYPTOR )tates 6 ransitions +nputs 7utputs 8lock Reset 6Reset type Reset )tate ,ncoding +mplementation $2 $* 2 $$ rising3edge positive asynchronous 00000$ automatic automatic

MACRO STATISTICS 9):s $

Adders;)ubtractors $2&bit adder 8ounters 5&bit up counter Registers 9lip&9lops !atches $2&bit latch :ultiplexers $2&bit $2&to&$ multiplexer Xors $2&bit xor2 $2&bit xor(

$(1 $(1 $ $ $95 $95 $ $ 2 2 $2 2 $*

7INAL RESULTS R ! op !evel 7utput 9ile <ame encryptor.ngr op !evel 7utput 9ile <ame 7utput 9ormat 7ptimi>ation =oal ?eep @ierarchy arget echnology :acro -reserve A,) A,) wysiwyg encryptor <=8 )peed A,) )-AR A< ( A,) A,) A,) <7

Besign )tatistics C +7s

12

Ce++ U'.&e8 A<B$ A<B2 A<B( A<B* A<B1 =<B +<D 7R2 7R( 7R1 D88 X7R2 9lip9lops;!atches 9B8 9B8, 9 8 !B +7 Euffers +E'9 7E'9 8-'.22.55 ; 22.9$ s 6,lapsed . 25.00 ; 25.00s 99$1 996: :; 1; 3 1 15:< 3635 <: 1 1 33 2== 6: 112 9 16 52 35 1< otal memory usage is 221120 kilobytes

SYNTHESIS REPORT 7OR DECRYPTOR

)tates ransitions +nputs 7utputs 8lock Reset Reset type Reset )tate ,ncoding

$2 $* 2 $2 clock #rising3edge% reset #positive% asynchronous 00000$ automatic

+mplementation automatic

M.! 3 St.t$'t$!' C Adders;)ubtractors $2&bit adder $2&bit subtractor C 8ounters 5&bit up C Registers $(1 $29 2 $ $ $2

$&bit register $2&bit register C 8omparators C !ogic shifters

$ $$ $ 2

$2&bit shifter logical right 2 C Xors $&bit xor2 $2&bit xor2 $2&bit xor( 54 22 2 $*

7INAL RESULTS R ! op !evel 7utput 9ile <ame decryptor.ngr op !evel 7utput 9ile <ame 7utput 9ormat 7ptimi>ation =oal ?eep @ierarchy arget echnology :acro -reserve X7R -reserve 8lock ,nable wysiwyg decryptor <=8 )peed A,) )-AR A< ( A,) A,) A,) <7

Ce++ U'.&e 8 C E,!) C C C C A<B2 A<B( A<B1 =<B $0(12 **50 $4$ 2 $

C C C C C

+<D 7R2 7R( 7R* X7R2

$915 (*40 224 $ (2 $9$ 4* $0( * 12 (1 $5 ,lapsed . 22.00 ; 25.00 s

C 9lip9lops;!atches C C C 9B8 9B8, 9 8

C +7 Euffers C C +E'9 7E'9

8-' . 22.2* ; 25.12 s otal memory usage is 22$*2* kilobytes