141 Review

CSE 141 Discussion
Final Review
Branch Prediction
Branch Pattern: T, T, T, NT, NT
What is the accuracy of always taken and

always-not-taken predictors for this
sequence?
Always taken: 3/5 = 60%
Always not taken: 2/5 = 40%
Branch Prediction
What is the accuracy of the two-bit predictor

for the first four branches in the pattern,
assuming the predictor starts off at strongly
not taken?
Outcomes: T, T, T, NT
Predictor Values at prediction time: 00, 01, 10, 11
Accuracy: 25%
Branch Prediction
What is the accuracy of the two-bit predictor

if this pattern is repeated forever?
Values at 1st Pass: 00, 01, 10, 11, 10 (20%)
Values at 2nd Pass: 01, 10, 11, 11, 10 (40%)
Values at nth Pass: 01, 10, 11, 11, 10 (40%)
Accuracy: 40%
Branch Prediction
Design a predictor that would achieve a perfect

accuracy if the pattern was repeated forever.
Requires a working knowledge of the branch
Create an N-bit Shift Register
Every time the register is accessed, it shifts one bit to the
right
Initialize the target branch pattern into the register

What are the problems of doing something like this?
Direct Mapped Caching

Memory Access Pattern: 1, 134, 212, 1, 135, 213, 162, 161, 2, 44, 41, 221
What does the cache look like if you have a

direct-mapped cache with 2-word blocks and
8 blocks? Show Hit/Miss rates as well.
Need a couple tables
Show a table that shows the index calculation and
whether it hits or misses the cache
Show a table of the cache to show what is in the
cache at that moment.

First address to go into cache

Index
Tag
000
0000
001
010
011
100
101
110
111
Tag
Index
Offset
H/M
0000
000

Nothing interesting to see here
Tag
Index
Offset
H/M
0000
000
Index
Tag
1000
011
000
0000
1101
010
001
010
1101
011
1000
100
101
110
111

First cache hit for Mem Address = 1!
Tag
Index
Offset
H/M
0000
000
Index
Tag
1000
011
000
0000
1101
010
0000
000
001
010
1101
011
1000
100
101
110
111

Wait135 isnt the same as 134, what gives?!
Same with 213!
Tag
Index
Offset
H/M
0000
000
Index
Tag
1000
011
000
0000
1101
010
0000
000
001
010
1101
1000
011
011
1000
1101
010
100
101
110
111

First Conflict and Replacement
Tag
Index
Offset
H/M
0000
000
Index
Tag
1000
011
000
0000 1010
1101
010
001
1010
0000
000
010
1101
1000
011
011
1000
1101
010
100
1010
001
101
1010
000
110
111

More Conflicts
Tag
Index
Offset
H/M
0000
000
Index
Tag
1000
011
000
1010
1101
010
001
1010 0000
0000
000
010
1101
1000
011
011
1000
1101
010
100
1010
001
101
1010
000
110
0000
001
111

Filling up the rest of cache
Tag
Index
Offset
H/M
0000
000
Index
Tag
1000
011
000
1010
1101
010
001
0000
0000
000
010
1101
1000
011
011
1000
1101
010
100
0010
1010
001
1010
000
0000
001
0010
110
0010
100
1101
110
101
110
111
0010 1101
What about associative caches?

Lets use the same instruction stream, but
have a 3-way set associative cache with twoword blocks and a total size of 24 words.
Waithow many possible indices will we have
then?
We will use LRU replacement to evict old data

from the cache.
Set-Associative Caching
Filling up Cache
Index
Tag[0]
00
00000
01
10
11010
11
10000
Tag[1]
Tag[2]
Tag
Index
Offset
H/M
00000
00
10000
11
11010
10
Bunch of hits!
Index
Tag[0]
00
00000
01
Tag[1]
Tag[2]
Tag
Index
Offset
H/M
00000
00
10000
11
11010
10
00000
00
10
11010
10000
11
11
10000
11010
10
Filling up more Cache
Tag
Index
Offset
H/M
00000
00
Index
Tag[0]
Tag[1]
Tag[2]
10000
11
00
00000
10100
00101
11010
10
01
10100
00000
00000
00
10
11010
00101
10000
11
11
10000
11010
10
10100
01
10100
00
00000
01
00101
10
00101
00
11011
10
11011
Example of LRU Step 1
Tag
Index
Offset
H/M
00000
00
Index
Tag[0]
Tag[1]
Tag[2]
10000
11
00
00000
00001
10100
00101
11010
10
00000
00
01
10100
00000
10000
11
10
11010
00101
11010
10
11
10000
10100
01
10100
00
00000
01
11011
NEW STREAM ADDRESSES: 8, 161, 1

Tag
Index
Offset
H/M
00101
10
00001
00
00101
00
10100
00
11011
10
Example of LRU Step 2
Tag
Index
Offset
H/M
00000
00
Index
Tag[0]
Tag[1]
Tag[2]
10000
11
00
00001
10100
00101
00000
11010
10
00000
00
10000
11
11010
10
10100
01
10100
00
00000
01
01
10100
00000
10
11010
00101
11
10000
11011
NEW STREAM ADDRESSES: 8, 161, 1

Tag
Index
Offset
H/M
00101
10
00001
00
00101
00
10100
00
11011
10
00000
00
TLB
Think of it as a cache for virtual memory
Operates in pretty much the same way as a
cache does
They tend to be fully associative
Will have some form of LRU (since true LRU is
difficult to implement in hardware)
Question: Show the TLB after a set of memory

addresses go through it.
TLB
Memory Access Pattern: 9452, 30964, 19136, 46502, 38110, 16653, 48480
Valid
Phys Page or Disk
Valid
Tag
Page Num
Disk
11
12
Disk
11
Disk
Disk
Disk
12
TLB
Address: 9452, TLB Miss AND Page Fault!
(Tag is 2)
Valid
Tag
Page Num
Valid
Phys Page or Disk
Disk
11
12
13
13
11
Disk
Disk
Disk
12
TLB
Address: 30964, TLB Hit (Tag is 7)
Valid
Phys Page or Disk
Valid
Tag
Page Num
Disk
11
12
13
13
11
Disk
Disk
Disk
12
TLB
Address: 19136, TLB Miss (Tag is 4 Replace 11)
Valid
Phys Page or Disk
Valid
Tag
Page Num
Disk
13
13
11
Disk
Disk
Disk
12
TLB
Address: 46502, TLB Miss (Tag is 11 Replace 3)
Valid
Phys Page or Disk
Valid
Tag
Page Num
Disk
13
11
12
13
11
Disk
Disk
Disk
12
TLB
Address: 38110, Page Fault! (Tag is 9 Replace 2)
Valid
Phys Page or Disk
Valid
Tag
Page Num
Disk
13
11
12
14
11
Disk
Disk
14
12
TLB
Address: 16553 (Tag = 4) Hit
Address: 48480 (Tag = 11) Hit
Valid
Tag
Page Num
Valid
Phys Page or Disk
Disk
13
11
12
14
11
Disk
Disk
14
12
What do we replace next?

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CSE 141 Discussion

What is the accuracy of always taken and

What is the accuracy of the two-bit predictor

What is the accuracy of the two-bit predictor

Design a predictor that would achieve a perfect

Initialize the target branch pattern into the register

Direct Mapped Caching

What does the cache look like if you have a

Direct Mapped Caching

First address to go into cache

Direct Mapped Caching

Nothing interesting to see here

Direct Mapped Caching

First cache hit for Mem Address = 1!

Direct Mapped Caching

Direct Mapped Caching

Direct Mapped Caching

Direct Mapped Caching

What about associative caches?

We will use LRU replacement to evict old data

NEW STREAM ADDRESSES: 8, 161, 1

NEW STREAM ADDRESSES: 8, 161, 1

Question: Show the TLB after a set of memory

Phys Page or Disk

Phys Page or Disk

Phys Page or Disk

Phys Page or Disk

Phys Page or Disk

Phys Page or Disk

Phys Page or Disk

What do we replace next?

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