LTCC Design Flow

Outline
Current methodologies employed today Ideal LTCC design methodology Challenges associated with reaching an ideal design methodology
Accurate modeling Integrated solution Library availability

Solutions to the current challenges Steps to reaching an ideal LTCC design methodology Demonstration of the implementation of the LTCC design methodology

LTCC Technology

X-ray view from top

Photograph view from top (no top layer conductor tracks)

Auto Assembly of components

LTCC Module Applications

RF/ Wireless includes:

WLAN Bluetooth Mobile Communications Multi-band radios Bluetooth Antenna Modules Front-End Transmitter Modules Front-End Receiver Module Power Amplifier Modules Duplexer Switch Component Markets Filter Component Markets Voltage-Controlled Oscillator (VCO)

LTCC Modules Mobile Radio

RF Front End - A dual Band Mobile radio.

Average parts count for Dual Band radio

LTCC

LTCC

LTCC Modules Mobile Radio

Next generation

LTCC

Lower parts count and more advanced radio .. Tri Band!

LTCC

Typical Design Methodology Today

Initial simulation in HF design tool

Layout in a layout package

EM simulation

2-10 Iterations
Ok?

Design Rule Check

GDSII Stream Output

Final Layout

Fab

Verification Test

Challenges with the current Methodology

Serial process, no interactivity to quickly change and verify, inaccurate modeling Several disconnected tools in use
Simulation tools: ADS, MWO, etc Layout: PADS, Protel, Mentor, etc EM Simulation: HFSS, Sonnet, Emsight, etc DRC: Calibre, Dracula, etc

Multiple cycles are required through multiple tools Cycle times are long and numerous as a result

LTCC Ideal Methodology

Outlined below is the generic LTCC design methodology Thus far, most designers have not been able to realize a fully integrated process

Process Characterization

Library Implementation

Process Verification

Schematic Design

no yes

no

EM Analysis Critical Areas

Ok?

Interactive Layout/Simulation with Inets and ACE

yes

Ok?

Simulation

Design Rule Check

GDSII Stream Output

Fab

Verification Test

LTCC Modules
Outlined in the previous slide is a generic Ideal Flow The details of the flow will vary dependent on the types of LTCC circuits being designed.
LTCC Diplexer/Filter modules Embedded Passives Compact size is important Understanding the coupling between passives is important Extensive use of EM simulation LTCC FEM Some embedded passives Chips are both passive and active. Many via interconnects Coupling issues between interconnects and not so much the embedded passives. Probably the most complex module, because of multiple technologies used. LTCC Pa amp modules LTCC is used as module package for PA chip. Most of the passives are SMD parts. Interconnects for SMD parts in 3d using vias. Coupling issues only between vias and interconnect lines.

LTCC Modules
LTCC Diplexer/Filter modules
Embedded Passives Compact size is important Understanding the coupling between passives is important Extensive use of EM simulation
Lowk LTCC SMD and embedded Sprials

Mixed HighK all embedded Passives

LTCC Modules
LTCC FEM Some embedded passives Chips are both passive and active. Many via interconnects Coupling issues between interconnects and not so much the embedded passives. Probably the most complex module, because of multiple technologies used.

LTCC Modules
LTCC PA amp modules
LTCC is used as module package for PA chip. Most of the passives are SMD parts. Interconnects for SMD parts in 3d using vias. Coupling issues only between vias and interconnect lines.

ACETM : What is it? Traditional High Frequency Circuit Design

All transmission lines and coupled transmission lines are modeled by a schematic element. Creating the schematics can be cumbersome and time consuming.

MBEND90X$ ID=MS3 M=0

MLIN ID=TL5 W=20 um L=40 um

W1
2

W2
3

W3
4

W4
5

W5
6

GM6CLIN 7 ID=TL1 W1=20 um W2=20 um W3=20 um 8 W4=20 um W5=20 um W6=20 um Offs1=40 um 9 Offs2=40 um Offs3=40 um Offs4=40 um Offs5=40 um 10 Offs6=40 um CL1=1 CL2=1 CL3=1 11 CL4=1 CL5=1 CL6=1 L=40 um 12 Acc=1

GM5CLIN ID=TL2 W1=20 um W2=20 um W3=20 um W4=20 um W5=20 um Offs1=40 um Offs2=40 um Offs3=40 um Offs4=40 um Offs5=40 um CL1=1 CL2=1 CL3=1 CL4=1 CL5=1 L=40 um Acc=1

MLIN ID=TL7 W=20 um L=40 um MBEND90X$ ID=MS4 M=0

MLIN ID=TL6 W=20 um L=40 um

GM4CLIN ID=TL3 W1=20 um W2=20 um W3=20 um W4=20 um Offs1=40 um Offs2=40 um Offs3=40 um Offs4=40 um CL1=1 CL2=1 CL3=1 CL4=1 L=40 um Acc=1

MLIN ID=TL8 W=20 um L=40 um VIA ID=V2 D=20 um H=100 um T=2 um RHO=1

VIA ID=V3 D=20 um H=100 um T=2 um RHO=1

VIA ID=V4 D=20 um H=100 um T=2 um RHO=1

W1
2 7

W2
3 8

VIA ID=V5 D=20 um H=100 um T=2 um RHO=1

VIA ID=V6 D=20 um H=100 um T=2 um RHO=1

VIA ID=V7 D=20 um H=100 um T=2 um RHO=1

VIA ID=V8 D=20 um H=100 um T=2 um RHO=1

W3
4 9

W1
2 7 2

W1
6

VIA ID=V1 D=20 um H=100 um T=2 um RHO=1

W4
GM5CLIN ID=TL4 W1=20 um W2=20 um W3=20 um W4=20 um W5=20 um Offs1=40 um Offs2=40 um Offs3=40 um Offs4=40 um Offs5=40 um CL1=1 CL2=1 CL3=1 CL4=1 CL5=1 L=40 um Acc=1

10

W5

W2
3 8 3

W2
7

W3
4 9 4

W3
8

W4
5 10

W4

W5
MBEND90X$ ID=MS2 M=0

W6

MBEND90X$ ID=MS1 M=0

ACETM : What is it? Current Trends in High Frequency Design

Because of the complexity of these types of designs, and the push to create smaller circuits, Designers are beginning to forego this part of the design process and go straight to EM analysis.

ACETM : What is it?

ACE is AWRs response to overuse of EM simulation in the design process.
ACE software reclaims parametric design for the user by creating netlist-based representations of complex interconnects using the very same networks of parametric models designers themselves would use if they had the time and patience to do so, in a fraction of the time that it would take EM tools to create equivalent S-parameters. The speed, accuracy, and parametric nature of ACE software enable engineers to return to real design by exploring design alternatives and changes in seconds. Obviously, EM verification is still a necessary part of the flow, but the ACE tool enables engineers to design once again rather than analyze, even on many of the most challenging RF and MW designs.

ACETM : How is it done? ACE software is based on the proven digital and analog-mixed signal (AMS) technique of circuit extraction from physical layout where the equivalent model is a RLCK circuit as shown below.
L 1 SR =RL hm ID =1 O H R 1e-9 L= L 1 SR =RL hm ID =1 O H R 1e-9 L= L 1 SR =RL hm ID =1 O H R 1e-9 L= L 1 SR =RL hm ID =1 O H R 1e-9 L=
L 1 SR =RL hm ID =1 O -9 H R 1e L= L 1 SR =RL hm ID =1 O -9 H R 1e L=

CAP ID=RL1 C=0 F

L L1 SR =R Ohm H ID =1 -9 R 1e L= L L1 SR =R Ohm H ID =1 -9 R 1e L=

CAP ID=RL1 C=0 F

L 1 SR =RL hm ID =1 O -9 H R 1e L= L 1 SR =RL hm ID =1 O -9 H R 1e L=

L L1 SR =R Ohm H ID =1 -9 R 1e L= L L1 SR =R Ohm H ID =1 -9 R 1e L=

CAP ID=RL1 C=0 F

CAP ID=RL1 C=0 F

L L1 SR =R Ohm H ID =1 -9 R 1e L= L L1 SR =R Ohm H ID =1 -9 R 1e L=

CAP ID=RL1 C=0 F

L 1 SR =RL hm ID =1 O -9 H R 1e L= L 1 SR =RL hm ID =1 O -9 H R 1e L=

CAP ID=RL1 C=0 F

L L1 SR =R Ohm H ID =1 -9 R 1e L= L L1 SR =R Ohm H ID =1 -9 R 1e L=

CAP ID=RL1 C=0 F

L L1 SR =R Ohm H ID =1 -9 R 1e L= L L1 SR =R Ohm H ID =1 -9 R 1e L=

CAP ID=RL1 C=0 F

CAP ID=RL1 C=0 F

CAP ID=RL1 C=0 F

CAP ID=RL1 C=0 F

CAP ID=RL1 C=0 F

ACE: How is it done? ACE uses the same methodology but substitutes the RLCK models with Microwave Models.

ACETM: How is it done?

Uses AWR microwave models including em based models Driven by AWR iNets & EXTRACT flow Reuse structures with any EM Socket solver 100x-1000x faster than EM

EXT RACT ID=EX1 EM_Doc="EM Mercury" Name="Mercury" Simulator={Choose} X_Cell_Size=1 um Y_Cell_Size=1 um PortT ype=Default ST ACKUP="ST ACK3" Create_Enclosure=Yes Create_Shapes=Yes Extension=600 um PORT P=1 Z=50 Ohm MT RACE2 ID=X1 W=200 um L=2.064e4 um BT ype=1 M=1 RES ID=R2 R=1 Ohm

PORT P=2 Z=50 Ohm

RES ID=R1 R=1 Ohm

PORT P=15 Z=50 Ohm

PORT P=3 Z=50 Ohm

RES ID=R3 R=1 Ohm

RES ID=R4 R=1 Ohm

PORT P=9 Z=50 Ohm

PORT P=4 Z=50 Ohm

RES ID=R5 R=1 Ohm

RES ID=R6 R=1 Ohm

PORT P=10 Z=50 Ohm

PORT P=5 Z=50 Ohm

RES ID=R7 R=1 Ohm

RES ID=R8 R=1 Ohm

PORT P=11 Z=50 Ohm

PORT P=6 Z=50 Ohm

RES ID=R9 R=1 Ohm

RES ID=R10 R=1 Ohm

PORT P=12 Z=50 Ohm

PORT P=7 Z=50 Ohm

RES ID=R11 R=1 Ohm PORT P=8 Z=50 Ohm

RES ID=R12 R=1 Ohm

PORT P=13 Z=50 Ohm

PORT P=14 Z=50 Ohm MT RACE2 PORT ID=X2 P=16 W=200 um Z=50 Ohm L=1.439e4 um BT ype=1 M=1

ACETM: Models

Circuit models from geometric features

GMCnlin EM solver built into model MLIN closed-form distributed model MTEEX X model MCROSSX X model MBENDX X model Vias sparameter via library, VIA model, or equivalent circuit

Goes from Geometry to netlist of EM-based models

ACETM: LTCC LTCC Diplexer and MCM modules

Embedded passive likes spirals can be modeled with ACE and Inets

ACETM: LTCC
LTCC Diplexer and MCM modules
All interconnects between layer are automatically drawn using Inets. Simulation times are drastically reduced. This is probably the most complex use of the ACE technology.

On to the actual design

Schematic Design

no

yes

Ok?

Simulation

The initial design is done in schematic form using the library elements and ACE Simulation and optimization is performed to meet required performance specifications

Simulation Options include: Time Domain

HSPICE

Frequency Domain
Harmonic Balance: Linear
yes

Schematic Design

no

Ok?

Simulation

Electromagnetic
3D Planar EM Full 3D EM

Generating the LTCC layout

Schematic Design

no yes

no

Ok?

Interactive Layout/Simulation with parasitics

yes

Ok?

Simulation

Ideally the LTCC layout is interactively generated with simulation of verified library models and Inets and ACE. This provides a quick interactive design process that provides correct by construction LTCC designs

Looking at interactions
no yes

Critical Area EM Analysis

Ok?

Interactive Layout/Simulation with parasitics

Once the initial layout is complete, each individual model in the library only represents the performance of that element in isolation Therefore, critical areas of the design now go through an EM simulation to see the effect of element interactions
Different EM simulators are used depending upon the specific problem (MOM,FDTD, FEM, etc)

Adjustments are then made to the layout to compensate for component interactions

LTCC Module Example

Build PDK
Element Models Layer stacks 3D viewers Inets with LPF

Circuit Design with PDK

Parasitics Interconnection modelling use Ace and Inets EM verification using em socket Coupling Leakage

LTCC PDK Vertical Capacitors

Element model 3D view for visualisation Layer Stack for process

LTCC PDK Vertical Inductors

Element model 3D view for visualisation Layer Stack for process

LTCC Module Design Start with an Ideal design.

C1=0.8224 C2=3.987 L1=0.856 L2=6.939 C3=1.055

IND ID=L2 L=L2 nH

PORT P=1 Z=50 Ohm

CAP ID=C1 C=C1 pF

CAP ID=C3 C=C3 pF

CAP ID=C5 C=C1 pF

PORT P=2 Z=50 Ohm

CAP ID=C2 C=C2 pF

IND ID=L1 L=L1 nH

IND ID=L3 L=L1 nH

CAP ID=C4 C=C2 pF

LTCC Design Flow

Replace Ideal components with PDK components.
Layout view EM view

PORT P=1 Z=50 Ohm

VSPIRALN ID=MI1 N=2 W=3 mil L=17 mil LN=15 mil START_LYR=1 VIA_DIA=6 mil ACC=1

PORT P=1 Z=50 Ohm

IND ID=L1 L=6.45 nH

PORT P=2 Z=50 Ohm

PORT P=2 Z=50 Ohm

CAP ID=C1 C=0.111 pF

CAP ID=C2 C=0.164 pF

EM Extracted Modeling
EM simulations automatically generated from Layout EM simulations can be enabled/disabled from the schematic/layout
Allows maximum flexibility in simulation of complete cicuit User can EM only the critical elements to save time Using the Circuit simulator to control EM simulations allows efficient design

Parameter

Change auto update

EM Extract creates parameterized EM Sim

LTCC Design Flow Replace all ideal elements with equivalent PDK elements Inets and ACE connect components
Inets automatically connect components with correct vias

Extract using both EM and ACE

LTCC Design Flow

The EM Solver is used to guide the corrections to the circuit elements
Perturbation/Optimisation techniques Space mapping/Optimisation techniques
Filter start values S21
0

Parasitics, coupling, poor -20 initial element values and -40 effects interconnect
-60

DB(|S(2,1)|) EM Block Filter with tuning DB(|S(2,1)|) Ideal Filter DB(|S(2,1)|) Filter with initial values

-80

-100 1 2 Frequency (GHz) 3 4

EM Verification of Complete Circuit

Fine tuning may be needed at this point, but if the previous steps were done correctly it is minimal.
EM Analysis Verification
Diplexer Ideal vs Final EM
0

DB(|S(2,1)|) Diplexer_EM DB(|S(3,1)|) Diplexer_EM DB(|S(3,1)|) Diplexer

Fine Tune Critical Elements

no OK?

yes

-20

-40

DB(|S(1,1)|) Diplexer DB(|S(2,1)|) Diplexer DB(|S(1,1)|) Diplexer_EM

-60

-80 0.1 1.1 2.1 Frequency (GHz) 3.1 4

V10 Design Flow, Shape Modifiers and Data Sets.

This design flow uses Em Based modeling in the form of save data sets. Interconnects, Sprial inductors, and Capacitors are simulated initially using Axiem then used as a model for tuning.

V10 Design Flow, Shape Modifiers and Data Sets.

Shape Modifiers are used to parameterize em simulation.

V10 Design Flow, Shape Modifiers and Data Sets.

Swept Variables setup the parameterized model that is then used as a subcircuit in a schematic.

V10 Design Flow, Shape Modifiers and Data Sets.

Tuning is used to match the ideal simulation. Tune with em based modeling!!

V10 Design Flow, Shape Modifiers and Data Sets.

Each component is integrated then fine tuned to account for coupling issues between components. Shape modifiers, and swept variables are used for fine tuning. Two different subckts used to design the GSM band and DCS band.

GSM Circuit

DCS Circuit

V10 Design Flow, Shape Modifiers and Data Sets.

Each Sub circuit now is tuned to match Ideal Performance. Fine tuning is needed as coupling between components must be tuned out. Shape modifiers allows adjusting the em simulation while considering as much coupling as needed.

V10 Design Flow, Shape Modifiers and Data Sets.

Finally, the complete diplexer is simulated together

V10 Design Flow, Shape Modifiers and Data Sets.

Final verification is done by doing an em analysis of the complete diplexer combining DCS and GSM Sub Circuits. There is a problem found in the final simulation, one of the notches in the diplexer has changed.

Coupling effects change the notch in simulation

V10 Design Flow, Shape Modifiers and Data Sets.

Via wall used to isolate sub circuits and fix problem with coupling.

V10 Design Flow, Shape Modifiers and Data Sets.

Via wall has fixed the notch problem. Fine em tuning is then done to complete the design.

V10 Design Flow, Shape Modifiers and Data Sets.

Final Design including attachment to FR4 PCB, and thick metal.

Motorola LTCC Filter

Motorola LTCC Quad Band Receiver

AWR LTCC
PORT1 P=1 Z=50 Ohm Pwr=-30 dBm MTRACE ID=X14 W=24 mil L=229.3 mil BType=3 M=0

MTAPER ID=MT2 W1=W@1 mil W2=5 mil L=50 mil

1
SUBCKT ID=S1 NET="LNA900 IC"

2
MLSC ID=TL9 W=30 mil L=0 mil

MTAPER ID=MT1 W1=W@1 mil W2=5 mil L=70 mil

MTRACE ID=X13 W=120 mil L=25 mil BType=2 M=0

MTRACE ID=X5 W=24 mil L=39.08 mil BType=3 M=0

SSUB Er=5.7 B=29.6 mil T=0.0393701 mil Rho=1 Tand=0 Name=SSUB1

CHIPCAP ID=C1 C=1000 pF Q=779 FQ=0.03 GHz FR=0.23 GHz ALPH=-1 MTRACE ID=X3 W=24 mil L=141 mil BType=3 M=0

2
SUBCKT ID=S4 NET="Filter1"

MTRACE ID=X12 W=120 mil L=25 mil BType=2 M=0

MSUB Er=5.7 H=14.8 mil T=0.1 mil Rho=1.2 Tand=.0007 ErNom=5.7 Name=SUB1

MSTEP$ ID=TL8

MSTEP$ ID=TL3 SUBCKT ID=S3 NET="Mixer Section"

MTRACE ID=X11 W=15 mil L=15.63 mil BType=3 M=0

2
MTEE$ ID=TL7

MTRACE ID=X9 W=15 mil L=96.17 mil BType=3 M=0

MTRACE ID=X8 W=15 mil L=30.83 mil BType=3 M=0

MTRACE ID=X2 W=15 mil L=31.67 mil BType=3 M=0 MTRACE ID=X1 W=15 mil L=30.83 mil BType=3 M=0

5 1 2 4

MSTEP$ ID=TL4

MTRACE ID=X4 W=24 mil L=102.6 mil BType=3 M=0

SUBCKT ID=S2 NET="Layout of Lo Buffer amp"

3 1
MSTEP$ ID=TL6

2 3

1
PORTFNS P=3 Z=50 Ohm Freq=0.998 GHz PStart=-15 dBm PStop=5 dBm PStep=5 dB Tone=2

MTRACE ID=X10 W=24 mil L=12.34 mil BType=3 M=0

RES ID=R1 R=82.5 Ohm

MLSC ID=TL1 W=30 mil L=0 mil

MLSC ID=TL2 W=30 mil L=0 mil

MTRACE ID=X6 W=15 mil L=175 mil BType=3 M=0

MSTEP$ ID=TL5

MLIN ID=TL11 W=24 mil L=0 mil MLSC ID=TL10 W=30 mil L=0 mil MTRACE ID=X7 W=24 mil L=267.1 mil BType=3 PORT M=0 P=2 Z=50 Ohm