STUDENT ATTENDENCE MANAGEMENT SYSTEM

INDEX

CONTENTS

1. Abbreviations 2. Figures o!ations ". Abstra!t #. Intro$u!tion %. & o!' Diagra( ). & o!' Diagra( Des!ri*tion +. S!,e(ati! -. S!,e(ati! Des!ri*tion .. /ar$0are Co(*onents 11. Cir!uit Des!ri*tion 11. So2t0are !o(*onents E(be$$e$ 3C4 12. 5EI6 *ro!e$ure $es!ri*tion 1". Con! usion 7or8 S9no*sis 1#. &I&I6IOG:A;/Y

A&:E<ATIONS=

Mi!ro!ontro er=

S9(bo
ACC & ;S> S; D;T: D;6 D;/ ;1 ;1 ;2 ;" I; IE TMOD TCON T2CON T2MOD T/1 T61 T/1 T61 T/2 T62

Na(e
A!!u(u ator & register ;rogra( status 0or$ Sta!' *ointer Data *ointer 2 b9tes 6o0 b9te /ig, b9te ;ort1 ;ort1 ;ort2 ;ort" Interru*t *riorit9 !ontro Interru*t enab e !ontro Ti(er?!ounter (o$e !ontro Ti(er?!ounter !ontro Ti(er?!ounter 2 !ontro Ti(er?!ounter (o$e2 !ontro Ti(er?!ounter 1,ig, b9te Ti(er?!ounter 1 o0 b9te Ti(er?!ounter 1 ,ig, b9te Ti(er?!ounter 1 o0 b9te Ti(er?!ounter 2 ,ig, b9te Ti(er?!ounter 2 o0 b9te

SCON S&UF ;CON

Seria !ontro Seria $ata bu22er ;o0er !ontro

& o!' $iagra(=

;o0er su** 9 5e9*a$

Mi!ro !ontro er 6CD

6ED4S

&6OC5 DIAG:AM EX;6ANATION=

MIC:OCONT:O66E:= In this project work the micro-controller is plays major role. Micro-controllers were originally used as components in complicated process-control systems. However, because of their small size and low price, Micro-controllers are now also being used in regulators for individual control loops. In several areas Microcontrollers are now outperforming their analog counterparts and are cheaper as well.

!"# display the status of the project.

;O>E: SU;;6Y= $ variable regulated power supply is used to generate %& "! to microcontroller. 'sually you start with an unregulated power #supply ranging from ( volts to )* volts to make a % volt power supply+ we use a M,-.% voltage regulator I!.

/he power supplies are designed to convert high voltage $! mains electricity to a suitable low voltage supply for electronics circuits and other devices. $ power supply can by broken down into a series of blocks, each of which performs a particular function. $ d.c power supply which maintains the output voltage constant irrespective of a.c mains fluctuations or load variations is known as 01egulated ".! 2ower 3upply4 5or e6ample a %& regulated power supply system as shown below#

Trans2or(er= $ transformer is an electrical device which is used to convert electrical power from one

7lectrical circuit to another without change in fre8uency.

/ransformers convert $! electricity from one voltage to another with little loss of power. /ransformers work only with $! and this is one of the reasons why mains electricity is $!. 3tep-up transformers increase in output voltage, step-down transformers decrease in output voltage. Most power supplies use a step-down transformer to reduce the dangerously high mains voltage to a safer low voltage. /he input coil is called the primary and the output coil is called the secondary. /here is no electrical connection between the two coils+ instead they are linked by an alternating magnetic field created in the soft-iron core of the transformer. /he two lines in the middle of the circuit symbol represent the core. /ransformers waste very little power so the power out is 9almost: e8ual to the power in. ;ote that as voltage is stepped down current is stepped up. /he ratio of the number of turns on each coil, called the turn<s ratio, determines the ratio of the voltages. $ step-down transformer has a large number of turns on its primary 9input: coil which is connected to the high voltage mains supply, and a small number of turns on its secondary 9output: coil to give a low output voltage.

$n 7lectrical /ransformer /urns ratio = &p> &3 = ;p>;3 2ower ?ut= 2ower In &3 @ I3=&2 @ I2 &p = primary 9input: voltage ;p = number of turns on primary coil Ip = primary 9input: current

:ECTIFIE:=

$ circuit which is used to convert a.c to dc is known as 17!/I5I71. /he process of conversion a.c to d.c is called 0rectification4

TY;ES OF :ECTIFIE:S=

Half wave 1ectifier 5ull wave rectifier A. !entre tap full wave rectifier. ). Bridge type full bridge rectifier.

Co(*arison o2 re!ti2ier !ir!uits=

T9*e o2 :e!ti2ier ;ara(eter ;umber of diodes A 2I& of diodes &m )&m &m ) * /a 2 0ave Fu 0ave &ri$ge

".! output voltage

&m>

)&m>

)&m>

&dc,at no-load

..CA-&m

..DCD&m

..DCD&m

1ipple factor 1ipple 5re8uency 1ectification 7fficiency /ransformer 'tilization 5actor9/'5: 1M3 voltage &rms

A.)A

..*-)

..*-)

)f

)f

..*.D

..-A)

..-A)

..)-,

..D(C

..-A)

&m>)

&m>E)

&m>E)

Fu @0ave :e!ti2ier= 5rom the above comparison we came to know that full wave bridge rectifier as more advantages than the other two rectifiers. 3o, in our project we are using full wave bridge rectifier circuit. &ri$ge :e!ti2ier= $ bridge rectifier makes use of four diodes in a bridge arrangement to achieve full-wave rectification. /his is a widely used configuration, both with individual diodes wired as shown and with single component bridges where the diode bridge is wired internally. $ bridge rectifier makes use of four diodes in a bridge arrangement as shown in fig9a: to achieve full-wave rectification. /his is a widely used configuration, both with individual diodes wired as shown and with single component bridges where the diode bridge is wired internally.

5ig9$: O*eration= "uring positive half cycle of secondary, the diodes ") and "C are in forward biased while "A and "* are in reverse biased as shown in the fig9b:. /he current flow direction is shown in the fig 9b: with dotted arrows.

5ig9B: "uring negative half cycle of secondary voltage, the diodes "A and "* are in forward biased while ") and "C are in reverse biased as shown in the fig9c:. /he current flow direction is shown in the fig 9c: with dotted arrows.

5ig9!:

Fi ter=

$ 5ilter is a device which removes the a.c component of rectifier output but allows the d.c component to reach the load

Ca*a!itor Fi ter=
Fe have seen that the ripple content in the rectified output of half wave rectifier is 121A or that of full-wave or bridge rectifier or bridge rectifier is #-A such high percentages of ripples is not acceptable for most of the applications. 1ipples can be removed by one of the following methods of filtering.

7a8 $ capacitor, in parallel to the load, provides an easier by Gpass for the ripples voltage though

it due to low impedance. $t ripple fre8uency and leave the d.c.to appears the load.

7b8 $n inductor, in series with the load, prevents the passage of the ripple current 9due to high

impedance at ripple fre8uency: while allowing the d.c 9due to low resistance to d.c:

7!8 &arious combinations of capacitor and inductor, such as -section filter

section filter,

multiple section filter etc. which make use of both the properties mentioned in 9a: and 9b: above. /wo cases of capacitor filter, one applied on half wave rectifier and another with full wave rectifier.

5iltering is performed by a large value electrolytic capacitor connected across the "! supply to act as a reservoir, supplying current to the output when the varying "! voltage from the rectifier is falling. /he capacitor charges 8uickly near the peak of the varying "!, and then discharges as it supplies current to the output. 5iltering significantly increases the average "! voltage to almost the peak value 9A.* H 1M3 value:. /o calculate the value of capacitor9!:, ! = IJECJfJrJ1l Fhere, f = supply fre8uency, r = ripple factor, 1l = load resistance Note# In our circuit we are using A...K5 Hence large value of capacitor is placed to reduce ripples and to improve the "! component.

:egu ator=

&oltage regulator I!s is available with fi6ed 9typically %, A) and A%&: or variable output voltages. /he ma6imum current they can pass also rates them. ;egative voltage regulators are

available, mainly for use in dual supplies. Most regulators include some automatic protection from e6cessive current 9Loverload protectionL: and overheating 9Lthermal protectionL:. Many of the fi6ed voltage regulator I!s has C leads and look like power transistors, such as the ,-.% M%& A$ regulator shown on the right. /he M,-.% is simple to use. Nou simply connect the positive lead of your unregulated "! power supply 9anything from (&"! to )*&"!: to the Input pin, connect the negative lead to the !ommon pin and then when you turn on the power, you get a % volt supply from the output pin.

+-XX= /he Bay inear M,-@@ is integrated linear positive regulator with three terminals. /he M,-@@ offer several fi6ed output voltages making them useful in wide range of applications. Fhen used as a zener diode>resistor combination replacement, the M,-@@ usually results in an effective output impedance improvement of two orders of magnitude, lower 8uiescent current. /he M,-@@ is available in the /?-)%), /?-)). O /?-)DCpackages, Features=
P ?utput !urrent of A.%$

P ?utput &oltage /olerance of %Q P Internal thermal overload protection

P Internal 3hort-!ircuit imited P ;o 76ternal !omponent P ?utput &oltage %..&, D&, -&, (&, A.&, A)&, A%&, A-&, )*& P ?ffer in plastic /?-)%), /?-)). O /?-)DC P "irect 1eplacement for M,-@@

Mi!ro!ontro er=
Fe use $/-(!%A microcontroller. $s port . doesn<t have any resistance internally, to improve the driving capability of the port ., we need to connect pull up resistors. . (th pin of the microcontroller is reset pin, when the reset pin is A, microcontroller clears all registers and restarts the procedure ,A- and A( pins of the microcontroller are @/$ A,@/$ ) which are connected with the e6tenal crystal. !rystal is used to set the baud rate. Renerally AA..%(MHS crystal is connected .gives (D.. baud rate. ;o0er Su** 9= /he main aim of this power supply is to convert the )C.& $! into %& "! in order to give supply for the // or !M?3 devices. In this process we are using a step down transformer, a bridge rectifier, a smoothing circuit and the 123. $t the primary of the transformer we are giving the )C.& $! supply. /he secondary is connected to the opposite terminals of the Bridge rectifier as the input. 5rom other set of opposite terminals we are taking the output to the rectifier. /he bridge rectifier converts the $! coming from the secondary of the transformer into pulsating "!. /he output of this rectifier is further given to the smoother circuit which is capacitor in our project. /he smoothing circuit eliminates the ripples from the pulsating "! and gives the pure

"! to the 123 to get a constant output "! voltage. /he 123 regulates the voltage as per our re8uirement

5EY;AD=

Teypads and !"<s are the most widely used input>output devices of the -.%A, a basic understanding of them is essential. In this section, we first discuss keypad fundamentals, along with key press detection mechanisms. $t the lowest level, keypads are organized in a matri6 of rows ad columns. /he !2' accesses both rows ad columns through ports+ therefore with two --bit ports, a -6- matri6 of keys can be connected to a microprocessor. Fhen a key is pressed a row and a column make a contact+ otherwise, there is o connection between rows and columns. I n IBM 2! keypads, a single microcontroller9consisting of a microprocessor, 1$M and 721?M, and several ports all on a single chip: takes care of hardware ad software interfacing of the keypad. In such systems, it is the function of programs stored n the 721?M of the microcontroller to scan the keys continuously, identify which one has bee activated and preset it to the motherboard.

G:OUNDING :O>S AND :EADING T/E CO6UMNS#

/o detect a pressed key, the microcontroller grounds al rows by providing . to the output latch, and then it reads the columns. If the data read from the columns is "C - ". = AAAA, no key press is detected. However, if one of the column bits has a zero, this means that a key press has occurred. 5or e6ample, if "C - ". = AA.A, this means that a key in the "A column has been pressed. $fter a key press is detected, the microcontroller will go through the process of identifying the key. 3tarting with the top row, the microcontroller grounds it by providing a low to row ". only+ then it reads the columns. If the data read us all A<s no key in that row is activated ad the process is moved to the e6t row. It grounds the ne6t row, read the columns, ad checks for any zero. /his process continues until the row is identified. $fter identification of the row I which he key has been pressed, the ne6t task is to find out which column the pressed key belongs to. /his should be easy since the microcontroller knows at any time which row ad columns are beg accessed. T,ere are 2our (aBor stages=

A. /o make sure that the preceding key has been released, .<s are output to all rows at once, and the columns are read and checked repeatedly until all the columns are high. Fhen all columns are found to be high, the program waits for a short amount of time before it goes to the ne6t stage of waiting for a key to be pressed.

). /o see if any key is pressed, the columns are scanned over and over in an infinite loop until one of them has a . in it. 1emember that the output latches connected to rows still have their initial zeroes 9providing in stage A:, making them grounded. $fter the key press detection, it waits ). ms for the bounce and them key press detection was not an erroneous one due to a spike noise, and the first ).ms delay prevent prevents the same key press from being interpreted as a multiple key press. If after the ).ms delay the key is pressed, it goes to the ne6t stage to detect which row it belongs to+ otherwise, it goes back into the loop to detect a real key press.

C. /o detect which row the key press belongs to, it grounds one row at a time, reading the columns each time. If it finds that all columns are high, this means that the key press cannot belong to that row+ therefore it grounds the ne6t row ad continues until it finds the row the key press belongs to, it sets up the starting address for the look-up table holding the scan codes9 or the $3!II value: for that row and goes to the e6t stage to identify the key.

*. /o identify the key press, it rotates the columns bits, one bit at a time into the carry flag ad checks to see if it is low, upon finding the zero it pulls out the $3!II code for the key from the look-up table otherwise it increments the pointer to point to the ne6t element of the look-up table.

Renerally in this project we use keypad for the password to be entered by the election commissioner which is only known to him. 3o, that he can see the results of the elections which will be displayed on the !". If u entered this password more than three times the total system will be shut down. /he results will be displayed according to the party wise and which party had how many votes.

6CD 76iCui$ Cr9sta Dis* a98

i8uid crystal displays 9 !" s: have materials which combine the properties of both li8uids and crystals. 1ather than having a melting point, they have a temperature range within which the molecules are almost as mobile as they would be in a li8uid, but are grouped together in an ordered form similar to a crystal. $n !" consists of two glass panels, with the li8uid crystal material sand witched in between them. /he inner surface of the glass plates are coated with transparent electrodes which define the character, symbols or patterns to be displayed polymeric layers are present in between

the electrodes and the li8uid crystal, which makes the li8uid crystal molecules to maintain a defined orientation angle. ?ne each polarisers are pasted outside the two glass panels. /hese polarisers would rotate the light rays passing through them to a definite angle, in a particular direction Fhen the !" is in the off state, light rays are rotated by the two polarisers and the li8uid crystal, such that the light rays come out of the !" without any orientation, and hence the !" appears transparent. Fhen sufficient voltage is applied to the electrodes, the li8uid crystal molecules would be aligned in a specific direction. /he light rays passing through the !" would be rotated by the polarisers, which would result in activating > highlighting the desired characters. /he !"<s are lightweight with only a few millimeters thickness. 3ince the !"<s

consume less power, they are compatible with low power electronic circuits, and can be powered for long durations. /he !" s won<t generate light and so light is needed to read the display. By using !"<s have long life and a wide operating

backlighting, reading is possible in the dark. /he temperature range.

!hanging the display size or the layout size is relatively simple which makes the !"<s more customer friendly. /he !" s used e6clusively in watches, calculators and measuring instruments is the

simple seven-segment displays, having a limited amount of numeric data. /he recent advances in technology have resulted in better legibility, more information displaying capability and a wider temperature range. /hese have resulted in the telecommunications and entertainment electronics. /he applications. !" s being e6tensively used in !" s has even started replacing the

cathode ray tubes 9!1/s: used for the display of te6t and graphics, and also in small /&

6CD o*eration

In recent years the !" is finding widespread use replacing 7" s 9seven-segment 7" or other multi segment 7" s:. /his is due to the following reasons# A. /he declining prices of !" s. ). /he ability to display numbers, characters and graphics. /his is in contract to 7" s, which are limited to numbers and a few characters. C. Incorporation of a refreshing controller into the !", there by by the !2' to keep displaying the data. *. 7ase of programming for characters and graphics. relieving the !2' of the task of refreshing the !". In the contrast, the 7" must be refreshed

6CD *in $es!ri*tion /he !" discussed in this section has A* pins. /he function of each pin is given in table.

TA&6E 1= ;in $es!ri*tion 2or 6CD= ;in A ) C s9(bo &ss &cc &77 I>? ---"escription Rround M%& power supply 2ower supply to

control contrast * 13 I 13=. to select

command register 13=A to select data register % 1>F I 1>F=. for write 1>F=A for read D 7 I>? 7nable

, ( A. AA A) AC A*

"B. "BA "B) "BC "B* "B% "BD "B,

I>? I>? I>? I>? I>? I>? I>? I>?

/he --bit data bus /he --bit data bus /he --bit data bus /he --bit data bus /he --bit data bus /he --bit data bus /he --bit data bus /he --bit data bus

TA&6E 2= 6CD Co((an$ Co$es !ode 9he6: !ommand to !" Instruction 1egister

A ) * D % , $ ! 7 5

!lear display screen 1eturn home "ecrement cursor Increment cursor 3hift display right 3hift display left "isplay off, cursor off "isplay off, cursor on "isplay on, cursor off "isplay on, cursor on "isplay on, cursor blinking

A. A* AA! -. !. C-

3hift cursor position to left 3hift cursor position to right 3hift the entire display to the left 3hift the entire display to the right 5orce cursor to beginning of Ast line 5orce cursor to beginning of )nd line ) lines and %6, matri6

Uses= /he !"s used e6clusively in watches, calculators and measuring instruments are the

simple seven-segment displays, having a limited amount of numeric data. /he recent advances in technology have resulted in better legibility, more information displaying capability and a wider temperature range. /hese have resulted in the telecommunications and entertainment electronics. /he applications. !"s being e6tensively used in !"s have even started replacing the

cathode ray tubes 9!1/s: used for the display of te6t and graphics, and also in small /&

6CD INTE:FACING

Sen$ing !o((an$s an$ $ata to 6CDs 0it, a ti(e $e a9=

/o send any command from table ) to the !", make pin 13=.. 5or data, make 13=A./hen place a high to low pulse on the 7 pin to enable the internal latch of the !".

/A:D>A:E COM;ONENTS MIC:OCONT:O66E:

Features
P !ompatible with M!3-%AU 2roducts P *T Bytes of In-3ystem 2rogrammable 9I32: 5lash Memory P *..& to %.%& ?perating 1ange P A)- 6 --bit Internal 1$M P C) 2rogrammable I>? ines P /wo AD-bit /imer>!ounters P 3i6 Interrupt 3ources P 5ull "uple6 '$1/ 3erial !hannel P ow-power Idle and 2ower-down Modes

Des!ri*tion=
/he $/-(3%A is a low-power, high-performance !M?3 --bit microcontroller with *T bytes of in-system programmable 5lash memory. /he device is manufactured using $tmel<s high-density nonvolatile memory technology and is compatible with the industry- standard -.!%A instruction set and pinout. /he on-chip 5lash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile --bit !2' with insystem programmable 5lash on a monolithic chip, the $tmel $/-(3%A is a powerful microcontroller which provides a highly-fle6ible and cost-effective solution to many embedded control applications.

T,e AT-.S%1 *rovi$es t,e 2o o0ing stan$ar$ 2eatures=

*T bytes of 5lash, A)- bytes of 1$M, C) I>? lines, Fatchdog timer, two data pointers, two ADbit timer>counters, a five vector two-level interrupt architecture, a full duple6 serial port, on-chip oscillator, and clock circuitry. In addition, the $/-(3%A is designed with static logic for operation down to zero fre8uency and supports two software selectable power saving modes. /he Idle Mode stops the !2' while allowing the 1$M, timer>counters, serial port, and interrupt system to continue functioning. /he 2ower-down mode saves the 1$M contents but freezes the oscillator, disabling all other chip functions until the ne6t e6ternal interrupt or hardware reset.

;in Des!ri*tion
<CC 3upply voltage. GND Rround. ;ort 1 2ort . is an --bit open drain bidirectional I>? port. $s an output port, each pin can sink eight // inputs. Fhen As are written to port . pins, the pins can be used as high-impedance inputs. 2ort . can also be configured to be the multiple6ed low-order address>data bus during accesses to e6ternal program and data memory. In this mode, 2. has internal pull-ups. 2ort . also receives the code bytes during 5lash programming and outputs the code bytes during program verification. EDterna *u @u*s are reCuire$ $uring *rogra( veri2i!ation.

;ort 1 2ort A is an --bit bidirectional I>? port with internal pull-ups. /he 2ort A output buffers can sink>source four // inputs. Fhen As are written to 2ort A pins, they are pulled high by the internal pull-ups and can be used as inputs. $s inputs, 2ort A pins that are e6ternally being pulled low will source current 9II : because of the internal pull-ups. 2ort A also receives the low-order address bytes during 5lash programming and verification.

;ort 2 2ort ) is an --bit bidirectional I>? port with internal pull-ups. /he 2ort ) output buffers cansink>source four // inputs. Fhen As are written to 2ort ) pins, they are pulled high by the internal pull-ups and can be used as inputs. $s inputs, 2ort ) pins that are e6ternally being pulled low will source current 9II : because of the internal pull-ups. 2ort ) emits the high-order address byte during fetches from e6ternal program memory and during accesses to e6ternal data memory that use AD-bit addresses 9M?&@ V "2/1:. In this application, 2ort ) uses strong internal pullups when emitting As. "uring accesses to e6ternal data memory that use --bit addresses 9M?&@ V 1I:, 2ort ) emits the contents of the 2) 3pecial 5unction 1egister. 2ort ) also receives the high-order address bits and some control signals during 5lash programming and verification. ;ort " 2ort C is an --bit bidirectional I>? port with internal pull-ups. /he 2ort C output buffers can sink>source four // inputs. Fhen As are written to 2ort C pins, they are pulled high by the internal pull-ups and can be used as inputs. $s inputs, 2ort C pins that are e6ternally being pulled low will source current 9II : because of the pull-ups. 2ort C receives some control signals for 5lash programming and verification. 2ort C also serves the functions of various special features of the $/-(3%A, as shown in the following table.

:ST 1eset input. $ high on this pin for two machine cycles while the oscillator is running resets the device. /his pin drives High for (- oscillator periods after the Fatchdog times out. /he "I31/? bit in 351 $'@1 9address -7H: can be used to disable this feature. In the default state of bit "I31/?, the 1737/ HIRH out feature is enabled. A6E?;:OG $ddress atch 7nable 9$ 7: is an output pulse for latching the low byte of the address during accesses to e6ternal memory. /his pin is also the program pulse input 921?R: during 5lash programming. In normal operation, $ 7 is emitted at a constant rate of A>D the oscillator fre8uency and may be used for e6ternal timing or clocking purposes. ;ote, however, that one $ 7 pulse is skipped during each access to e6ternal data memory. If desired, $ 7 operation can be disabled by setting bit . of 351 location -7H. Fith the bit set, $ 7 is active only during a M?&@ or M?&! instruction. ?therwise, the pin is weakly pulled high. 3etting the $ 7-disable bit has no effect if the microcontroller is in e6ternal e6ecution mode. ;SEN 2rogram 3tore 7nable 9237;: is the read strobe to e6ternal program memory. Fhen the $/-(3%A is e6ecuting code from e6ternal program memory, 237; is activated twice each machine cycle, e6cept that two 237; activations are skipped during each access to e6ternal data memory. EA?<;; 76ternal $ccess 7nable. 7$ must be strapped to R;" in order to enable the device to fetch code from e6ternal program memory locations starting at ....H up to 5555H. ;ote, however, that if lock bit A is programmed, 7$ will be internally latched on reset. 7$ should be

strapped to &!! for internal program e6ecutions. /his pin also receives the A)-volt programming enable voltage 9&22: during 5lash programming. XTA61 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTA62 ?utput from the inverting oscillator amplifier

S*e!ia Fun!tion :egisters $ map of the on-chip memory area called the 3pecial 5unction 1egister 9351: space is shown in /able A. ;ote that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. 1ead accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

'ser software should not write As to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be .. Interru*t :egisters= /he individual interrupt enable bits are in the I7 register. /wo priorities can be set for each of the five interrupt sources in the I2 register.

Dua Data ;ointer :egisters= /o facilitate accessing both internal and e6ternal data memory, two banks of AD-bit "ata 2ointer 1egisters are provided# "2. at 351 address locations -)H-CH and "2A at -*H--%H. Bit "23 = . in 351 $'@1A selects "2. and "23 = A selects "2A. /he user should always initialize the "23 bit to the appropriate value before accessing the respective "ata 2ointer 1egister.

;o0er o22 F ag= /he 2ower ?ff 5lag 92?5: is located at bit * 92!?;.*: in the 2!?; 351. 2?5 is set to 0A4 during power up. It can be set and rest under software control and is not affected by reset.

Me(or9 OrganiEation M!3-%A devices have a separate address space for 2rogram and "ata Memory. 'p to D*T bytes each of e6ternal 2rogram and "ata Memory can be addressed. ;rogra( Me(or9 If the 7$ pin is connected to R;", all program fetches are directed to e6ternal memory. ?n the $/-(3%A, if 7$ is connected to &!!, program fetches to addresses ....H through 555H are directed to internal memory and fetches to addresses A...H through 5555H are directed to e6ternal memory. Data Me(or9 /he $/-(3%A implements A)- bytes of on-chip 1$M. /he A)- bytes are accessible via direct and indirect addressing modes. 3tack operations are e6amples of indirect addressing, so the A)- bytes of data 1$M are available as stack space. >at!,$og Ti(er 7One@ti(e Enab e$ 0it, :eset@out8 /he F"/ is intended as a recovery method in situations where the !2' may be subjected to software upsets. /he F"/ consists of a A*-bit counter and the Fatchdog /imer 1eset 9F"/13/: 351. /he F"/ is defaulted to disable from e6iting reset. /o enable the F"/, a user must write .A7H and .7AH in se8uence to the F"/13/ register 9351 location .$DH:.

Fhen the F"/ is enabled, it will increment every machine cycle while the oscillator is running. /he F"/ timeout period is dependent on the e6ternal clock fre8uency. /here is no way to disable the F"/ e6cept through reset 9either hardware reset or F"/ overflow reset:. Fhen F"/ overflows, it will drive an output 1737/ HIRH pulse at the 13/ pin. Using t,e >DT /o enable the F"/, a user must write .A7H and .7AH in se8uence to the "/13/ register 9351 location .$DH:. Fhen the F"/ is enabled, the user needs to service it by writing .A7H and .7AH to F"/13/ to avoid a F"/ overflow. /he A*-bit counter overflows when it reaches ADC-C 9C555H:, and this will reset the device. Fhen the F"/ is enabled, it will increment every machine cycle while the oscillator is running. /his means the user must reset the F"/ at least every ADC-C machine cycles. /o reset the F"/ the user must write .A7H and .7AH to F"/13/. F"/13/ is a write-only register. /he F"/ counter cannot be read or written. Fhen F"/ overflows, it will generate an output 1737/ pulse at the 13/ pin. /he 1737/ pulse duration is (-6/?3!, where /?3!=A>5?3!. /o make the best use of the F"/, it should be serviced in those sections of code that will periodically be e6ecuted within the time re8uired to prevent a F"/ reset. >DT During ;o0er@$o0n an$ I$ e In 2ower-down mode the oscillator stops, which means the F"/ also stops. Fhile in 2owerdown mode, the user does not need to service the F"/. /here are two methods of e6iting 2ower-down mode# by a hardware reset or via a level-activated e6ternal interrupt, which is enabled prior to entering 2ower-down mode. Fhen 2ower-down is e6ited with hardware reset, servicing the F"/ should occur as it normally does whenever the $/-(3%A is reset. 76iting 2ower-down with an interrupt is significantly different. /he interrupt is held low long enough for the oscillator to stabilize. Fhen the interrupt is brought high, the interrupt is serviced. /o prevent the F"/ from resetting the device while the interrupt pin is held low, the F"/ is not started until the interrupt is pulled high. It is suggested that the F"/ be reset during the interrupt service for the interrupt used to e6it 2ower-down mode. /o ensure that the F"/ does not overflow within a few states of e6iting 2ower-down, it is best to reset the F"/ just before entering 2ower-down

mode. Before going into the I" 7 mode, the F"I" 7 bit in 351 $'@1 is used to determine whether the F"/ continues to count if enabled. /he F"/ keeps counting during I" 7 9F"I" 7 bit = .: as the default state. /o prevent the F"/ from resetting the $/-(3%A while in I" 7 mode, the user should always set up a timer that will periodically e6it I" 7, service the F"/, and reenter I" 7 mode. Fith F"I" 7 bit enabled, the F"/ will stop to count in I" 7 mode and resumes the count upon e6it from I" 7. UA:T /he '$1/ in the $/-(3%A operates the same way as the '$1/ in the $/-(!%A. Ti(er 1 an$ 1 /imer . and /imer A in the $/-(3%A operate the same way as /imer . and /imer A in the $/-(!%A. Interru*ts /he $/-(3%A has a total of five interrupt vectors# two e6ternal interrupts 9I;/. and I;/A:, two timer interrupts 9/imers . and A:, and the serial port interrupt. /hese interrupts are all shown in 5igure A. 7ach of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in 3pecial 5unction 1egister I7. I7 also contains a global disable bit, 7$, which disables all interrupts at once. ;ote that /able * shows that bit position I7.D is unimplemented. In the $/-(3%A, bit position I7.% is also unimplemented. 'ser software should not write As to these bit positions, since they may be used in future $/-( products. /he /imer . and /imer A flags, /5. and /5A, are set at 3%2) of the cycle in which the timers overflow. /he values are then polled by the circuitry in the ne6t cycle.

Os!i ator C,ara!teristi!s @/$ A and @/$ ) are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in 5igure ). 7ither a 8uartz crystal or ceramic resonator may be used. /o drive the device from an e6ternal clock source, @/$ ) should be left unconnected while @/$ A is driven, as shown in 5igure C. /here are no

re8uirements on the duty cycle of the e6ternal clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and ma6imum voltage high and low time specifications must be observed.

I$ e Mo$e In idle mode, the !2' puts itself to sleep while all the on-chip peripherals remain active. /he mode is invoked by software. /he content of the on-chip 1$M and all the special function registers remain unchanged during this mode. /he idle mode can be terminated by any enabled interrupt or by a hardware reset. ;ote that when idle mode is terminated by a hardware reset, the device normally resumes program e6ecution from where it left off, up to two machine cycles before the internal reset algorithm takes control. ?n-chip hardware inhibits access to internal 1$M in this event, but access to the port pins is not inhibited. /o eliminate the possibility of an une6pected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to e6ternal memory.

;o0er@$o0n Mo$e In the 2ower-down mode, the oscillator is stopped, and the instruction that invokes 2owerdown is the last instruction e6ecuted. /he on-chip 1$M and 3pecial 5unction 1egisters retain their values until the 2ower-down mode is terminated. 76it from 2ower-down mode can be initiated either by a hardware reset or by activation of an enabled e6ternal interrupt into I;/. or I;/A. 1eset redefines the 351s but does not change the on-chip 1$M. /he reset should not be activated before &!! is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

;rogra( Me(or9 6o!' &its /he $/-(3%A has three lock bits that can be left unprogrammed 9': or can be programmed 92: to obtain the additional features listed in the following table.

Fhen lock bit A is programmed, the logic level at the 7$ pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. /he latched value of 7$ must agree with the current logic level at that pin in order for the device to function properly.

;rogra((ing t,e F as, F ;ara e Mo$e /he $/-(3%A is shipped with the on-chip 5lash memory array ready to be programmed. /he programming interface needs a high-voltage 9A)-volt: program enable signal and is compatible with conventional third-party 5lash or 721?M programmers. /he $/-(3%A code memory array is programmed byte-by-byte. ;rogra((ing A gorit,(= Before programming the $/-(3%A, the address, data, and control signals should be set up according to the 5lash programming mode table and 5igures AC and A*. /o program the $/-(3%A, take the following steps# A. Input the desired memory location on the address lines. ). Input the appropriate data byte on the data lines. C. $ctivate the correct combination of control signals. *. 1aise 7$>&22 to A)&. %. 2ulse $ 7>21?R once to program a byte in the 5lash array or the lock bits. /he bytewrite cycle is self-timed and typically takes no more than %. Ws. 1epeat steps A through %, changing the address and data for the entire array or until the end of the object file is reached. Data ;o ing= /he $/-(3%A features "ata 2olling to indicate the end of a byte write cycle. "uring a write cycle, an attempted read of the last byte written will result in the complement of the written data on 2..,. ?nce the write cycle has been completed, true data is valid on all outputs, and the ne6t cycle may begin. "ata 2olling may begin any time after a write cycle has been initiated. :ea$9?&us9= /he progress of byte programming can also be monitored by the 1"N>B3N output signal. 2C.. is pulled low after $ 7 goes high during programming to indicate B'3N. 2C.. is pulled high again when programming is done to indicate 17$"N. ;rogra( <eri29= If lock bits BA and B) have not been programmed, the programmed code data can be read back via the address and data lines for verification. /he status of the individual lock bits can be verified directly by reading them back.

:ea$ing t,e Signature &9tes= /he signature bytes are read by the same procedure as a normal verification of locations ...H, A..H, and )..H, e6cept that 2C.D and 2C., must be pulled to a logic low. /he values returned are as follows. 9...H: = A7H indicates manufactured by $tmel 9A..H: = %AH indicates -(3%A 9)..H: = .DH C,i* Erase= In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing $ 7>21?R low for a duration of ).. ns %.. ns. In the serial programming mode, a chip erase operation is initiated by issuing the !hip 7rase instruction. In this mode, chip erase is self-timed and takes about %.. ms. "uring chip erase, a serial read from any address location will return ..H at the data output. ;rogra((ing t,e F as, F Seria Mo$e /he !ode memory array can be programmed using the serial I32 interface while 13/ is pulled to &!!. /he serial interface consists of pins 3!T, M?3I 9input: and MI3? 9output:. $fter 13/ is set high, the 2rogramming 7nable instruction needs to be e6ecuted first before other operations can be e6ecuted. Before a reprogramming se8uence can occur, a !hip 7rase operation is re8uired. /he !hip 7rase operation turns the content of every memory location in the !ode array into 55H. 7ither an e6ternal system clock can be supplied at pin @/$ A or a crystal needs to be connected across pins @/$ A and @/$ ). /he ma6imum serial clock 93!T: fre8uency should be less than A>AD of the crystal fre8uency. Fith a CC MHz oscillator clock, the ma6imum 3!T fre8uency is ) MHz. Seria ;rogra((ing A gorit,( /o program and verify the $/-(3%A in the serial programming mode, the following se8uence is recommended# A. 2ower-up se8uence#

$pply power between &!! and R;" pins. 3et 13/ pin to 0H4. If a crystal is not connected across pins @/$ A and @/$ ), apply a C MHz to CC MHz clock to @/$ A pin and wait for at least A. milliseconds. ). 7nable serial programming by sending the 2rogramming 7nable serial instruction to pin M?3I>2A.%. /he fre8uency of the shift clock supplied at pin 3!T>2A., needs to be less than the !2' clock at @/$ A "ivided by AD. C. /he !ode array is programmed one byte at a time in either the Byte or 2age mode. /he write cycle is self-timed and typically takes less than ..% ms at %&. *. $ny memory location can be verified by using the 1ead instruction that returns the content at the selected address at serial output MI3?>2A.D. %. $t the end of a programming session, 13/ can be set low to commence normal device operation.

2ower-off se8uence 9if needed:# 3et @/$ A to 0 4 9if a crystal is not used:. 3et 13/ to 0 4. /urn &!! power off. Data ;o ing= /he "ata 2olling feature is also available in the serial mode. In this mode, during a write cycle an attempted read of the last byte written will result in the complement of the M3B of the serial output byte on MI3?. Seria ;rogra((ing Instru!tion Set /he Instruction 3et for 3erial 2rogramming follows a *-byte protocol and is shown in /able - on page A-.

;rogra((ing Inter2a!e F ;ara e Mo$e 7very code byte in the 5lash array can be programmed by using the appropriate combination of control signals. /he write operation cycle is self-timed and once initiated, will automatically time itself to !ompletion. $ll major programming vendors offer worldwide support for the $tmel microcontroller series. 2lease contact your local programming vendor for the appropriate software revision.

$fter 1eset signal is high, 3!T should be low for at least D* system clocks before it goes high to clock in the enable data bytes. ;o pulsing of 1eset signal is necessary. 3!T should be no faster than A>AD of the system clock at @/$ A. 5or 2age 1ead>Frite, the data always starts from byte . to )%%. $fter the command byte and upper address byte are latched, each byte thereafter is treated as data until all )%D bytes are shifted in>out. /hen the ne6t instruction will be ready to be decoded.

J;?/I!7# 3tresses beyond those listed under 0$bsolute Ma6imum 1atings4 may cause permanent damage to the device. /his is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. 76posure to absolute ma6imum rating conditions for e6tended periods may affect device reliability.

Cir!uit Des!ri*tion=

In this project we re8uired operating voltage for Microcontroller -(!%A is %&. Hence the %& ".!. power supply is needed for the I!<s. /his regulated %& is generated by stepping down the voltage from )C.& to A-& now the step downed a.c voltage is being rectified by the Bridge 1ectifier using A;*.., diodes. /he rectified a.c voltage is now filtered using a X!< filter. ;ow the rectified, filtered ".!. voltage is fed to the &oltage 1egulator. /his voltage regulator provides>allows us to have a 1egulated constant &oltage which is of M%&. /he rectified+ filtered and regulated voltage is again filtered for ripples using an electrolytic capacitor A..W5. ;ow the output from this section is fed to *.th pin of -(!%A microcontroller to supply operating voltage. /he microcontroller -(!%A with 2ull up resistors at 2ort. and crystal oscillator of AA..%() MHz crystal in conjunction with couple of C.-CCpf capacitors is placed at A- th O A(th pins of -(!%A to make it work 9e6ecute: properly.

So2t0are

So2t0are !o(*onents

About 5ei

1. 2.

!lick on the Teil u &ision Icon on "esktop /he following fig will appear

". #.

!lick on the 2roject menu from the title bar /hen !lick on ;ew 2roject

%.

3ave the 2roject by typing suitable project name with no e6tension in u r own folder sited in either !#Y or "#Y

). +.

/hen !lick on 3ave button above. 3elect the component for u r project. i.e. $tmelZZ

-.

!lick on the M 3ymbol beside of $tmel

..

3elect $/-(!%A as shown below

11. 11.

/hen !lick on 0?T4 /he 5ollowing fig will appear

12. 1". 1#.

/hen !lick either N73 or ;?ZZZmostly 0;?4 ;ow your project is ready to '37 ;ow double click on the /argetA, you would get another option 03ource group A4 as shown in ne6t page.

1%.

!lick on the file option from menu bar and select 0new4

1).

/he ne6t screen will be as shown in ne6t page, and just ma6imize it by double clicking on its blue boarder.

1+. 1-.

;ow start writing program in either in 0!4 or 0$3M4 5or a program written in $ssembly, then save it with e6tension 0. asm4 and for 0!4 based program save it with e6tension 0 .!4

1..

;ow right click on 3ource group A and click on 0A$$ 2i es to Grou* Sour!e4

21.

;ow you will get another window, on which by default 0!4 files will appear.

21. 22. 2".

;ow select as per your file e6tension given while saving the file !lick only one time on option 0ADD4 ;ow 2ress function key 5, to compile. $ny error will appear if so happen.

2#. 2%.

If the file contains no error, then press !ontrolM5% simultaneously. /he new window is as follows

2).

/hen !lick 0?T4

2+.

;ow !lick on the 2eripherals from menu bar, and check your re8uired port as shown in fig below

2-.

"rag the port a side and click in the program file.

2.. "1.

;ow keep 2ressing function key 05AA4 slowly and observe. Nou are running your program successfully

CONC6UTION

/he project 0Stu$ent atten$an!e (anage(ent s9ste(G has been successfully designed and tested.

It has been developed by integrating features of all the hardware components used. 2resence of every module has been reasoned out and placed carefully thus contributing to the best working of the unit. 3econdly, using highly advanced I!<s and with the help of growing technology the project has been successfully implemented. 5inally we conclude that 0Stu$ent atten$an!e (anage(ent s9ste(4 is an emerging field and there is a huge scope for research and development.

&ib iogra*,9

T,e -1%1 Mi!ro !ontro er an$ E(be$$e$ S9ste(s @Muhammad $li Mazidi [anice Rillispie Mazidi T,e -1%1 Mi!ro !ontro er Ar!,ite!tureH ;rogra((ing I A** i!ations -Tenneth [.$yala Fun$a(enta s O2 Mi!ro *ro!essors an$ Mi!ro !o(*uters -B.1am Mi!ro *ro!essor Ar!,ite!tureH ;rogra((ing I A** i!ations -1amesh 3. Raonka E e!troni! Co(*onents @".&. 2rasad Mobi e Te e Co((uni!ations @ >i ia( C.Y. 6ee