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EC2 Solution Mid semester Test ( EEEZG512 Embedded Systems )

1. No the value will be logically incorrect. Once a port is used as output before using the port as
input the port pins should be driven to a logical High.

2. Yes 8051 architecture follows register banking. Register banking help to improve performance
during a subroutine execution as context saving can be reduced. In Register windowing there is
sharing of some registers among the register banks. While executing subroutines parameter s can
be passed easily.

3. In-System Programming means that the device can be programmed in the circuit by
using an utility such as the ULINK USB-JTAG Adapter.
In-Application Programming means that the application itself can re-program the on-
chip Flash ROM.
4. Idle Mode of operation. Peripherals can continue to work in idle mode

5. h=98% ;
Tav=htcache+(1-h)tmain

6. In case of IRQ multiple peripherals can raise IRQ so if more than one device has raised an
interrupt, the INT unit has to verify h/w and s/w mask status, check priorities and then raise the IRQ
with the address of appropriate interrupt meanwhile the other interrupt has to wait. In case of FIQ
though the increase in the latency is negligible still masking and using hardware priorities to decide
source of FIQ will add to latency.

7. Counts for rollover=(FFFF-FFF2)+1 =14(decimal)

T= 14*1us *2 = 28us
With overhead =2* 28*2us =56us

8. The SWI is used for calls to the operating system and is oftern called a supervisor call. It puts
the processor into supervisor mode and begin execution from address 0x08
Entry : Save addredd of instruction after SWI to r14
Save CPSR in SPSR
Enter supervisor mode ,disable IRQ but not FIQ , cpsr[4:0]=10011(binary) , cpsr[7]=1
Set PC=08(hex) and begin executing instructions there

Exit : Copy r14 to PC
RESTORE CPSR from SPSR

9. Code 2 is faster .The load cost is reduced by using multiple register loads and branch cost is
reduced by loop unrolling.

10. Reduces code density and improves performance. Conditional execution reduces the number of
branches and hence reduce the number of pipeline flushes thus improving the pipeline
performance.
SUBS R3,R1,R2 ; R3=R1-R2
MOVEQ R9,R1 ; If R1 and R2 ARE EQUAL mov R1 to R9
MOVHI R10,R1 ; IF R1>R2 ,C=1, R1 moved tp R10
MOV R10,R2 ; OTHERWISE MOVE r2 TO R10

11. It helps quick context saving in stacks. When ever a highpriority interrupt needs to be
serviced it can be disadvantageous. ARM processor finishes execution of the current ISR before
accepting new. So will have to wait for a longer period.

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