Working with Altera

Devices
and Place and Route Tools

Version (v2.0) Feb 29, 2008 1
Altium Designers FPGA development environment can be used to capture, synthesize,
place and route and download a digital system design into an FPGA. Place and route, the
process of implementing the design on the target silicon, requires an intimate
understanding of the functionality and architecture of the device, a task best performed by
software tools provided by the device vendor. The vendor software is operated by the
Altium Designer environment, which automatically manages all project and file handling
aspects required to generate the FPGA program file. There is a large degree of user-
control over this process, which this application note details.

Introduction
Altera tools are integrated and accessed in the Altium Designer environment through the Devices view (View Devices View).
This view allows step-by-step control over the entire FPGA design process, enabling you to program and debug your system
design on the FPGA.
For information on using the Devices view to process the design, see the Processing the Captured FPGA Design
application note.
This application note makes reference to Alteras Introduction to Quartus II Manual. Users wishing to change any of the
default settings should refer to this document for details.
If you are not familiar with the Altera tools it is recommended that you start designing with the built-in default settings.
Supported Architecture
The system supports the latest Altera FPGA technology and includes both FPGA and PCB schematic library support. The
following table summarizes the supported device technologies and the available library support, at the time of publication of this
document.
Device
Technology
Architecture-
Independent Library
Support
Architecture-Dependent
FPGA Library Name
(*.IntLib)
Associated PCB
Library Name
(*.IntLib)
Cyclone Yes Altera FPGA Altera Cyclone
Cyclone II Yes Altera FPGA Altera Cyclone II
MAX II Yes Altera FPGA Altera MAX II
Max3000A Yes Altera FPGA Altera MAX 3000A
Max7000AE Yes Altera FPGA Altera MAX 7000AE
Max7000B Yes Altera FPGA Altera MAX 7000B
Max7000S Yes Altera FPGA Altera MAX 7000S
Stratix Yes Altera FPGA Altera Stratix
Stratix II Yes Altera FPGA Altera Stratix II
Stratix GX Yes Altera FPGA Altera Stratix GX
Summary
This application note
provides an advanced
Altera designer with
information on how to
control the Altera place
and route software
options and properties,
and also includes
information on libraries.
AP0113 Working with Altera Devices and Place and Route Tools

Version (v2.0) Feb 29, 2008 2
FPGA Architecture-Independent Library
To maintain device independence, the system includes a large library of typical generic design components, the FPGA Generic
Library. This integrated library can be found in the \Library\FPGA folder of the installation.
For complete documentation with respect to the FPGA Generic Library, refer to the FPGA Generic Library Guide.
FPGA Architecture-Dependent Library
If device independence is not required the system also includes the standard Altera FPGA primitive library, in the
\Library\Altera folder of the installation.
This integrated library includes the library-mapping file (LMF). This is automatically linked into the Build process and maps the
generated design files with the Altera placement and routing tools.
MegaWizard Plug-in Component Support
Specialized cores that are available from the Altera MegaWizard plug-in manager can be used in your FPGA design. Once you
have generated the core, you link the generated VHDL file to a schematic component and place this component in your FPGA
design.
To create a component symbol from the VHDL file, open it in the software and select Design Create Schematic Part From
File from the menus. To reference the VHDL file from this component symbol, add the parameter
CoreFile=VHDL_Filename.vhd to it. The VHDL file must be placed in the FPGA project folder, or stored in a location included
in the CoreFile parameter.
For more information on the MegaWizard refer to the Instantiating Megafunctions in EDA Tools section (chapter 2) of the Altera
Introduction to Quartus II Manual.
Integrated PCB libraries
There are also PCB design libraries available for many of the Altera programmable devices, in the \Library\Altera folder of
the installation. These libraries include schematic symbols and PCB footprints, as well as 3-D models and signal integrity
models where available.
Altera Place and Route Tools Configuration
The place and route tools are all accessed and configured from the Build stage of the Process Flow associated to the target
physical device in the Devices view. To enable and display the Process Flow when the target device is an Altera FPGA you
must:
have the appropriate Altera place and route tools installed either the full tool suite or the freely downloadable version
available from the Altera website and
your design must be configured for a valid Altera target architecture. This is done by including a suitable device constraint in
a project constraint file, which belongs to a current project configuration (Project Configuration Manager).
For an example of creating a design and configuring it for a target FPGA, refer to the Getting Started with FPGA Design
tutorial.
Build Options
The Build process allows interface with Altera tools and
produces the device program files such as the Raw Binary
Files (.rbf) for downloading into your target FPGA device.
By clicking on the down arrow, a list of individual steps
used to complete the Build process can be found.
Click the Options icon adjacent to each stage to configure
Reports
Options
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Version (v2.0) Feb 29, 2008 3
that feature. Errors or design rules that are not allowed for your target architecture or in the design will be picked up at each
stage of the Build process. The location in the design and the error or warning is logged in a report file, accessed by clicking on
the appropriate Report icon.
For advanced users who want more control over the options passed to the Altera tools, each stage in the Build process is linked
to a single script file DefaultScript_Quartus.Txt located in the \System folder of the installation. Be aware that this
script is defaulted to standard optimization any changes should be carefully applied in consultation with the Altera Introduction
to Quartus II Manual. Individual Build stages are described in the following sections.
Translate Design
This stage creates a Quartus TCL (TCLQ) script, settings, and project (Quartus) files that are used by all the subsequent steps
in the Build process. The TCL (TCLQ) script links the files FPGA_HexMultiplier_constraints.tcl and
FPGA_HexMultiplier_macros.tcl generated from the Synthesis process flow. The TCLQ file is then executed with the
Quartus II Shell (Quartus_sh) using the t switch.
The Altera project can be opened in Quartus if required.
Map Design To FPGA
This stage creates the Altera project database and map.eqn file by running the Quartus II Analysis & Synthesis (Quartus_Map)
tool. It links all design files and performs technology mapping using the Quartus II TCL (TCLQ) script file.
Place and Route
This stage runs the Quartus II Fitter (Quartus_Fit) tool and Quartus TCL (TCLQ) script file to place and route the design for the
target FPGA. It uses the .map, .eqn and other files generated from the Map Design to FPGA process.
Timing Analysis
This stage runs the Quartus II Timing Analyzer (Quartus_Tan) tool to analyze the speed and performance of the implemented
logic for the target FPGA. Analysis options can be configure by clicking on the Options icon.
Make Bit File
This process runs the Quartus II Assembler (Quartus_Asm) tool to generate the Altera device programmable and configuration
files, such as Hexadecimal (Intel-Format) Output Files (.hexout), Raw Binary Files (.rbf), Jam Files (.jam), Jam Byte-
Code Files (.jbc) and Serial Vector Format Files (.svf), for downloading to the chip.
Altera Quartus II Synthesizer Configuration
The system includes a powerful built-in synthesis engine, which is used by default. It also supports use of the Altera Quartus II
synthesizer within the design environment. To enable an FPGA project to utilize this synthesis tool the project synthesis option
must be set to Altera Quartus II. This is done by selecting Project Project Options from the menus, clicking on the
Synthesis tab and choosing Altera Quartus II from the dropdown Synthesizer list. Once this is selected, you must indicate the
folder where the quartus_map binary executable file resides, using the dropdowns associated browse button (). The Options
region of the Synthesis tab will become populated with Altera Quatus II-related options. Configure these to best suit your
design.
For advanced users, options that are not present on the Synthesis tab can be accessed from the
DefaultScript_Quartus.Txt script file located in the \System folder of the installation. Analysis and synthesis switches
must be configured in accordance with the Altera Introduction to Quartus II Manual.
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Figure 1. Setting the Altera Quartus II Synthesizer options.
If you are not familiar with the Altera synthesis tools, it is recommended that you start designing with the built-in DXP or
Altium synthesis engines.
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Revision History
Date Version No. Revision
19-Dec-2003 1.0 New product release
12-Jul-2005 1.1 Updated for Altium Designer SP4
20-Sep-2005 1.2 Cyclone II added to list of supported architectures
12-Dec-2005 1.3 Path references updated for Altium Designer 6
29-Feb-2008 2.0 Updated for Altium Designer Summer 08
22-Aug-2011 - Updated template.
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