Substrate Noise Analysis and Simulation With SubstrateStorm

Substrate Noise Analysis and
Simulation with SubstrateStorm
Philippe Duchene
duchene@simplex.com
© Copyright 2001 Simplex Solutions, Inc. 1

Complete SoC Verification Suite
Power Integrity
VoltageStorm™ SoC
Timing Integrity
Fire & Ice® QX
ClockStorm™
Signal Integrity
SubstrateStorm™
SI Report™
Reliability
ElectronStorm™
The Substrate Crisis
Digital Noise Sensitive Section
Noise Generation Noise Sensitivity

Number devices - UP Signal resolution - UP
Frequency - UP Frequency - UP
Rise / fall time - DOWN Power - DOWN
At 0.13 micron
Noise generation increases by 50%
Noise
© Copyright 2001 Simplex Solutions, Inc. sensitivity increases by 100% 3
ADI Disaster Example:
Trial & Error
• Video converter
with 27 MHz PLL
failed
• VCO locked to
substrate clock
• Various solution
techniques
attempted
• What worked?
www.imse.cnm.es/esd-msd/WORKSHOPS/ESSDERC2000

What designs need
SubstrateStorm?
• Mixed-Signal SoCs
– Digital Noise Generation + Noise
Std cell Logic Transmission + Analog Sensitivity
– 100 MHz or above
Embedded
Memory • RF designs
A/D – Wireless, Bluetooth, 3G, SiGe
D/A – GHz range
• Sensitive analog designs
Std cell – A/D’s, D/A’s
I/O
block
CPU • High-speed I/O’s
PLL core – 1 GHz or above
I/O • High-speed PLL’s
– 500 MHz or above

Typical Substrate Related
Questions
• I have 5 isolation structures

– which is optimal for this design?
• How wide should my guard ring be?
• How will a technology port effect my design
performance?
• What immunity do I gain by backside plating?
• What benefit do I get by splitting my power supply?
•••

SubstrateStorm Design Flow
IC Design
SubstrateStorm
Substrate
Layout Edit
Abstract View
Substrate Technology
LVS/LPE Extraction Description
Netlist
Simulation Visual Analysis

CDS DFII or Standalone GUI

Model Extraction Strategy
Technology
Technology
description
description Layout
Layout
IN
3-D
3-DModel
Model
OUT
Electrical
Electrical Visual
simulation Visual
simulation analysis
analysis

Modeling the Substrate
Bonding Wire
Noise Source Noise Victim
P+ contacts Nwell
N+ contact
• Substrate Abstract View Definition

- Process regions (wells, buried layers, deep trenches, …)
- Ports connecting the ideal circuit to the substrate
- Equivalent ideal circuit model for interactive visual analysis
• RC Model Extraction
3D Modeling
poly
p+
nwell
} LAYOUT
interconnect
y contact device
x
(doping profiles)
p+
PROCESS
z nwell
p-substrate

Distributed RC Model
poly
p+ n+ p+
nwell
well-substrate
resistive junction resistive
p-substrate substrate capacitance well
Modeling

Self-Adjusting Grid
• Unlimited chip size
• Highest accuracy where

needed
• Non-manhattan shapes

SubstrateStorm™ TCT
SubstrateStorm Fabrication Process
Technology
TCAD Measurement
Characterization
Substrate Technology
Extraction Description Doping
Profiles
Patents granted
Simplex Foundry Partners
• Simplex teams up with foundry

Measurement
or TCAD partners to provide acurate
Simulations substrate parameters
Doping Designer
Profiles
Technology
Description
Technology
Characterization
Tool
Substrate
Extraction
Full-chip Analysis
• Design Example
– Effect of pad ring switching
noise on PLLs
• Exploration Questions
– Noise frequency dependence
– Splitting ground lines
– Backside grounding
– Number of VSS pins (package
inductance)
– Guard rings
– etc.

PLL Affected By Output Ring
• Design
– 1M gates, 0.18µ
– 100MHz clock (PLL)
• PLL Noise Concerns:

– Noise propagated from the output
buffer ring
– Explore various solutions to
improve noise immunity

Buffer Creates Substrate Noise
Substrate Noise
Abstract Color
GDS View Map
abstraction analysis
not shown
on customer
request
extraction
SPICE substrate
simulation
subnetlist

Pad Ring Creates Substrate Noise
• SubstrateStorm
– surface distribution of the
noise
• Conditions
– 400ps rise/fall time
– 30pF off-chip load
– 2nH bond inductance
– Plotted @ 350MHz

Noise Is Collected By PLL
PLL is well protected by its

guard rings
BUT
Guard rings also carry noise

!!

Noise Increases with Frequency
DC 350 MHz
Noise isolation typically degrades at higher frequencies
Isolation is 6dB @ DC, but -0.42dB @ 350MHz
Splitting Power Reduces Noise
VSS1 VSS1 VSS2
Effective way of improving isolation (-0.42dB to -9.5dB)

Requires additional pins but no additional space
Backside Grounding Has Little
Effect
With backside connection through a 5nH bond wire:

F Isolation at PLL ring improved by only 0.03dB
F Not worth the cost !
Exploration Questions
• What if you:
– added a N-well guard ring around your PLL?
– used a triple-well process?
– used a low-resistivity substrate?
– introduced a grounded backside connection?
– took the seal ring into account?
– cut the VSS ring to avoid noise transportation
– … Etc …
Each question only takes minutes to answer

using SubstrateStorm
Detailed Cell-level Analysis
Sensitive analog cell

(op-amp)
Noise source (substrate

propagation only)
Goal: locate the most sensitive parts of the analog cell and improve
the noise immunity (lightly doped substrate)
Simulation Set-Up
Noise source
Non-inverter amplifier, gain = 1000

Substrate Impact
s e t Output
i
No pac
im Noise
220mV
Noise source
Through the substrate
tr = 350 ps
What Is the Most Sensitive Part?
Differential input pair?

Input current mirror?
Output driver?
Output current mirror?
Active load?
Compensation circuit?
Combination of them?

Differential Input Pair
VDDA VSSA Substrate model extraction
Circuit netlist back-annotation
SPICE simulation
Output noise < 1% Total noise
Substrate
No impact from this stage
Active Devices < 1% Total Noise
Input Current Mirror

Output Driver
Output Current Mirror
Active Load
Differential Input Pair

Feedback Circuitry
Substrate model extraction
VDDA VSSA
Circuit netlist back-annotation
SPICE simulation
Output noise > 95% Total noise
Substrate Major noise collector is

feedback capacitor
Immunity Increase
1st Solution:
extending the n-well under the
compensation devices
Result:
1: noise immunity improved: 50%
2nd Solution:
p+ ring around the cell
Result:
2: noise immunity improved: 80%
Design trade-off: What’s your choice?

Substrate Technology You Need
• Unique Solution
– Technology Characterization + Accurate Modeling
– Visual Analysis
• Flow Integration
– Standalone: GDS to Spice
– Diva, Calibre, Assura, Dracula
– Seamless Integration in Cadence Virtuoso and Analog Artist
• 2 Use Models
– Detailed Cell Analysis and Simulation
– Chip-level Floorplan Analysis
• Foundry Program
– TSMC, ST, UMC
• Currently Used In Production Designs

New in SubstrateStorm V4.0
• Performance & Capacity

– Upgraded extraction & analysis kernel
• speed 3-5x
– RC Netlist reduction
• capacity 5x
– Macro-modeling
• Ease-of-Use
– Automation of common tasks
– Multiple object edition
• Flow Integration
– Cadence 4.4.5, 4.4.6
– Calibre, Assura, Dracula

STV0399 - first single chip CMOS integration
“Until now, two or more ICs have been required to
implement these functions, at a cost some 25 - 50%
higher.”
• Zero IF tuner
• multistandard demodulator (QPSK and 8-PSK)
• Forward Error Correction (FEC)
• 950-2200 MHz RF input
“We have already applied SubstrateStorm successfully to several
designs, one of which is a very advanced single-chip satellite RF
receiver for cable television. We have been impressed that the first
silicon confirmed the predictions of SubstrateStorm in that the digital
block interference with the RF blocks was sufficiently low as to make
the chip functional.”
Philippe Magarshack
Central R&D Group Vice President for Design Automation and Libraries
SoC + Analog = Substrate Noise
Substrate noise kills

analog performance
...
Don’t wait for it to kill
your design !

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Substrate Noise Analysis and

Simulation with SubstrateStorm

© Copyright 2001 Simplex Solutions, Inc. 1

Digital Noise Sensitive Section

Noise Generation Noise Sensitivity

© Copyright 2001 Simplex Solutions, Inc. 4

© Copyright 2001 Simplex Solutions, Inc. 5

• I have 5 isolation structures

© Copyright 2001 Simplex Solutions, Inc. 6

Simulation Visual Analysis

© Copyright 2001 Simplex Solutions, Inc. 7

© Copyright 2001 Simplex Solutions, Inc. 8

Noise Source Noise Victim

• Substrate Abstract View Definition

© Copyright 2001 Simplex Solutions, Inc. 10

© Copyright 2001 Simplex Solutions, Inc. 11

• Unlimited chip size

• Highest accuracy where

© Copyright 2001 Simplex Solutions, Inc. 12

SubstrateStorm Fabrication Process

• Simplex teams up with foundry

© Copyright 2001 Simplex Solutions, Inc. 15

• PLL Noise Concerns:

© Copyright 2001 Simplex Solutions, Inc. 16

© Copyright 2001 Simplex Solutions, Inc. 17

© Copyright 2001 Simplex Solutions, Inc. 18

PLL is well protected by its

Guard rings also carry noise

© Copyright 2001 Simplex Solutions, Inc. 19

Effective way of improving isolation (-0.42dB to -9.5dB)

With backside connection through a 5nH bond wire:

Each question only takes minutes to answer

Sensitive analog cell

Noise source (substrate

Non-inverter amplifier, gain = 1000

© Copyright 2001 Simplex Solutions, Inc. 25

Differential input pair?

© Copyright 2001 Simplex Solutions, Inc. 27

VDDA VSSA Substrate model extraction

Circuit netlist back-annotation

Output noise < 1% Total noise

Input Current Mirror

© Copyright 2001 Simplex Solutions, Inc. 29

Circuit netlist back-annotation

Output noise > 95% Total noise

Substrate Major noise collector is

Design trade-off: What’s your choice?

• Currently Used In Production Designs

• Performance & Capacity

© Copyright 2001 Simplex Solutions, Inc. 33

Substrate noise kills

© Copyright 2001 Simplex Solutions, Inc. 35

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