Professional Documents
Culture Documents
08190010
CURSO:
LABORATORIO DE MICROELECTRONICA
2012
Diagrama Stick
Corte 2D
Para el LAYOUT del inversor, hallar las dimensiones (W/L) de los transistores, la
frecuencia mxima de operacin y dar respuesta escrita a todas las interrogantes
de la gua que estn arriba planteadas. En el laboratorio pide responder dichas
preguntas.
Segn el CIR spice las dimensiones de los transitores son:
MOS devices
NMOS W= 0.75U L= 0.25U
W/L=3.
PMOS W= 0.75U L= 0.25U
W/L=3.
Extraer
la
descripcin
CIR
(Spice)
y
la
descripcin
CIF(CaltechIntermediateForm) del inversor. En cada caso establecer las reglas
principales de sintaxis y describir sus contenidos. Buscar en internet la
informacin necesaria.
CIF(CaltechIntermediateForm)
( File : "C:\Documents and Settings\Usuario\Escritorio\inversor1.CIF")
( Conversion from Microwind 2b - 17.01.2000 to CIF)
( Version 11/09/2012,3:32:48)
DS 1 1 1;
9 topcell;
L 1;
CIR(Space)
VDD 1 0 DC 2.50
VEntrada 6 0 PULSE(0.00 2.50 0.50N 0.05N 0.05N 0.50N 1.10N)
* List of nodes
* "Vsalida" corresponds to n3
* "Entrada" corresponds to n6
*
* MOS devices
MN1 3 6 0 0 TN W= 0.75U L= 0.25U
MP1 1 6 3 1 TP W= 0.75U L= 0.25U
*
C2 1 0 2.475fF
C3 3 0 1.085fF
C4 1 0 0.551fF
C6 6 0 0.128fF
*
* n-MOS Model 3 :
*
.MODEL TN NMOS LEVEL=3 VTO=0.45 KP=300.000E-6
+LD =0.020U THETA=0.300 GAMMA=0.400
In2
0
0
0
0
1
1
1
1
In1
0
0
1
1
0
0
1
1
S
0
1
0
1
0
1
0
1
F
1
1
1
0
0
1
0
0
Su funcin lgica:
CIF
( File : "C:\Documents and Settings\Usuario\Mis documentos\planxas\informe n1 de
microelectronica\trabajo1\fig1.CIF")
( Conversion from Microwind 2b - 17.01.2000 to CIF)
( Version 11/09/2012,3:51:16)
DS 1 1 1;
9 topcell;
L 1;
P 1750,750 10125,750 10125,3375 1750,3375;
L 19;
P 8850,1975 9150,1975 9150,2275 8850,2275;
P 4100,-1275 4400,-1275 4400,-975 4100,-975;
P 2725,-1275 3025,-1275 3025,-975 2725,-975;
P 6975,-1275 7275,-1275 7275,-975 6975,-975;
P 6975,1975 7275,1975 7275,2275 6975,2275;
P 8850,-1275 9150,-1275 9150,-975 8850,-975;
P 4100,1975 4400,1975 4400,2275 4100,2275;
P 5350,-1275 5650,-1275 5650,-975 5350,-975;
P 5350,1975 5650,1975 5650,2275 5350,2275;
P 2725,1975 3025,1975 3025,2275 2725,2275;
P 7600,100 7900,100 7900,400 7600,400;
L 13;
P 4750,-4000 5000,-4000 5000,-375 4750,-375;
P 7125,-125 8125,-125 8125,625 7125,625;
P 3500,1125 3750,1125 3750,4875 3500,4875;
P 3500,-2125 3750,-2125 3750,-375 3500,-375;
P 7875,625 8125,625 8125,3000 7875,3000;
P 7875,-2125 8125,-2125 8125,-125 7875,-125;
P 4750,1125 5000,1125 5000,4875 4750,4875;
L 23;
P 6750,1750 7500,1750 7500,4375 6750,4375;
P 6375,-125 8125,-125 8125,625 6375,625;
P 8625,-1500 9375,-1500 9375,4375 8625,4375;
P 5125,-4000 5875,-4000 5875,2500 5125,2500;
P 2500,-4000 3250,-4000 3250,2500 2500,2500;
P 3875,-1500 4625,-1500 4625,2500 3875,2500;
L 16;
P 3500,-1750 5000,-1750 5000,-500 3500,-500;
P 2250,-1750 3750,-1750 3750,-500 2250,-500;
P 3250,-1750 4000,-1750 4000,-500 3250,-500;
P 4500,-1750 5250,-1750 5250,-500 4500,-500;
P 7625,-1750 8375,-1750 8375,-500 7625,-500;
P 7875,-1750 9625,-1750 9625,-500 7875,-500;
P 6500,-1750 8125,-1750 8125,-500 6500,-500;
P 4750,-1750 6125,-1750 6125,-500 4750,-500;
L 17;
P 7875,1500 9625,1500 9625,2750 7875,2750;
P 6500,1500 8125,1500 8125,2750 6500,2750;
P 4750,1500 6125,1500 6125,2750 4750,2750;
P 3500,1500 5000,1500 5000,2750 3500,2750;
P 2250,1500 3750,1500 3750,2750 2250,2750;
P 3250,1500 4000,1500 4000,2750 3250,2750;
P 4500,1500 5250,1500 5250,2750 4500,2750;
P 7625,1500 8375,1500 8375,2750 7625,2750;
L 60;
94 F 9000,4125;
94 In2 5625,-3500;
94 Vss 1625,-2875;
94 S 3625,4750;
94 In1 3000,-3750;
94 S 3625,-1875;
94 /S 4875,4750;
94 /S 4875,-3750;
94 Vdd 1375,4000;
DF;
C 1;
E
CIR (Spice)
* List of nodes
* "N2" corresponds to n2
* "F" corresponds to n3
* "In2" corresponds to n5
* "N6" corresponds to n6
* "In1" corresponds to n7
* "/S" corresponds to n9, WARNING: appears 2 times in the layout
* "S" corresponds to n10, WARNING: appears 2 times in the layout
* "S" corresponds to n11, WARNING: appears 2 times in the layout
* "/S" corresponds to n12, WARNING: appears 2 times in the layout
*
* MOS devices
MN1 0 6 3 0 TN W= 0.75U L= 0.25U
MN2 6 9 5 0 TN W= 0.75U L= 0.25U
MN3 7 11 6 0 TN W= 0.75U L= 0.25U
MP1 1 6 3 2 TP W= 0.75U L= 0.25U
MP2 6 12 5 2 TP W= 0.75U L= 0.25U
MP3 7 10 6 2 TP W= 0.75U L= 0.25U
*
C2 2 0 4.122fF
C3 3 0 1.497fF
C4 1 0 1.272fF
C5 5 0 1.358fF
C6 6 0 1.898fF
C7 7 0 1.426fF
C9 9 0 0.073fF
C10 10 0 0.075fF
C11 11 0 0.035fF
C12 12 0 0.075fF
*
* n-MOS Model 3 :
*
.MODEL TN NMOS LEVEL=3 VTO=0.45 KP=300.000E-6
+LD =0.020U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.010 VMAX=130.00K
+CGSO= 0.0p CGDO= 0.0p
*
* p-MOS Model 3:
*
.MODEL TP PMOS LEVEL=3 VTO=-0.45 KP=120.000E-6
+LD =0.020U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.010 VMAX=100.00K
+CGSO= 0.0p CGDO= 0.0p
*
* Transient analysis
*
.TEMP 27.0
.TRAN 0.80PS 20.00N
.PROBE
FIGURA 3
Y=D.C+ D.B+B.C
X=D.C+A.D+ C.A
CIR
CIRCUIT Example.msk
*
* IC Technology: ST 0.25m - 6 Metal
*
VDD 1 0 DC 2.50
VA2 13 0 PULSE(0.00 2.50 2.15N 0.05N 0.05N 2.15N 4.40N)
VA1 14 0 PULSE(0.00 2.50 1.05N 0.05N 0.05N 1.05N 2.20N)
VA0 15 0 PULSE(0.00 2.50 0.50N 0.05N 0.05N 0.50N 1.10N)
VA3 16 0 PULSE(0.00 2.50 4.35N 0.05N 0.05N 4.35N 8.80N)
*
* List of nodes
* "N4" corresponds to n4
* "N5" corresponds to n5
* "Salida 2" corresponds to n6
* "Salida 1" corresponds to n7
* "N8" corresponds to n8
* "N9" corresponds to n9
* "A2" corresponds to n13
* "A1" corresponds to n14
* "A0" corresponds to n15
* "A3" corresponds to n16
*
* MOS devices
MN1 9 13 6 0 TN W= 0.50U L= 0.25U
MN2 10 15 7 0 TN W= 0.50U L= 0.25U
MN3 0 16 9 0 TN W= 0.50U L= 0.25U
MN4 0 13 10 0 TN W= 0.50U L= 0.25U
MN5 10 16 0 0 TN W= 0.50U L= 0.25U
MN6 12 16 0 0 TN W= 0.50U L= 0.25U
MN7 6 14 10 0 TN W= 0.50U L= 0.25U
MN8 7 13 12 0 TN W= 0.50U L= 0.25U
MP1 5 16 1 1 TP W= 0.50U L= 0.25U
MP2 4 13 1 1 TP W= 0.50U L= 0.25U
MP3 6 16 4 1 TP W= 0.50U L= 0.25U
MP4 7 15 5 1 TP W= 0.50U L= 0.25U
MP5 5 14 6 1 TP W= 0.50U L= 0.25U
MP6 8 16 7 1 TP W= 0.50U L= 0.25U
MP7 1 13 8 1 TP W= 0.50U L= 0.25U
MP8 1 13 5 1 TP W= 0.50U L= 0.25U
*
C2 1 0 12.131fF
C3 1 0 5.189fF
C4 4 0 0.121fF
C5 5 0 2.022fF
C6 6 0 4.109fF
C7 7 0 5.021fF
C8 8 0 0.121fF
C9 9 0 0.183fF
C10 10 0 2.414fF
C12 12 0 0.239fF
C13 13 0 4.297fF
C14 14 0 1.375fF
C15 15 0 2.186fF
C16 16 0 1.646fF
*
* n-MOS Model 3 :
*
.MODEL TN NMOS LEVEL=3 VTO=0.45 KP=300.000E-6
+LD =0.020U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.010 VMAX=130.00K
+CGSO= 0.0p CGDO= 0.0p
*
* p-MOS Model 3:
*
.MODEL TP PMOS LEVEL=3 VTO=-0.45 KP=120.000E-6
+LD =0.020U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.010 VMAX=100.00K
CIR(SPACE)
VISTA 3D
FIGURA 2
Cn+1
Funcin logica
F= ac + bc +ca
LAYOUT
CIR
CIRCUIT example
*
* IC Technology: ST 0.25m - 6 Metal
*
VDD 1 0 DC 2.50
VB 16 0 PULSE(0.00 2.50 2.05N 0.05N 0.05N 2.05N 4.20N)
VA 17 0 PULSE(0.00 2.50 1.00N 0.05N 0.05N 1.00N 2.10N)
*
* List of nodes
* "N4" corresponds to n4
* "N5" corresponds to n5
* "N6" corresponds to n6
* "C" corresponds to n9
* "B" corresponds to n16
* "A" corresponds to n17
*
* MOS devices
MN1 11 17 0 0 TN W= 0.50U L= 0.25U
MN2 5 16 11 0 TN W= 0.50U L= 0.25U
MN3 12 17 5 0 TN W= 0.50U L= 0.25U
MN4 0 16 12 0 TN W= 0.50U L= 0.25U
MN5 0 5 9 0 TN W= 0.75U L= 0.25U
MN6 12 9 14 0 TN W= 0.63U L= 0.25U
MP1 4 17 1 1 TP W= 0.50U L= 0.25U
MP2 5 16 4 1 TP W= 0.50U L= 0.25U
MP3 6 17 5 1 TP W= 0.50U L= 0.25U
MP4 1 16 6 1 TP W= 0.50U L= 0.25U
MP5 9 5 1 1 TP W= 0.75U L= 0.25U
MP6 4 9 6 1 TP W= 0.63U L= 0.25U
*
C2 1 0 24.011fF
C3 1 0 0.716fF
C4 4 0 2.869fF
C5 5 0 3.633fF
C6 6 0 2.013fF
C7 1 0 0.717fF
C8 1 0 0.547fF
C9 9 0 2.313fF
C11 11 0 0.791fF
C12 12 0 4.278fF
C14 14 0 0.587fF
C16 16 0 2.247fF
C17 17 0 1.827fF
C18 18 0 2.862fF
*
* n-MOS Model 3 :
*
.MODEL TN NMOS LEVEL=3 VTO=0.45 KP=300.000E-6
+LD =0.020U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.010 VMAX=130.00K
+CGSO= 0.0p CGDO= 0.0p
*
* p-MOS Model 3:
*
.MODEL TP PMOS LEVEL=3 VTO=-0.45 KP=120.000E-6
+LD =0.020U THETA=0.300 GAMMA=0.400
VISTA EN 3D