VLSI interview questions with answers

Steps involved in designing an optimal padring

Ans:
2. Ensure that the Padring ful-fills the ESD requirement, Identify the power-domains,
split the domains, Ensure ommon ground aross all the domains.
!. Ensure the padring has full-filled the SS"#Simultaneous Swithing "oise$
requirement.
%. Plaing &ransfer-ell Pads in the ross power-domains, for different height pads, to
ha'e rail onneti'ity.
(. Ensure that the design has suffiient ore power-pads.
). *hoose the Dri'e-strength of the pads +ased on the urrent requirements, timing.
,. Ensure that there is separate analog ground and power pads.
-. A "o-*onnetion Pad is used to fill out the pad-frame if there is no requirement for
I./0s.E1tra 2DD.3"D pads also ould +e used. Ensure that no Input.output pads are used
with un-onneted inputs, as they onsume power if the inputs float.
4. Ensure that osillator-pads are used for lo5 inputs.
67. In-ase if the design requirement for soure synhronous iruits, ma5e sure that the
lo5 and data pads are of same dri'e-strength.
66. 8rea5er-pads are used to +rea5 the power-ring, and to isolate the power-struture
aross the pads.
62. Ensure that the metal-wire onneted to the pin an arry suffiient amount of the
urrent, he5 if more than one metal-layer is neessary to arry the ma1imum urrent
pro'ided at the pin.
6!. In ase if required , plae pads with apaitane.
What is metastability and steps to prevent it.
Ans: 9etasta+ility is an un5nown state it is neither :ero nor /ne. 9etasta+ility happens
for the design systems 'iolating setup or hole time requirements. Setup time is a
requirement , that the data has to +e sta+le +efore the lo5-edge and hold time is a
requirement , that the data has to +e sta+le after the lo5-edge. &he potential 'iolation of
the setup and hold 'iolation an happen when the data is purely asynhronous and
lo5ed synhronously.
Steps to pre'ent 9etasta+ility.
6. ;sing proper synhroni<ers#two-stage or three stage$, as soon as the data is oming
from the asynhronous domain. ;sing Synhroni<ers, reo'ers from the metasta+le
e'ent.
2. ;se synhroni<ers +etween ross-lo5ing domains to redue the possi+ility from
metasta+ility.
!. ;sing =aster flip-flops #whih has narrower 9etasta+le >indow$.
62. what is loal-s5ew, glo+al-s5ew,useful-s5ew mean?
@oal s5ew : &he differene +etween the lo5 reahing at the launhing flop 's the lo5
reahing the destination flip-flop of a timing-path.
3lo+al s5ew : &he differene +etween the earliest reahing flip-flop and latest reahing
flip-flop for a same lo5-domain.
;seful s5ew: ;seful s5ew is a onept of delaying the apturing flip-flop lo5 path, this
approah helps in meeting setup requirement with in the launh and apture timing path.
8ut the hold-requirement has to +e met for the design.
what is meant by virtual clock definition and why do i need it?
Ans: 2irtual lo5 is mainly used to model the I./ timing speifiation. 8ased on what
lo5 the output.input pads are passing the data.
What are the various timingpaths which i should take care in my S!" runs?
Ans:
6. &iming path starting from an input-port and ending at the output port#purely
om+inational path$.
2. &iming path starting from an input-port and ending at the register.
!. &iming path starting from an Aegister and ending at the output-port.
%. &iming path starting from an register and ending at the register.
What are the various components of Leakagepower?
Ans: 6. su+-threshold lea5age,....thin5 of ths answer
What are the various yieldlosses in the design?
Ans: &he yield loss in the design is harateri<ed +y
6. =untional yield losses, mainly aused +y spot defets , espeially #shorts B opens$
2. Parametri yield losses, due to proess 'ariations.
what is the difference between mealy and moore statemachines
Ans: In the mealy state mahine we an alulate the ne1t state and output +oth from the
input and state. 8ut in the moore state mahine we an alulate only ne1t state +ut not
output from the input and state and the output is issued aording to ne1t state.
#ow to solve setup $ #old violations in the design
Ans: &o sol'e setup 'iolation
6. optimi<ing.restruturing om+ination logi +etween the flops.
2. &wea5 flops to offer lesser setup delay CD==D6 -E D==D1F
!. &wea5 launh-flop to ha'e +etter slew at the lo5 pin, this will ma5e *G-EH of
launh flop to +e fast there +y helping fi1ing setup 'iolations
%. Play with s5ew C twea5 lo5 networ5 delay, slow-down lo5 to apturing flop and
fasten the lo5 to launh-flopF#otherwise alled as ;seful-s5ews$
&o sol'e Iold 2iolations
6. Adding delay.+ufferCas +uffer offers lesser delay, we go for spl Delay ells whose
funtionality JKA, +ut with more delayF
2. 9a5ing the launh flop lo5 reahing delayed
!. Also, one an add lo5up-lathes Cin ases where the hold time requirement is 'ery
huge, +asially to a'oid data slipF
What is antenna Violation $ ways to prevent it
Ans: During the proess of plasma ething, harges aumulate along the metal strips.
&he longer the strips are, the more harges are aumulated. I= a small transistor gate
onneted to these long metal strips, the gate o1ide an +e destroyed #large eletri field
o'er a 'ery thin eletri$ , &his is alled as Antenna 'iolation.
&he ways to pre'ent is , +y ma5ing Logging the metal line, whih is atleast one metal
a+o'e the layer to +e proteted. If we want to remo'e antenna 'iolation in metal2 then
need to Log it in metal! not in metal6. &he reason +eing while we are ething metal2,
metal! layer is not laid out. So the two piees of metal2 got disonneted. /nly the piee
of metal onneted to gate ha'e harge to gate. >hen we laydown metal!, the remaining
portion of metal got harge added to metal!. &his is alled aumulati'e antenna effet.
Another way of pre'enting is adding re'erse Diodes at the gates
what is tiehigh and tielow cells and where it is used
Ans: &ie-high and &ie-@ow ells are used to onnet the gate of the transistor to either
power or ground. In deep su+ miron proesses, if the gate is onneted to power.ground
the transistor might +e turned on.off due to power or ground +oune. &he suggestion from
foundry is to use tie ells for this purpose. &hese ells are part of standard-ell li+rary.
&he ells whih require 2dd, omes and onnet to &ie high...#so tie high is a power
supply ell$...while the ells whih wants 2ss onnets itself to &ie-low.
what is the difference between latches and flipflops based designs
Ans: @athes are le'el-sensiti'e and flip-flops are edge sensiti'e. lath +ased design and
flop +ased design is that lath allowes time +orrowing whih a tradition flop does not.
&hat ma5es lath +ased design more effiient. 8ut at the same time, lath +ased design is
more ompliated and has more issues in min timing #raes$. Its S&A with time
+orrowing in deep pipelining an +e quite omple1.
What is #ighVt and LowVt cells.
Ans: I't ells are 9/S de'ies with less lea5age due to high 2t +ut they ha'e higher
delay than low 2&, where as the low 2t ells are de'ies whih ha'e less delay +ut
lea5age is high. &he thereshold#t$ 'loltage ditates the transistor swithing speed , it
matters how muh minimum threshold 'oltage applied an ma5e the transistor swithing
to ati'e state whih results to how fast we an swith the trasistor. disad'antage is it
needs to maintain the transistor in a minimum su+threshold 'oltage le'el to ma5e ir
swith fast so it leads to lea5age of urrent inturn loss of power.
What is L%& mean?
Ans: @E= is an AS*II data format from *adene Design in, to desri+e a standard ell
li+rary. It inludes the design rules for routing and the A+strat layout of the ells. @E=
file ontains the following,
&ehnology: layer, design rules, 'ia-definitions, metal-apaitane
Site : Site e1tension
9aros : ell desriptions, ell dimensions, layout of pins and +lo5ages, apaitanes
what is '%& mean?
Ans: DE= is an AS*II data format from *adene Design in., to desri+e Design related
information.
hat are the various 'esign constraints used while performing Synthesis for a
design?
Ans: 6. *reate the lo5s #frequeny, duty-yle$.
2. Define the transition-time requirements for the input-ports
!. Speify the load 'alues for the output ports
%. =or the inputs and the output speify the delay 'alues#input delay and ouput delay$,
whih are already onsumed +y the neigh+our hip.
(. Speify the ase-setting #in ase of a mu1$ to report the timing to a speifi paths.
). Speify the false-paths in the design
,. Speify the multi-yle paths in the design.
-. Speify the lo5-unertainity 'alues#w.r.t Litter and the margin 'alues for setup.hold$.
64. Speify few 'erilog onstruts whih are not supported +y the synthesis tool.
What are the various design changes you do to meet design power targets?
Ans: Design with 9ulti-2DD designs, Areas whih requires high performane, goes with
high 2DD and areas whih needs low-performane are wor5ing with low 2dd0s, +y
reating 2oltage-islands and ma5ing sure that appropriate le'el-shifters are plaed in the
ross-'oltage domains Designing with 9ulti-2t0s#threshold 'oltages$, areas whih
require high performane, goes with low 2t, +ut ta5es lot of lea5age urrent, and areas
whih require low performane with high 2t ells, whih has low lea5age num+ers, +y
inorporating this design proess, we an redue the lea5age power. As in the design ,
lo5s onsume more amount of power, plaing optimal lo5-gating ells, in the design
and ontrolling them +y the module ena+le0s gi'es a lot of power-sa'ings.
As lo5-tree0s always swith ma5ing sure that most num+er of lo5-+uffers are after the
lo5-gating ells, this redues the swithing there +y power-redution.
Inorporating Dynami 2oltage B =requeny saling #D2=S$ onepts +ased on the
appliation , there +y reduing the systems 'oltage and frequeny num+ers when the
appliation does not require to meet the performane targets. Ensure the design with IA-
Drop analysis and ground-+oune analysis, is with-in the design speifiation
requirement. Plae power-swithes, so that the lea5age power an +e redued. related
information.
what is meant by Library (haracteri)ing
Ans: *harateri<ation in terms of delay, power onsumption,..
what is meant by wireload model
Ans: In the synthesis tool, in order to model the wires we use a onept alled as
M>ireload modelsM, "ow the question is what is wireload models: >ireload models are
statistial +ased on models with respet to fanout. say for a partiular tehnology +ased
on our pre'ious hip e1periene we ha'e a rough estimate we 5now if a wire goes for MnM
num+er of fanin then we estimate its delay as say M1M delay units. So a model file is
reated with the fanout num+ers and orresponding estimated delay 'alues. &his file is
used while performing Synthesis to estimate the delay for >ires, and to estimate the
delay for ells, tehnology speifi li+rary model files will +e a'aila+le
what are the measures to be taken to design for optimi)ed area
Ans: As silion real-estate is 'ery ostly and sa'ing is diretly propotional to the
ompany0s re'enue generation lot of emphasi<e is to design whih has optimial utili<ation
in the area-front. &he steps to redue area are
If the path is not timing-ritial, then optimi<e the ells to use the low-dri'e strength ells
so that there will sa'ing in the area. A+ut the 2DD rows Analy<ing the utili<ation
num+ers with multiple floor-planning 'ersions whih +rings up with optimi<ed area
targets.
what all will you be thinking while performing floorplan
Ans: Study the data-flow graph of the design and plae the +lo5s aordingly, to
reduing the weighted sum of area, wire-length. 9inimi<e the usuage of +lo5s other-
than square shapes, ha'ing nothes Plae the +lo5s +ased on aessi+ility.onneti'ity,
there+y reduing wire-length. A+ut the memory, if the pins are one-sided, there-+y area
ould +e redued. If the memory ommuniates to the outside world more frequently ,
then plaing at the +oundary ma5es muh of a sense. Study the num+er of pins to +e
routed, with the minimum metal width allowed , estimate the routa+ility issues. Study the
arhiteture and appliation , so that the +lo5s whih will +e ena+led should +e
sattered, to redue the power-ground noise.
what are the measures in the 'esign taken for *eeting Signalintegrity targets
Ans: As more and more de'ies are getting pa5ed, results in more ongested areas, and
oupling apatianes dominating the wire-apaitane, reates SI 'iolations. @et0s see
now +y what are all the measures we an redue.sol'e it.
As lo5-tree runs aross the whole hip, optimi<ing the design for SI, is essential route
the lo5 with dou+le-pith and triple spaing. In-ase of SI 'iolation, spaing the signal
nets redues ross-tal5 impats.
Shield the nets with power-nets for high frequeny signal nets to pre'ent from SI.
Ena+le SI aware routing , so that the tool ta5es are for SI
Ensure SI ena+led S&A runs, and guarantee the design meeting the SI requirements
Aoute signals on different layers orthogonal to eah other
9inimi<e the parallel run-length wires, +y inserting +uffers.
what are the measures taken in the 'esign achieving better +ield
Ans: 8etter yield ould +e ahie'ed +y reduing the possi+ility of manufatura+ility
flaws. 3uaranting the iruit performane, +y reduing parametri yield, with proess
'ariations playing a maLor role is a +ig-hallenge.
*reate more powerful stringent runset files with pessimisti spaing.short rules.
*he5 for the areas where the design is prone to lithographi issues, li5e sharp uts and
try to re-route it.
=or 'ia-relia+ility issues, use redundant 'ias, to redue the hanes for 'ia-+rea5age.
In order to design for yield-enhanement , design systems, whih ould ha'e optimal
redundany, li5e repaira+le memories.
/ptimal plaing of de-oupling apaitanes, redues the power-surges.
Dou+ling the width of the non-ritial nets, lo5-nets an inrease the yield parameter.
Ensure that the poly-orientation are maintained.
what are the measures or precautions to be taken in the 'esign when the chip
has both analog and digital portions
Ans: Designing for /ptimal integration of Analog and Digital As today0s I* has analog
omponents also in+uilt , some design praties are required for optimal integration.
Ensure in the floorplanning stage that the analog +lo5 and the digital +lo5 are not siting
lose-+y, to redue the noise. Ensure that there e1ists seperate ground for digital and
analog ground to redue the noise. Plae appropriate guard-rings around the analog-
maro0s. Inorporating in-+uilt DA*-AD* on'erters, allows us to test the analog portion
using digital testers in an analog loop-+a5 fashion. Perform tehniques li5e lo5-
dithering for the digital portion.
what are the steps incorporated for %ngineering (hange ,rder-%(,.
Ans: As more and more omple1 the I* design is , and with lot of first time appliation ,
is more prone to last minute hanges, there should +e pro'ision in the design-flow to
aomodate the funtional and timing +ugs. &he step to perform this alled as
Engineering hange order#E*/$. Ensure that the design has spare funtional gates well
distri+uted aross the layout. Ensure that the seletion the spare gates, has many fla'ours
of gates and uni'ersal gates, so that any funtionality ould +e ahie'ed.
what are the steps performed to achieve Lithography friendly 'esign
Ans: Designing for 9anufatura+ility requires 'alidating the design full-filling
lithography rules *he5ing the layout onfirming the design rules #spaing,trae-
width,shorts$. *he5 for the less-ongested areas and inreasing the spaing of the nets.
what does synthesis mean
Ans: Synthesis is a step of mapping the A&@ files #'erilog format or 'hdl format$ to
on'ert it to the tehnology speifi ells..
What are the various ways to reduce (lock Insertion 'elay in the 'esign
Ans: 6. "um+er of *lo5 sin5s
2. 8alaning two different lo5 frequenies
!. Plaement of lo5 sin5s.
%. Plaement of *lo5 gating ells
(. *lo5 tree +uffers.in'erters dri'e strength0s
). *lo5 &ransition
,. plaement of *lo5gating ells and the lo5 sin5s
-. *om+inationals ells in the path of lo5s #say lo5 di'iders, mu1es, lo5gates$ ...
what are the various functional verification methodologies
Ans: &@9#&ransation @e'el 9odelling$
@inting
A&@ Simulation # Eni'ronment in'ol'ing : stimulus generators, monitors, response
he5ers, transators$
3ate le'el Simulation
9i1ed-signal simulations
Aegression
What does formal verification mean?
Ans: =ormal 'erifiation uses 9athematial tehniquest +y proo'ing the design through
assertions or properties. *orretness of the design an +e ahie'ed through assertions
with out the neessity for simulations. &he methods of formal 'erifiation are
6. Equi'alene he5ing In this method of he5ing the designs are ompared +ased on
mathematial equations and ompared whether they are equal or not . /riginal A&@ 's
9odified A&@ A&@ 's "etlist 3olden "etlist 's 9odified.Edited "etlist Synthesis "etlist
's Plae and route "etlist Aemem+er : =ormal 'erifiation doesnt he5 for funtionality
of the A&@ ode. It will +e only he5ing the equi'alene.
2. 9odel he5ing Property speifiation languages li5e PS@ or S2A, are formally
analy<ed to see if they are always true for a design. &his an e1hausti'ely pro'e if a
property is orret, +ut does tend to suffer from state-spae e1plosion: the time to analyse
a design is diretly propotional to the amount of states.
/reparation for analog 0 rfic interview
6$ Differentiate +etween Analog and Digital I* design ?
Analog iruit design is different from Digital *iruit design in following aspets:
N @ayout is ritial sine the routing should +e done aording to A= design rules
N @ayout in digital an +e ompletely automati whih is not the ase in analog iruits
N 3rounding issue is ritial in Analog or A=I* ompared to Digital I*
N Si<e of analog I*Os are large ompared to digital sine it omprises of indutors
apaitors and resistors where as digital I*Os inludes only apaitors and resistors.
2$ >hih are the 'arious proesses used for fa+riation of I*Os?
&he different proesses used for fa+riation of I*Os are:
N 3aAs
Si3e *9/S 8i*9/SP should 5now some fundamentals on eah proess
!$ >hat is the +asi purpose of using E9 simulation?
8asi purpose of E9 simulation is to predit the atual +eha'ior of A= *iruits
onsidering all the parasiti and oupling. &his is not onsidered in iruit simulation.
%$ @ist the instruments required for testing A= 9odules and I*Os Instruments required for
A= testing are:
N Spetrum Analy<er
N 2etor "etwor5 Analy<er
N "oise =igure 9eter
N Power 9eter
($ >hih are +asi +lo5s that omprise the A= &ransei'er?
A= Aeei'er onsists of
N @ow "oise Amplifier.A= Amplifier
N 9i1er
N @oal /sillator
N Demodulator
N Automati 3ain ontroller
N Automati =requeny ontroller.
N =ilters
N Swith
A= &ransmitter onsists of
N A= power amplifier
N 9odulator
N *arrier /sillator
N P@@
N =ilters
N Swith
)$ >hat is the +asi funtion of a power amplifier?
&he main funtion of A= power amplifier is to +oost the power le'el of a Signal so that it
an tra'el a signifiant distane. Power amplifiers are required in all the transmitters
,$ >hat is the +asi funtion of a low noise amplifier?
&he main funtion of @ow "oise Amplifier is to amplify the wea5est possi+le Signal with
"oise =igure as low as possi+le during reeption and to impro'e the sensiti'ity and
dynami range of a reei'er.
-$ >hat is the +asi funtion of a 9i1er?
=requeny translation is the 5ey role of 9i1er. /utput ontains the sum or differene of
two frequenies i.e. A= frequeny and @/#@oal /sillator$

&hese analog design tehniques are also useful for inter'iew preparation
6. 9inimum hannel length of the transistor should +e four to fi'e times the minimum
feature si<e of the proess. >e do it, to ma5e the lam+da of the transistor low i.e. the rate
of hange of Id w.r.t to 2ds is low.
2. Present art of analog design still uses the transistor in the saturation region. So one
should always 5eep 2gs of the &ransistor !7Q a+o'e the 2t.
!. /ne should always split the +ig transistor into small transistors ha'ing width or length
feature si<e RK 6(um.
%. >.@ Aatio of transistors of the mirror iruit should +e less than or equal to (, to
ensure the proper mathing of the transistors in the layout. /therwise, it results to the
Systamati /ffset in the iruit.
(. /ne should ma5e all the required pins in the shmeti +efore generating the layout
'iew. All I/ pins should +e a metal2 pins whereas 2dd and 3round should +e metal6
pins.
). /ne should first simulate the iruit with the typial model parameters of the de'ies.
Sine 2t of the trasistor an +e anything +etween 2t#&ypial$ 27Q. So we he5 our
iruit for the e1treme ases i.e. 2t S 27Q, 2t 27Q. A transistor ha'ing 2t 27Q is alled
a fast transistor and transistor ha'ing 2tS27Q is alled slow transistor. It0s Lust a way to
di
erentiate them. So with these fast and slow transistor models we ma5e four om+ination
alled nfpf, nfps, nspf, nsps, whih are 5nown as proess orners. "ow, one we are
stised with the iruit performane with typial models than we he5 it in di
erent proess orners, to ta5e the proess 'ariation into aount. 2t is Lust one e1ample of
the proess 'ariation there are others parameter too.
,. Its thum+ rule that poly resistane has a 27Q proess 'ariation whereas well resistane
has got 67Q. 8ut the poly resistane has got lower temperature ofeent and lower Sheet
Aesistane than well resistane. So we hoose the resistane type depending upon the
requirments. Poly *apaitane has got a proess 'ariation of 67Q.
-. /ne should also he5 the iruit performane with the temperature 'ariation. >e
usuly do it for the range of -%7* to -(*.
4. /ne should ta5e the parasiti apaitane into aount where'er one is ma5ing an
o'erlap with metal layers or wells.
67. In @ayout, all transistors should +e plaed in one diretion, to pro'ide the same
en'ironment to all the transistors.
66. /ne should plae all transistor in layout with a due are to the pinposition +efore start
routing them.
62. /ne should always use the 9etal 6 for hori<ontal routing and 9etal 2 for the 'ertial
routing as far as possi+le.
6!. /ne should ne'er use P/@J as routing layer when the interonnets arries a urrent.
/ne an ha'e a short gate onnetion using poly.
6%. /ne should try to a'oid running metal o'er poly gate. As this ause to inrease in
parasiti apaitane.
6(. *urrent in all the transistor and resistor part should ow in the same diretion.
6). /ne should do the Power#2dd B 3nd$ routing in top layer metal #metal( only$.
8eause &op layer metals are usually thi5er and wider and so has low resistane.
6,. /ne should always merge drain and soure of transistor #of same type$ onneted
together.
6-. &o minimi<e the proess 'ariation in the Aesistor 'alue one should always ta5e the
resistor0s width three to four times of the default 'alue. we do it to derease the 'alue of
dA.d@
64. /ne should o'er the resistane with metal layer, to a'oid the damaged during the
wafer le'el testing.
27. /ne should always ma5e a *ommon *entroid struture for the mathed transistor in
the layout. .Eah di
erential pair transistor should +e di'ide into four transistors and should +e plaed in two
rows ommon entroid struture. ./ne may use the the linear ommon entroid struture
for the urrent mirror iruit.
26. It0s ad'isia+le to put a dummy layers around the resistane and the apaitane to
a'oid the erosion at the time of ething.
22. /ne should always ha'e a 3uard Aing arround the di
erential pair.
2!. Always put a 3uard Aing arround the "-well and P-well.
2%. &hum+ rule for the metal urrent density is 7:-mAKm. It0s larger for the top most
metal layer.
2(. &o a'oid the @athup, one should always ma5e the P" Luntion re'erse +iased i.e. In
">E@@ should +e onneted to positi'e power supply#2dd$ and P>E@@ should +e
onneted to negati'e power supply# 3nd$. Designers do it to ma5e the lea5age urrent
small.
2). It0s always a good pratie to use a infote1t layer to put the name of the de'ie on the
top of it in layout and ha'e a netname for e'ery nets in shemati. Designer should put
the pin name on the top of the pin with same metalt1t layer +eause heruels ta5es the
netname from metalt1t only whereas Di'a ta5es from the pin-name.
2,. *adene SPI*E simulator ta5e 'ddT B gndT as a glo+al 2dd and 3nd net i.e. any net
ending with 0 T0 is onsidered as a glo+al net..
(ommon 1ote 2 !he basic principle is same 3 but for some notes vary from company
to company
!iming "nalysis Interview 4uestions
>hy is Iold time negleted while alulating 9a1 =requeny? >hy only Setup
time is onsidered?
>hat is apaiti'e loading? Iow does it affet slew rate?
>hat is useful-s5ew mean?
>hat is false path? 3i'e an e1ample?
>hat are multi-yle paths? 3i'e e1ample.
Iow operating 'oltage an +e used to satisfy timing?
Iow to sol'e setup and Iold 'iolations in the design
>hat is the differene +etween loal-s5ew, glo+al-s5ew and useful-s5ew?
>hat are the 'arious timing-paths whih should +e ta5en are in S&A?
>hat is meant +y 'irtual lo5 definition and why do i need it?
>hat are the 'arious Design onstraints used while performing Synthesis for a
design?
>hat are set up time and hold time onstraints? >hat do they signify? >hih one
is ritial for estimating ma1imum lo5 frequeny of a iruit?
>hat is differene +etween setup and hold time?
Iold time does not depend on lo5. Is it true? If so why?
>hat is false path? Iow it is determined in iruit?
>hat are the affets of false path in a iruit?
Iow power is related with lo5 frequeny?
>hat are multi-yle paths?
Is it possi+le to redue lo5 s5ew to <ero?
>hat is s5ew, what are pro+lems assoiated with it and how to minimi<e it?
>hat is sla5?
Iow you an inrease lo5 frequeny?
>hat is the signifiane of ontamination delay in sequential iruit timing?
>hat is negati'e sla5? Iow it affets timing?
>hat is positi'e sla5? Iow it affets timing?
Differene +etween Synthesis and simulation?
>hat is ell delay and net delay?
>hat are delay models and differene +etween them.
>hat is wire load model?
>hat does SD* onstraints has?
/" path means for a partiular path from input port to outport there is no dependeny
+y other ports.
It< quit opposite for /== path.
=ew Huestions :
if A and 8 are two l5 pulses whih are out of phase and ha'ing same frequeny, how to
find whih input l5 signal is leading?
Iere is the simple solution for this.
All it needs is a flip flop.
if we ha'e 2 l5s, l56 and l52 gi'e l56 to D-input of flip flop and other to *@G input
of ==.
if l56 is leading the output is high.
if l52 is leading the output is low.
Do you guys get this...
&he a+o'e answer of mine assumes that the 2 lo5s are of out of phase not more than %(
degrees.
If the two lo5s are out of phase more than %( degrees than state diagram
implementation is to +e done. I wor5ed on it and I ha'e the equations for the iruit
implemented using 2 flip flops.
H6#tS6$KH6SH208
H2#tS6$KH2SH60A
:KH2 K 6 for l5A leading else 7 for l58 leading.
wor5 this out.
&he sla5 is the time delay differene from the e1peted delay#6.lo5$ to the atual
delay in a partiular path.
Sla5 may +e S'e or -'e.
what is.are the differenes +etween SI9;@A&I/" and SJ"&IESIS
Simulation RK 'erify your design.
synthesis RK *he5 for your timing
Simulation is used to 'erify the funtionality of the iruit.. a$=untional
Simulation:study of 5t0s operation independent of timing parameters and gate delays. +$
&iming Simulation :study inluding estimated delays, 'erify setup,hold and other timing
requirements of de'ies li5e flip flops are met.
Synthesis:/ne of the foremost in +a5 end steps where +y synthesi<ing is nothing +ut
on'erting 2ID@ or 2EAI@/3 desription to a set of primiti'es#equations as in *P@D$
or omponents#as in =P3A0S$to fit into the target tehnology.8asially the synthesis tools
on'ert the design desription into equations or omponents
an u tell me the differenes +etween lathes B flipflops?
&here are 2 types of iruits:
6. *om+inational
2. Sequential
@athes and flipflops +oth ome under the ategory of Msequential iruitsM.
Differene: @athes are le'el-sensiti'e, whereas, == are edge sensiti'e. 8y edge sensiti'e,
I mean /.p hanges only when there is a lo5 transition.# from 6 to 7, or from 7 to 6$
E1ample: In a flipflop, inputs ha'e arri'ed on the input lines at timeK 2 seonds. 8ut,
output won0t hange immediately. At time K ! seonds, lo5 transition ta5es plae. After
that, /.P will hange.
=lip-flops are of 2 types:
6.Positi'e edge triggered
2. negati'e edge triggered
6$fllipflops ta5e twie the nym+er of gates as lathes
2$ so automatially delay is more for flipflops
!$power onsumption is also more
I ha'e got few +asi 2ID@ questions:
6. >hat is the differene +etween using diret instntiations and omponent ones
e1ept that you need to delare the omponent ?
2. >hat is the use of 8@/*GS ?
!. >hat is the use of PA/*ED;AES?
%. >hat is the usage of using more then one arhiteture in an entity?
9mm... >hat do mean +y diret instantiation and omponent ones? In 2ID@,
you always ha'e to delare a omponent +efore you instantiate it. I don0t thin5
I understand the question.
2. 8@/*G is a tri5y one. If you do mostly in synthesis, then you
will rarely need to use it. I don0t remem+er all the detail +ut it has to
do how the signal is +eing determine whether it is glo+al or not. #2isi+le
+y other proess, et.$ 9ainly for simulation purpos. #Someone should
gi'e more detail than I an.$
!. Proedure is a way to reuse ode. Proedure and =untion are 'ery
simular e1ept funtion returns something and proedure don0t. ;sually
proedures and funtions are for test+enh and simulation although I ha'e
used them in synthesis sometimes. Do +e aware that not all synthesi<er
an handle it properly. /ne plae to see how it wor5s is to get a 2ID@
SDAA9 simulation model and study it. It usually use either proedure or
funtion. &his is a 'ery general topi, people use an entire hapter to do
this.
%. ;se of more than one arhiteture has many +enefits. =or e1ample, a
olour spae on'erter. Jou an implement a standard !1! matri1
multiplier. 8ut if you 5now you are wor5ing on a speifi olour spae, suh
as )76, then you an optimi<e it to use only % multiplers #if I remem+er
orretly$. In the main ode, you put in a onfiguration line to speify whih
arhiteture to use for that entity. It is a good way to ha'e a module
implement or +eha'e different under non run time situation.
I : one +asi question, what is S&A.
U : S&A stands for Stati &iming Analysis, he5s whether the Design 9eeets the timing
requirements, aross all the timing ars.
I : Jou mentioned timing *he5s , what do you mean +y that.
U : Setup &iming *he5, Iold &iming *he5, *lo5-gating *he5
I : 3ood, do you perform some he5s for asynhronous stuffs or not.
U : Jes , I do perform he5s , li5e reo'ery, remo'al.
I : what is reo'ery and remo'al he5?
U : reo'ery is similar to setup he5 and remo'al is similar to a hold he5.
I : what are the 'arious &iming-paths you see in any hip?
U : Path 6: Path starting from input port and ending at a Aegister Data
Path 2: Path starting from register output and ending at the register output
Path !: Path starting from register output and ending at the output port
Path %: Path starting from inputport and ending at the output port.
Path (: &iming Soure synhronous paths.
I : 3ood, ha'e you ome aross with a report Vhe5Ptiming V, does this was of some use
to you any-time.
U : yes , as soon as i reie'e data+ase , i used to generate this report, this will guide me to
5now the list of flip-flops not ha'ing lo5s, flip flops with multiple lo5s, input port
onstraints missing, timing loops and things li5e that , It is a quiet informati'e report.
I : >e will ontinue after a +rea5,
signoff for nowW. ontinue in part 2 setion.
&ill then &o +rush up the +asis of Stati &iming Analysis:
http:..www.'lsihipdesign.om.statiPtimingPanalysis.html
I CInter'iewerF : Is the &iming analysis intelligent enough to 5now all the lo5s and
generated lo5s in your design .
U CLo+ see5erF : >e used to reate the lo5 definitions, 3enerated lo5 definitions using
their speifi master lo5s , lo5s speifing their rise and fall edges, periods and things
li5e that..
I : >ell, >hat is this ideal mode and propagated mode in lo5s.
U : Ideal mode is assuming that the lo5s to all the flops are assumed to +e reahing at
the same time. &his is used during synthesis stage, assuming we are going to perform
lo5-tree synthesis and then we will notie the real time lo5 arri'al times.
In the propagation mode settings are used after *&SClo5 tree synthesisF is performed,
and after this stage while we perform the Stati &iming Analysis, we need to set this.
I : Assume i forgot to +e in the propagation mode after *&S, and i had performed S&A,
do you still see any ris5.
U : &he *hip timing performane is totally not guaranteed after the Silion. 8eause we
are +lindly assuming that the *lo5-tree synthesis has performed a 3reat Lo+ and not
'alidating the realisti +eha'iour of the *lo5s. Atleast i would not do this.
I : good , 2ery 3ood.
I : what is the term lo5 - unertanity and why we need this, do you see a reason.
U : &here are so muh unertanity in lo5s, li5e lo5 Litter and there ould +e lot of
'ariations: lo5 'ariations, proess 'ariations , so some e1tra margin is required and it is
modeled with unertainity term.
I: 3ood , an i speify different unertanity 'alue for setup as well as hold.
U : Jes sire, there are pro'isions to do this, there are speifi swithes speifi for setup
and hold requirement.
I : we will onnet later, I need to ath up for a meeting.
What is the derate value that can be used?
=or setup he5 derate data path +y -Q to 6(Q, no derate in the lo5 path.
=or hold he5 derate lo5 path +y -Q to 6(Q, no derate in the data path.
What are the corners you check for timing signoff? Is there any changes in the
derate value for each corner?
*orners: >orst, 8est, &ypial.
Same derating 'alue for +est and worst.=or typial it an +e less.
Write Setup and #old equtions?
Setup equation: &launh lo5 S &l5-qPma1 S &om+oPma1 RK &apute lo5 -
#&setupSs5ew$
Iold equation: &launh lo5 S &l5-qPmin S &om+oPmin EK &apture lo5 S
#&hold-s5ew$
Where do you get the WL*5s? 'o you create WL*5s? #ow do you specify?
>ire @oad 9odels #>@9$ are a'aila+le from the li+rary 'endors.
>e dont reate >@9.
>@9s an +e speified depending on the area.
Where do you get the derating value? What are the factors that decide the derating
factor?
8ased on the guidelines and suggestions from the li+rary 'endor and pre'ious
design e1periene derating 'alue is deided.
P2& 'ariation is the fator that deides the derating fator.
What factors decides the setup time of flipflop?
D- pin transition and lo5 transition.
Why dont you derate the clock path by 678 for worst corner analysis?
>e an do. 8ut it may not +e aurate as the data path derate.
9ate delay
&ransistors within a gate ta5e a finite time to swith. &his means that a hange on
the input of a gate ta5es a finite time to ause a hange on the output.C9agmaF
3ate delay Kfuntion of#i.p transition time, *netS*pin$.
*ell delay is also same as 3ate delay.
Source 'elay :or Source Latency;
It is 5nown as soure lateny also. It is defined as Mthe delay from the lo5 origin
point to the lo5 definition point in the designM.
Delay from lo5 soure to +eginning of lo5 tree #i.e. lo5 definition point$.
&he time a lo5 signal ta5es to propagate from its ideal wa'eform origin point to
the lo5 definition point in the design.
1etwork 'elay:latency;
It is also 5nown as Insertion delay or "etwor5 lateny. It is defined as Mthe delay
from the lo5 definition point to the lo5 pin of the registerM.
&he time lo5 signal #rise or fall$ ta5es to propagate from the lo5 definition
point to a register lo5 pin.
Insertion delay
&he delay from the lo5 definition point to the lo5 pin of the register.
!ransition delay
It is also 5nown as MSlewM. It is defined as the time ta5en to hange the state of the
signal. &ime ta5en for the transition from logi 7 to logi 6 and 'ie 'ersa . or
&ime ta5en +y the input signal to rise from 67Q#27Q$ to the 47Q#-7Q$ and 'ie
'ersa.
&ransition is the time it ta5es for the pin to hange state.
Slew
Aate of hange of logi.See &ransition delay.
Slew rate is the speed of transition measured in 'olt . ns.
<ise !ime
Aise time is the differene +etween the time when the signal rosses a low
threshold to the time when the signal rosses the high threshold. It an +e a+solute
or perent.
@ow and high thresholds are fi1ed 'oltage le'els around the mid 'oltage le'el or
it an +e either 67Q and 47Q respeti'ely or 27Q and -7Q respeti'ely. &he
perent le'els are on'erted to a+solute 'oltage le'els at the time of measurement
+y alulating perentages from the differene +etween the starting 'oltage le'el
and the final settled 'oltage le'el.
&all !ime
=all time is the differene +etween the time when the signal rosses a high
threshold to the time when the signal rosses the low threshold.
&he low and high thresholds are fi1ed 'oltage le'els around the mid 'oltage le'el
or it an +e either 67Q and 47Q respeti'ely or 27Q and -7Q respeti'ely. &he
perent le'els are on'erted to a+solute 'oltage le'els at the time of measurement
+y alulating perentages from the differene +etween the starting 'oltage le'el
and the final settled 'oltage le'el.
=or an ideal square wa'e with (7Q duty yle, the rise time will +e 7.=or a
symmetri triangular wa'e, this is redued to Lust (7Q.
&he rise.fall definition is set on the meter to 67Q and 47Q +ased on the linear
power in >atts. &hese points translate into the -67 d8 and -7.( d8 points in log
mode #67 log 7.6$ and #67 log 7.4$. &he rise.fall time 'alues of 67Q and 47Q are
alulated +ased on an algorithm, whih loo5s at the mean power a+o'e and
+elow the (7Q points of the rise.fall times. *li5 here to see more.
/ath delay
Path delay is also 5nown as pin to pin delay. It is the delay from the input pin of
the ell to the output pin of the ell.
1et 'elay :or wire delay;
&he differene +etween the time a signal is first applied to the net and the time it
reahes other de'ies onneted to that net.
It is due to the finite resistane and apaitane of the net.It is also 5nown as wire
delay.
>ire delay Kfn#Anet , *netS*pin$
/ropagation delay
=or any gate it is measured +etween (7Q of input transition to the orresponding
(7Q of output transition.
&his is the time required for a signal to propagate through a gate or net. =or gates
it is the time it ta5es for a e'ent at the gate input to affet the gate output.
=or net it is the delay +etween the time a signal is first applied to the net and the
time it reahes other de'ies onneted to that net.
It is ta5en as the a'erage of rise time and fall time i.e. &pdK #&phlS&plh$.2.
/hase delay
Same as insertion delay
(ell delay
=or any gate it is measured +etween (7Q of input transition to the orresponding
(7Q of output transition.
Intrinsic delay
Intrinsi delay is the delay internal to the gate. Input pin of the ell to output pin
of the ell.
It is defined as the delay +etween an input and output pair of a ell, when a near
<ero slew is applied to the input pin and the output does not see any load
ondition.It is predominantly aused +y the internal apaitane assoiated with
its transistor.
&his delay is largely independent of the si<e of the transistors forming the gate
+eause inreasing si<e of transistors inrease internal apaitors.
%=trinsic delay
Same as wire delay, net delay, interonnet delay, flight time.
E1trinsi delay is the delay effet that assoiated to with interonnet. output pin
of the ell to the input pin of the ne1t ell.
Input delay
Input delay is the time at whih the data arri'es at the input pin of the +lo5 from
e1ternal iruit with respet to referene lo5.
,utput delay
/utput delay is time required +y the e1ternal iruit +efore whih the data has to
arri'e at the output pin of the +lo5 with respet to referene lo5.
%=it delay
It is defined as the delay in the longest path #ritial path$ +etween lo5 pad
input and an output. It determines the ma1imum operating frequeny of the
design.
Latency :pre0post cts;
@ateny is the summation of the Soure lateny and the "etwor5 lateny. Pre *&S
estimated lateny will +e onsidered during the synthesis and after *&S
propagated lateny is onsidered.
>ncertainty :pre0post cts;
;nertainty is the amount of s5ew and the 'ariation in the arri'al lo5 edge. Pre
*&S unertainty is lo5 s5ew and lo5 Uitter. After *&S we an ha'e some
margin of s5ew S Uitter.
>nateness
A funtion is said to +e unate if the rise transition on the positi'e unate input
'aria+le auses the ouput to rise or no hange and 'ie 'ersa.
"egati'e unateness means ell output logi is in'erted 'ersion of input logi. eg.
In in'erter ha'ing input A and output J, J is -'e unate w.r.to A. Positi'e unate
means ell output logi is same as that of input.
&hese S'e ad -'e unateness are onstraints defined in li+rary file and are defined
for output pin w.r.to some input pin.
A lo5 signal is positi'e unate if a rising edge at the lo5 soure an only ause
a rising edge at the register lo5 pin, and a falling edge at the lo5 soure an
only ause a falling edge at the register lo5 pin.
A lo5 signal is negati'e unate if a rising edge at the lo5 soure an only
ause a falling edge at the register lo5 pin, and a falling edge at the lo5 soure
an only ause a rising edge at the register lo5 pin. In other words, the lo5
signal is in'erted.
A lo5 signal is not unate if the lo5 sense is am+iguous as a result of non-unate
timing ars in the lo5 path. =or e1ample, a lo5 that passes through an D/A
gate is not unate +eause there are nonunate ars in the gate. &he lo5 sense
ould +e either positi'e or negati'e, depending on the state of the other input to
the D/A gate.
?itter
&he short-term 'ariations of a signal with respet to its ideal position in time.
Uitter is the 'ariation of the lo5 period from edge to edge. It an 'arry S.- Litter
'alue.
=rom yle to yle the period and duty yle an hange slightly due to the lo5
generation iruitry. &his an +e modeled +y adding unertainty regions around
the rising and falling edges of the lo5 wa'eform.
Sources of ?itter *ommon soures of Litter inlude:
Internal iruitry of the phase-lo5ed loop #P@@$
Aandom thermal noise from a rystal
/ther resonating de'ies
Aandom mehanial noise from rystal 'i+ration
Signal transmitters
&raes and a+les
*onnetors
Aeei'ers
Skew
&he differene in the arri'al of lo5 signal at the lo5 pin of different flops.
&wo types of s5ews are defined: @oal s5ew and 3lo+al s5ew.
Local skew
&he differene in the arri'al of lo5 signal at the lo5 pin of related flops.
9lobal skew
&he differene in the arri'al of lo5 signal at the lo5 pin of non related flops.
S5ew an +e positi'e or negati'e.
>hen data and lo5 are routed in same diretion then it is /ositive skew.
>hen data and lo5 are routed in opposite then it is negative skew.
<ecovery !ime
Aeo'ery speifies the minimum time that an asynhronous ontrol input pin
must +e held sta+le after +eing de-asserted and +efore the ne1t lo5 #ati'e-edge$
transition.
Aeo'ery time speifies the time the inati'e edge of the asynhronous signal has
to arri'e +efore the losing edge of the lo5.
Aeo'ery time is the minimum length of time an asynhronous ontrol signal
#eg.preset$ must +e sta+le +efore the ne1t ati'e lo5 edge. &he reo'ery sla5
time alulation is similar to the lo5 setup sla5 time alulation, +ut it applies
asynhronous ontrol signals.
Equation 6:
Aeo'ery Sla5 &ime K Data Aequired &ime XYV Data Arri'al &ime
Data Arri'al &ime K @aunh Edge S *lo5 "etwor5 Delay to Soure Aegister S
&l5qS Aegister to Aegister Delay
Data Aequired &ime K @ath Edge S *lo5 "etwor5 Delay to Destination
Aegister K&setup
If the asynhronous ontrol is not registered, equations shown in Equation 2 is used to
alulate the reo'ery sla5 time. Equation 2:
Aeo'ery Sla5 &ime K Data Aequired &ime XYV Data Arri'al &ime
Data Arri'al &ime K @aunh Edge S 9a1imum Input Delay S Port to Aegister
Delay
Data Aequired &ime K @ath Edge S *lo5 "etwor5 Delay to Destination
Aegister DelayS&setup
If the asynhronous reset signal is from a port #de'ie I./$, you must ma5e an
Input 9a1imum Delay assignment to the asynhronous reset pin to perform
reo'ery analysis on that path.
<emoval !ime
Aemo'al speifies the minimum time that an asynhronous ontrol input pin must
+e held sta+le +efore +eing de-asserted and after the pre'ious lo5 #ati'e-edge$
transition.
Aemo'al time speifies the length of time the ati'e phase of the asynhronous
signal has to +e held after the losing edge of lo5.
Aemo'al time is the minimum length of time an asynhronous ontrol signal must
+e sta+le after the ati'e lo5 edge. *alulation is similar to the lo5 hold sla5
alulation, +ut it applies asynhronous ontrol signals. If the asynhronous
ontrol is registered, equations shown in Equation ! is used to alulate the
remo'al sla5 time.
If the reo'ery or remo'al minimum time requirement is 'iolated, the output of
the sequential ell +eomes unertain. &he unertainty an +e aused +y the 'alue
set +y the reset+ar signal or the 'alue lo5ed into the sequential ell from the
data input.
Equation !
Aemo'al Sla5 &ime K Data Arri'al &ime XYV Data Aequired &ime
Data Arri'al &ime K @aunh Edge S *lo5 "etwor5 Delay to Soure Aegister S
&l5q of Soure Aegister S Aegister to Aegister Delay
Data Aequired &ime K @ath Edge S *lo5 "etwor5 Delay to Destination
Aegister S &hold
If the asynhronous ontrol is not registered, equations shown in Equation % is
used to alulate the remo'al sla5 time.
Equation %
Aemo'al Sla5 &ime K Data Arri'al &ime XYV Data Aequired &ime
Data Arri'al &ime K @aunh Edge S Input 9inimum Delay of Pin S 9inimum
Pin to Aegister Delay
Data Aequired &ime K @ath Edge S *lo5 "etwor5 Delay to Destination
Aegister S&hold
If the asynhronous reset signal is from a de'ie pin, you must speify the Input
9inimum Delay onstraint to the asynhronous reset pin to perform a remo'al
analysis on this path.
What is the difference between soft macro and hard macro?
What is the difference between hard macro3 firm macro and soft macro?
or
What are I/s?
Iard maro, firm maro and soft maro are all 5nown as IP #Intelletual
property$. &hey are optimi<ed for power, area and performane. &hey an +e
purhased and used in your ASI* or =P3A design implementation flow. Soft
maro is fle1i+le for all type of ASI* implementation. Iard maro an +e used in
pure ASI* design flow, not in =P3A flow. 8efore +ying any IP it is 'ery
important to e'aluate its ad'antages and disad'antages o'er eah other, hardware
ompati+ility suh as I./ standards with your design +lo5s, reusa+ility for other
designs.
Soft macros
Soft maros are in synthesi<a+le A&@.
Soft maros are more fle1i+le than firm or hard maros.
Soft maros are not speifi to any manufaturing proess.
Soft maros ha'e the disad'antage of +eing somewhat unpredita+le in terms of
performane, timing, area, or power.
Soft maros arry greater IP protetion ris5s +eause A&@ soure ode is more
porta+le and therefore, less easily proteted than either a netlist or physial layout
data.
=rom the physial design perspeti'e, soft maro is any ell that has +een plaed
and routed in a plaement and routing tool suh as Astro. #&his is the definition
gi'en in Astro Aail user manual T$
Soft maros are edita+le and an ontain standard ells, hard maros, or other soft
maros.
&irm macros
=irm maros are in netlist format.
=irm maros are optimi<ed for performane.area.power using a speifi
fa+riation tehnology.
=irm maros are more fle1i+le and porta+le than hard maros.
=irm maros are prediti'e of performane and area than soft maros.
#ard macro
Iard maros are generally in the form of hardware IPs #or we termed it as
hardwre IPs T$.
Iard maos are targeted for speifi I* manufaturing tehnology.
Iard maros are +lo5 le'el designs whih are silion tested and pro'ed.
Iard maros ha'e +een optimi<ed for power or area or timing.
In physial design you an only aess pins of hard maros unli5e soft maros
whih allows us to manipulate in different way.
Jou ha'e freedom to mo'e, rotate, flip +ut you an0t touh anything inside hard
maros.
2ery ommon e1ample of hard maro is memory. It an +e any design whih
arries dediated single funtionality #in general$.. for e1ample it an +e a 9P%
deoder.
8e aware of features and harateristis of hard maro +efore you use it in your
design... other than power, timing and area you also should 5now pin properties
li5e syn pin, I./ standards et
@E=, 3DS2 file format allows easy usage of maros in different tools.
=rom the physial design #+a5end$ perspeti'e:
Iard maro is a +lo5 that is generated in a methodology other than plae and
route #i.e. using full ustom design methodology$ and is +rought into the physial
design data+ase #eg. 9il5yway in SynopsysZ 2olano in 9agma$ as a 3DS2 file.
Synthesis and plaement of maros in modern So* designs are hallenging. EDA tools
employ different algorithms aomplish this tas5 along with the target of power and area.
&here are se'eral researh papers a'aila+le on these su+Lets.
What is the difference between &/9" and (/L'?
=P3A-=ield Programma+le 3ate Array and *P@D-*omple1 Programma+le @ogi
De'ie-- +oth are programma+le logi de'ies made +y the same ompanies with
different harateristis.
MA *omple1 Programma+le @ogi De'ie #*P@D$ is a Programma+le @ogi
De'ie with omple1ity +etween that of PA@s #Programma+le Array @ogi$ and
=P3As, and arhitetural features of +oth. &he +uilding +lo5 of a *P@D is the
maro ell, whih ontains logi implementing disLunti'e normal form
e1pressions and more speiali<ed logi operationsM.
&his is what >i5i defines.....TT
"rchitecture
3ranularity is the +iggest differene +etween *P@D and =P3A.
=P3A are Mfine-grainM de'ies. &hat means that they ontain hundreds of #up to
677777$ of tiny +lo5s #alled as @;& or *@8s et$ of logi with flip-flops,
om+inational logi and memories.=P3As offer muh higher omple1ity, up to
6(7,777 flip-flops and large num+er of gates a'aila+le.
*P@Ds typially ha'e the equi'alent of thousands of logi gates, allowing
implementation of moderately ompliated data proessing de'ies. PA@s
typially ha'e a few hundred gate equi'alents at most, while =P3As typially
range from tens of thousands to se'eral million.
*P@D are Moarse-grainM de'ies. &hey ontain relati'ely few #a few 6770s ma1$
large +lo5s of logi with flip-flops and om+inational logi. *P@Ds +ased on
A"D-/A struture.
*P@D0s ha'e a register with assoiated logi #A"D./A matri1$. *P@D0s are
mostly implemented in ontrol appliations and =P3A0s in datapath appliations.
8eause of this ourse grained arhiteture, the timing is 'ery fi1ed in *P@Ds.
=P3A are AA9 +ased. &hey need to +e MdownloadedM #onfigured$ at eah
power-up. *P@D are EEPA/9 +ased. &hey are ati'e at power-up i.e. as long as
they0'e +een programmed at least one.
=P3A needs +oot A/9 +ut *P@D does not. In some systems you might not ha'e
enough time to +oot up =P3A then you need *P@DS=P3A.
3enerally, the *P@D de'ies are not 'olatile, +eause they ontain flash or
erasa+le A/9 memory in all the ases. &he =P3A are 'olatile in many ases and
hene they need a onfiguration memory for wor5ing. &here are some =P3As
now whih are non'olatile. &his distintion is rapidly +eoming less rele'ant, as
se'eral of the latest =P3A produts also offer models with em+edded
onfiguration memory.
&he harateristi of non-'olatility ma5es the *P@D the de'ie of hoie in
modern digital designs to perform 0+oot loader0 funtions +efore handing o'er
ontrol to other de'ies not ha'ing this apa+ility. A good e1ample is where a
*P@D is used to load onfiguration data for an =P3A from non-'olatile memory.
8eause of oarse-grain arhiteture, one +lo5 of logi an hold a +ig equation
and hene *P@D ha'e a faster input-to-output timings than =P3A.
*li5 here to read one good artile.
&eatures
=P3A ha'e speial routing resoures to implement +inary ounters,arithmeti
funtions li5e adders, omparators and AA9. *P@D don0t ha'e speial features
li5e this.
=P3A an ontain 'ery large digital designs, while *P@D an ontain small
designs only.&he limited omple1ity #R(77E
Speed: *P@Ds offer a single-hip solution with fast pin-to-pin delays, e'en for
wide input funtions. ;se *P@Ds for small designs, where Minstant-onM, fast and
wide deoding, ultra-low idle power onsumption, and design seurity are
important #e.g., in +attery-operated equipment$.
Security: In *P@D one programmed, the design an +e lo5ed and thus made
seure. Sine the onfiguration +itstream must +e reloaded e'ery time power is re-
applied, design seurity in =P3A is an issue.
Power: &he high stati #idle$ power onsumption prohi+its use of *P@D in
+attery-operated equipment. =P3A idle power onsumption is reasona+ly low,
although it is sharply inreasing in the newest families.
Design flexibility: =P3As offer more logi fle1i+ility and more sophistiated
system features than *P@Ds: lo5 management, on-hip AA9, DSP funtions,
#multipliers$, and e'en on-hip miroproessors and 9ulti-3iga+it
&ransei'ers.&hese +enefits and opportunities of dynami reonfiguration, e'en in
the end-user system, are an important ad'antage.
;se =P3As for larger and more omple1 designs.
=P3A is suited for timing iruit +eaue they ha'e more registers , +ut *P@D is
suited for ontrol iruit +eause they ha'e more om+inational iruit. At the
same time, If you synthesis the same ode for =P3A for many times, you will find
out that eah timing report is different. 8ut it is different in *P@D synthesis, you
an get the same result.
As *P@Ds and =P3As +eome more ad'aned the differenes +etween the two de'ie
types will ontinue to +lur. >hile this trend may appear to ma5e the two types more
diffiult to 5eep apart, the arhitetural ad'antage of *P@Ds om+ining low ost, non-
'olatile onfiguration, and maro ells with predita+le timing harateristis will li5ely
+e suffiient to maintain a produt differentiation for the foreseea+le future.
Ioping that information and referenes helps you ....... omments and further referenes
are welome T
What is the difference between &/9" and "SI(?
&his question is 'ery popular in 2@SI fresher inter'iews. It loo5s simple +ut a
deeper insight into the su+Let re'eals the fat that there are lot of thin5s to +e
understood TT So here is the answer.
&/9" vs. "SI(
Differene +etween ASI*s and =P3As mainly depends on osts, tool a'aila+ility,
performane and design fle1i+ility. &hey ha'e their own pros and ons +ut it is
designers responsi+ility to find the ad'antages of the eah and use either =P3A or
ASI* for the produt. Iowe'er, reent de'elopments in the =P3A domain are
narrowing down the +enefits of the ASI*s.
&/9"
&ield /rogramable 9ate "rrays
&/9" 'esign "dvantages
Faster time-to-market: "o layout, mas5s or other manufaturing steps are needed
for =P3A design. Aeadymade =P3A is a'aila+le and +urn your ID@ ode to
=P3A T Done TT
1o 1<% :1on <ecurring %=penses;2 &his ost is typially assoiated with an
ASI* design. =or =P3A this is not there. =P3A tools are heap. #sometimes its
free T Jou need to +uy =P3A.... thats all T$. ASI* youpay huge "AE and tools are
e1pensi'e. I would say M'ery e1pensi'eM...Its in rores....TT
Simpler design cycle: &his is due to software that handles muh of the routing,
plaement, and timing. 9anual inter'ention is less.&he =P3A design flow
eliminates the omple1 and time-onsuming floorplanning, plae and route,
timing analysis.
More predictable project cycle: &he =P3A design flow eliminates potential re-
spins, wafer apaities, et of the proLet sine the design logi is already
synthesi<ed and 'erified in =P3A de'ie.
Field Reprogramability: A new +itstream # i.e. your program$ an +e uploaded
remotely, instantly. =P3A an +e reprogrammed in a snap while an ASI* an ta5e
[(7,777 and more than %-) wee5s to ma5e the same hanges. =P3A osts start
from a ouple of dollars to se'eral hundreds or more depending on the hardware
features.
Reusability: Aeusa+ility of =P3A is the main ad'antage. Prototype of the design
an +e implemented on =P3A whih ould +e 'erified for almost aurate results
so that it an +e implemented on an ASI*. Ifdesign has faults hange the ID@
ode, generate +it stream, program to =P3A and test again.9odern =P3As are
reonfigura+le +oth partially and dynamially.
=P3As are good for prototyping and limited prodution.If you are going to ma5e
677-277 +oards it isn0t worth to ma5e an ASI*.
3enerally =P3As are used for lower speed, lower omple1ity and lower 'olume
designs.8ut today0s =P3As e'en run at (77 9I< with superior performane. >ith
unpreedented logi density inreases and a host of other features, suh as
em+edded proessors, DSP +lo5s, lo5ing, and high-speed serial at e'er lower
prie, =P3As are suita+le for almost any type of design.
;nli5e ASI*s, =P3A0s ha'e speial hardwares suh as 8lo5-AA9, D*9
modules, 9A*s, memories and highspeed I./, em+edded *P; et in+uilt, whih
an +e used to get +etter performae. 9odern =P3As are pa5ed with features.
Ad'aned =P3As usually ome with phase-lo5ed loops, low-'oltage differential
signal, lo5 data reo'ery, more internal routing, high speed, hardware
multipliers for DSPs, memory,programma+le I./, IP ores and miroproessor
ores. Aemem+er Power P* #hardore$ and 9iro+la<e #softore$ in Dilin1 and
AA9 #hardore$ and "ios#softore$ in Altera. &here are =P3As a'aila+le now
with +uilt in AD* T ;sing all these features designers an +uild a system on a
hip. "ow, dou yo really need an ASI* ?
=P3A sythesis is muh more easier than ASI*.
In =P3A you need not do floor-planning, tool an do it effiiently. In ASI* you
ha'e do it.
&/9" 'esign 'isadvantages
Powe onsumption in =P3A is more. Jou don0t ha'e any ontrol o'er the power
optimi<ation. &his is where ASI* wins the rae T
Jou ha'e to use the resoures a'aila+le in the =P3A. &hus =P3A limits the
design si<e.
3ood for low quantity prodution. As quantity inreases ost per produt
inreases ompared to the ASI* implementation.
"SI(
"pplication Specific Intergrated (irciut
"SI( 'esign "dvantages
ost!!!!cost!!!!cost!!!!"ower unit costs: =or 'ery high 'olume designs osts omes
out to +e 'ery less. @arger 'olumes of ASI* design pro'es to +e heaper than
implementing design using =P3A.
Speed!!!speed!!!speed!!!!#S$s are faster t%an FP&#: ASI* gi'es design
fle1i+ility. &his gi'es enoromous opportunity for speed optimi<ations.
"ow power!!!!"ow power!!!!"ow power: ASI* an +e optimi<ed for required low
power. &here are se'eral low power tehniques suh as power gating, lo5
gating, multi 't ell li+raries, pipelining et are a'aila+le to ahie'e the power
target. &his is where =P3A fails +adly TTT *an you thin5 of a ell phone whih has
to +e harged for e'ery all.....ne'er.....low power ASI*s helps +attery li'e longer
life TT
In ASI* you an implement analog iruit, mi1ed signal designs. &his is generally
not possi+le in =P3A.
In ASI* D=& #Design =or &est$ is inserted. In =P3A D=& is not arried out
#rather for =P3A no need of D=& T$ .
"SI( 'esign 'iadvantages
'ime-to-market: Some large ASI*s an ta5e a year or more to design. A good
way to shorten de'elopment time is to ma5e prototypes using =P3As and then
swith to an ASI*.
Design $ssues: In ASI* you should ta5e are of D=9 issues, Signal Integrity
isuues and many more. In =P3A you don0t ha'e all these +eause ASI* designer
ta5es are of all these. # Don0t forget =P3A isan I* and designed +y ASI* design
enginner TT$
(xpensi)e 'ools: ASI* design tools are 'ery muh e1pensi'e. Jou spend a huge
amount of "AE.
Structured "SI(S
Strutured ASI*s ha'e the +ottom metal layers fi1ed and only the top layers an
+e designed +y the ustomer.
Strutured ASI*s are ustom de'ies that approah the performane of today0s
Standard *ell ASI* while dramatially simplifying the design omple1ity.
Strutured ASI*s offer designers a set of de'ies with speifi, ustomi<a+le
metal layers along with predefined metal layers, whih an ontain the underlying
pattern of logi ells, memory, and I./.
"SI( 'esign (heck List
Silicon /rocess and Library (haracteristics
>hat e1at proess are you using?
Iow many layers an +e used for this design?
Are the *ross tal5 "oise onstraints, Dtal5 Analysis onfiguration, *ell E9 B
>ire E9 a'aila+le?
'esign (haracteristics
>hat is the design appliation?
"um+er of ells #plaea+le o+Lets$?
Is the design 2erilog or 2ID@?
Is the netlist flat or hierarhial?
Is there A&@ a'aila+le?
Is there any datapath logi using speial datapath tools?
Is the D=& to +e onsidered?
*an san hains +e reordered?
Is memory 8IS&, +oundary san used on this design?
Are stati timing analysis onstraints a'aila+le in SD* format?
(lock (haracteristics
Iow many lo5 domains are in the design?
>hat are the lo5 frequenies?
Is there a target lo5 s5ew, lateny or other lo5 requirements?
Does the design ha'e a P@@?
If so, is it used to remo'e lo5 lateny?
Is there any I./ ell in the feed+a5 path?
Is the P@@ used for frequeny multipliers?
Are there deri'ed lo5s or omple1 lo5 generation iruitry?
Are there any gated lo5s?
If yes, do they use simple gating elements?
Is the gate lo5 used for timing or power?
=or gated lo5s, an the gating elements +e si<ed for timing?
Are you mu1ing in a test lo5 or using a U&A3 lo5?
A'aila+le ells for lo5 tree?
Are there any speial lo5 repeaters in the li+rary?
Are there any E9, slew or apaitane limits on these repeaters?
Iow many dri'e strengths are a'aila+le in the standard +uffers and in'erters?
Do any of the +uffers ha'e +alaned rise and fall delays?
Any there speial requirements for lo5 distri+ution?
>ill the lo5 tree +e shielded? If so, what are the shielding requirements?
&loorplan and /ackage (haracteristics
&arget die area?
Does the area estimate inlude power.signal routing?
>hat gates.mm2 has +een assumed?
"um+er of routing layers?
Any speial power routing requirements?
"um+er of digital I./ pins.pads?
"um+er of analog signal pins.pads?
"um+er of power.ground pins.pads?
&otal num+er of pins.pads and @oation?
>ill this hip use a wire +ond pa5age?
>ill this hip use a flip-hip pa5age?
If Jes, is it I./ +ump pith? Aows of +umps? 8ump alloation?8ump pad layout
guide?
Ia'e you already done floorplanning for this design?
If yes, is onformane to the e1isting floorplan required?
>hat is the target die si<e?
>hat is the e1peted utili<ation?
Please draw the o'erall floorplan ?
Is there an e1isting floorplan a'aila+le in DE=?
>hat are the num+er and type of maros #memory, P@@, et.$?
Are there any analog +lo5s in the design?
>hat 5ind of pa5aging is used? =liphip?
Are the I./s periphery I./ or area I./?
Iow many I./s?
Is the design pad limited?
Power planning and Power analysis for this design?
Are layout data+ases a'aila+le for hard maros ?
&iming analysis and orrelatio?
Physial 'erifiation ?
'ata Input
@i+rary information for new li+rary
.li+ for timing information
3DSII or @E= for li+rary ells inluding any AA9s
A&@ in 2erilog.2ID@ format
"um+er of logial +lo5s in the A&@
*onstraints for the +lo5 in SD*
=loorplan information in DE=
I./ pin loation
9aro loations
In scan chains if some flip flops are @ve edge triggered and remaining flip
flops are ve edge triggered how it behaves?
Answer:
=or designs with +oth positi'e and negati'e lo5ed flops, the san insertion tool will
always route the san hain so that the negati'e lo5ed flops ome +efore the positi'e
edge flops in the hain. &his a'oids the need of lo5up lath.
=or the same lo5 domain the negedge flops will always apture the data Lust aptured
into the posedge flops on the posedge of the lo5.
=or the multiple lo5 domains, it all depends upon how the lo5 trees are +alaned. If
the lo5 domains are ompletely asynhronous, A&P3 has to mas5 the reei'ing flops.
What you mean by scan chain reordering?
"nswer62
8ased on timing and ongestion the tool optimally plaes standard ells. >hile doing so,
if san hains are detahed, it an +rea5 the hain ordering #whih is done +y a san
insertion tool li5e D=& ompiler from Synopsys$ and an reorder to optimi<e it.... it
maintains the num+er of flops in a hain.
"nswerA2
During plaement, the optimi<ation may ma5e the san hain diffiult to route due to
ongestion. Iene the tool will re-order the hain to redue ongestion.
&his sometimes inreases hold time pro+lems in the hain. &o o'erome these +uffers
may ha'e to +e inserted into the san path. It may not +e a+le to maintain the san hain
length e1atly. It annot swap ell from different lo5 domains.
8eause of san hain reordering patterns generated earlier is of no use. 8ut this is not a
pro+lem as A&P3 an +e redone +y reading the new netlist.
What is the difference between a latch and a flipflop?
8oth lathes and flip-flops are iruit elements whose output depends not only on
the present inputs, +ut also on pre'ious inputs and outputs.
&hey +oth are hene referred as MsequentialM elements.
In eletronis, a lath, is a 5ind of +ista+le multi 'i+rator, an eletroni iruit
whih has two sta+le states and there+y an store one +it of of information. &oday
the word is mainly used for simple transparent storage elements, while slightly
more ad'aned non-transparent #or lo5ed$ de'ies are desri+ed as flip-flops.
Informally, as this distintion is quite new, the two words are sometimes used
interhangea+ly. Cwi5iF
In digital iruits, a flip-flop is a 5ind of +ista+le multi 'i+rator, an eletroni
iruit whih has two sta+le states and there+y is apa+le of ser'ing as one +it of
memory. &oday, the term flip-flop has ome to generally denote non-transparent
#lo5ed or edge-triggered$ de'ies, while the simpler transparent ones are often
referred to as lathes.Cwi5iF
A flip-flop is ontrolled +y #usually$ one or two ontrol signals and.or a gate or
lo5 signal.
@athes are le'el sensiti'e i.e. the output aptures the input when the lo5 signal
is high, so as long as the lo5 is logi 6, the output an hange if the input also
hanges.
=lip-=lops are edge sensiti'e i.e. flip flop will store the input only when there is a
rising or falling edge of the lo5.
A positi'e le'el lath is transparent to the positi'e le'el#ena+le$, and it lathes the
final input +efore it is hanging its le'el#i.e. +efore ena+le goes to 070 or +efore the
lo5 goes to -'e le'el.$
A positi'e edge flop will ha'e its output effeti'e when the lo5 input hanges
from 070 to 060 state #060 to 070 for negati'e edge flop$ only.
@athes are faster, flip flops are slower.
@ath is sensiti'e to glithes on ena+le pin, whereas flip-flop is immune to
glithes.
@athes ta5e less gates #less power$ to implement than flip-flops.
D-== is +uilt from two lathes. &hey are in master sla'e onfiguration.
@ath may +e lo5ed or lo5 less. 8ut flip flop is always lo5ed.
=or a transparent lath generally D to H propagation delay is onsidered while for
a flop lo5 to H and setup and hold time are 'ery important.
Synthesis perspective2 /ros and (ons of Latches and &lip &lops
In synthesis of ID@ odes inappropriate oding an infer lathes instead of flip
flops. Eg.:MifM and MaseM statements. &his should +e a'oided sa lathes are more
prone to glithes.
@ath ta5es less area, =lip-flop ta5es more area # as flip flop is made up of
lathes$ .
@ath failitate time +orrowing or yle stealing whereas flip flops allow
synhronous logi.
@athes are not friendly with D=& tools. 9inimi<e inferring of lathes if your
design has to +e made testa+le. Sine ena+le signal to lath is not a regular lo5
that is fed to the rest of the logi. &o ensure testa+ility, you need to use /A gate
using Mena+leM and MsanPena+leM signals as input and feed the output to the
ena+le port of the lath. CrefF
9ost EDA software tools ha'e diffiulty with lathes. Stati timing analy<ers
typially ma5e assumptions a+out lath transpareny. If one assumes the lath is
transparent #i.e.triggered +y the ati'e time of lo5,not triggered +y Lust lo5
edge$, then the tool may find a false timing path through the input data pin. If one
assumes the lath is not transparent, then the tool may miss a ritial path.
If target tehnology supports a lath ell then rae ondition pro+lems are
minimi<ed. If target tehnology does not support a lath then synthesis tool will
infer it +y +asi gates whih is prone to rae ondition. &hen you need to add
redundant logi to o'erome this pro+lem. 8ut while optimi<ation redundant logi
an +e remo'ed +y the synthesis tool T &his will reate endless pro+lems for the
design team.
Due to the transpareny issue, lathes are diffiult to test. =or san testing, they
are often replaed +y a lath-flip-flop ompati+le with the san-test shift-register.
;nder these onditions, a flip-flop would atually +e less e1pensi'e than a lath.
Aead a good artile on pro+lems of lath pu+lished in eetimes long +a5 TT
=lip flops are friendly with D=& tools. San insertion for synhronous logi is
hassle free.
'igital design Interview 4uestions
If in'erted output of D flip-flop is onneted to its input how the flip-flop
+eha'es?
Design a iruit to di'ide input frequeny +y 2?
Design a di'ide +y two ounter using D-@ath.
Design a di'ide-+y-! sequential iruit with (7Q duty yle.
>hat are the different types of adder implementation?
Draw a &ransmission 3ate-+ased D-@ath?
3i'e the truth ta+le for a Ialf Adder. 3i'e a gate le'el implementation of the
same.
Design an /A gate from 2:6 9;D.
>hat is the differene +etween a @A&*I and a =@IP-=@/P?
Design a D =lip-=lop from two lathes.
Design a 2 +it ounter using D =lip-=lop.
>hat are the two types of delays in any digital system
Design a &ransparent @ath using a 2:6 9u1.
Design a %:6 9u1 using 2:6 9u10s.
>hat is metasta+le state? Iow does it our?
>hat is metasta+lity?
Design a !:- deoder
Design a =S9 to detet sequene M676M in input sequene
*on'ert "A"D gate into In'erter in two different ways.
Design a D and & flip flop using 2:6 mu1 only.
Design D @ath from SA flip-flop.
Define *lo5 S5ew, "egati'e *lo5 S5ew, Positi'e *lo5 S5ew?
>hat is rae ondition? Iow it ours? Iow to a'oid it?
Design a % +it 3ray *ounter?
Design %-+it synhronous ounter, asynhronous ounter?
Design a 6) +yte asynhronous =I=/?
>hat is the differene +etween a EEPA/9 and =@ASI?
>hat is the differene +etween a "A"D-+ased =lash and "/A-+ased =lash?
>hih one is good: asynhronous reset or synhronous reset? >hy?
Design a simple iruit +ased on om+inational logi to dou+le the output
frequeny.
>hat is the differene +etween flip-flop and lath?
Implement omparator using om+inational logi, that ompares two 2-+it
num+ers A and 8. &he omparator should ha'e ! outputs: A E 8, A R a KM 8.ME
3i'e two ways of on'erting a two input "A"D gate to an in'erter?
>hat is the differene +etween mealy and moore state-mahines?
>hat is the differene +etween lath +ased design and flip-flop +ased design?
>hat is metasta+ility and how to pre'ent it?
Design a four-input "A"D gate using only two-input "A"D gates.
>hy are most interrupts ati'e low?
Iow do you detet if two --+it signals are same?
, +it ring ounter0s initial state is 7677767. After how many lo5 yles will it
return to the initial state?
Design all the +asi gates "/&, A"D, /A, "A"D, "/A, D/A, D"/A using 2:6
9ultiple1er.
Iow will you implement a full su+trator from a full adder?
In a !-+it Uohnson0s ounter what are the unused states?
>hat is differene +etween AA9 and =I=/?
>hat is an @=SA? @ist a few of its industry appliations.
Implement the following iruits: #a$ ! input "A"D gate using minimum num+er
of 2 input "A"D gates #+$ ! input "/A gate using minimum num+er of 2 input
"/A gates #$ ! input D"/A gate using minimum num+er of 2 input D"/A
gates assuming ! inputs A,8,*?
Design a D-lath using #a$ using 2:6 9u1 #+$ from S-A @ath?
Iow to implement a 9aster Sla'e flip flop using a 2 to 6 mu1?
Iow many 2 input 1or0s are needed to inplement 6) input parity generator?
*on'ert 1or gate to +uffer and in'erter.
Differene +etween onehot and +inary enoding?
>hat are different ways to synhroni<e +etween two lo5 domains?
Iow to alulate ma1imum operating frequeny?
Iow to find out longest path?
Iow to ahie'e 6-7 degree e1at phase shift?
>hat is signifiane of ras and as in SDAA9?
&ell some of appliations of +uffer?
Implement an A"D gate using mu1?
>hat will happen if ontents of register are shifter left, right?
>hat is the +asi differene +etween analog and digital design?
>hat ad'antages do synhronous ounters ha'e o'er asynhronous ounters?
>hat types of flip-flops an +e used to implement the memory elements of a
ounter?
>hat are the ad'antages of using a miroproessor to implement a ounter rather
than the on'entional method #flip-flop and logi gates$?
>hat is the prinipal ad'antage of 3ray *ode o'er straight #on'entional$ +inary?
>hat does Pipelining do?
Design di'ide +y 2, di'ide +y ! iruit with equal duty yle.
Iow many %:6 mu1 do you need to design a -:6 mu1?
>hat is D->ord, H-word?
Define 9oore, 9ealy state mahines. >hih one is good for timing?
Design a =S9 to detet 67667. >hat is the minimum num+er of flops required?
Design a simple iruit +ased on om+inational logi to dou+le the output
frequeny.
Design a 2+it up.down ounter with lear using gates. #"o 'erilog or 'hdl$
Design a finite state mahine to gi'e a modulo ! ounter when 1K7 and modulo %
ounter when 1K6.
9inimi<e: SK A0 S A8
>hat is the funtion of a D-flipflop, whose in'erted outputs are onneted to its
input?
Iow to synhroni<e ontrol signals and data +etween two different lo5
domains?
Desri+e a finite state mahine that will detet three onseuti'e oin tosses #of
one oin$ that results in heads.
In what ases do you need to dou+le lo5 a signal +efore presenting it to a
synhronous state mahine?
Iow many +it om+inations are there in a +yte?
>hat are the different Adder iruits you studied?
3i'e the truth ta+le for a Ialf Adder. 3i'e a gate le'el implementation of the
same.
*on'ert )(#Ie1$ to 8inary
*on'ert a num+er to its two0s ompliment and +a5.
>hat is the 60s and 20s omplement of the deimal num+er 2(.
If A?8K* and *?AK8 then what is the +oolean operator ?
/hysical 'esign ,bBective !ype of 4uestions and "nswers
6; (hip utili)ation depends on CCC.
a. /nly on standard ells +. Standard ells and maros . /nly on maros d. Standard
ells maros and I/ pads
A; In Soft blockages CCCC cells are placed.
a. /nly sequential ells +. "o ells . /nly 8uffers and In'erters d. Any ells
D; Why we have to remove scan chains before placement?
a. 8eause san hains are group of flip flop +. It does not ha'e timing ritial path . It is
series of flip flop onneted in =I=/ d. "one
E; 'ealy between shortest path and longest path in the clock is called CCCC.
a. ;seful s5ew +. @oal s5ew . 3lo+al s5ew d. Sla5
F; (ross talk can be avoided by CCC.
a. Dereasing the spaing +etween the metal layers +. Shielding the nets . ;sing lower
metal layes d. ;sing long nets
G; /rerouing means rouing of CCCCC.
a. *lo5 nets +. Signal nets . I/ nets d. P3 nets
H; Which of the following metal layer has *a=imum resistance?
a. 9etal6 +. 9etal2 . 9etal! d. 9etal%
I; What is the goal of (!S?
a. 9inimum IA Drop +. 9inimum E9 . 9inimum S5ew d. 9inimum Sla5
J; >sually #old is fi=ed CCC.
a. 8efore Plaement +. After Plaement . 8efore *&S d. After *&S
67; !o achive better timing CCCC cells are placed in the critical path.
a. I2& +. @2& . A2& d. S2&
66; Leakage power is directly propotional to CCC.
a. =requeny +. @oad *apaitane . Supply 'oltage d. &hreshold 2oltage
6A; &iller cells are added CCC.
a. 8efore Plaement of std ells +. After Plaement of Std *ells . 8efore =loorplanning
d. 8efore Detil Aouting
6D; Search and <epair is used for CCC.
a. Aeduing IA Drop +. Aeduing DA* . Aeduing E9 'oilations d. "one
6E; *a=imum current density of a metal is available in CCC.
a. .li+ +. .' . .tf d. .sd
6F; *ore I< drop is due to CCC.
a. Inrease in metal width +. Inrease in metal length . Derease in metal length d. @ot of
metal layers
6G; !he minimum height and width a cell can occupy in the design is called
as CCC.
a. ;nit &ile ell +. 9ulti heighted ell . @2& ell d. I2& ell
6H; (</< stands for CCC.
a. *ell *on'ergene Pessimism Aemo'al +. *ell *on'ergene Preset Aemo'al . *lo5
*on'ergene Pessimism Aemo'al d. *lo5 *on'ergene Preset Aemo'al
6I; In ,(V timing check3 for setup time3 CCC.
a. 9a1 delay is used for launh path and 9in dealy for apture path +. 9in delay is used
for launh path and 9a1 dealy for apture path . 8oth 9a1 dealy is used for launh and
*apture path d. 8oth 9in dealy is used for +oth *apture and @auh paths
6J; K!otal metal area and:or; perimeter of conducting layer 0 gate to gate
areaK is called CCC.
a. ;tili<ation +. Aspet Aatio . /*2 d. Antenna Aatio
A7; !he Solution for "ntenna effect is CCC.
a. Diode insertion +. Shielding . 8uffer insertion d. Dou+le spaing
A6; !o avoid cross talk3 the shielded net is usually connected to CCC.
a. 2DD +. 2SS . 8oth 2DD and 2SS d. *lo5
AA; If the data is faster than the clock in <eg to <eg path CCC violation may
come.
a. Setup +. Iold . 8oth d. "one
AD; #old violations are prefered to fi= CCC.
a. 8efor plaement +. After plaement . 8efore *&S d. After*&S
AE; Which of the following is not present in S'( CCC?
a. 9a1 tran +. 9a1 ap . 9a1 fanout d. 9a1 urrent density
AF; !iming sanity check means :with respect to /';CCC.
a. *he5ing timing of routed design with out net delays +. *he5ing &iming of plaed
design with net delays . *he5ing &iming of unplaed design without net delays d.
*he5ing &iming of routed design with net delays
AG; Which of the following is having highest priority at final stage :post
routed; of the design CCC?
a. Setup 'iolation +. Iold 'iolation . S5ew d. "one
AH; Which of the following is best suited for (!S?
a. *@G8;= +. 8;= . I"2 d. *@GI"2
AI; *a= voltage drop will be there at:with out macros; CCC.
a. @eft and Aight sides +. 8ottom and &op sides . 9iddle d. "one
AJ; Which of the following is prefered while placing macros CCC?
a. 9aros plaed enter of the die +. 9aros plaed left and right side of die . 9aros
plaed +ottom and top sides of die d. 9aros plaed +ased on onneti'ety of the I./
D7; <outing congestion can be avoided by CCC.
a. plaing ells loser +. Plaing ells at orners . Distri+uting ells d. "one
D6; /itch of the wire is CCC.
a. 9in width +. 9in spaing . 9in width - min spaing d. 9in width S min spaing
DA; In /hysical 'esign following step is not there CCC.
a. =loorplaning +. Plaement . Design Synthesis d. *&S
DD; In technology file if H metals are there then which metals you will use for
power?
a. 9etal6 and metal2 +. 9etal! and metal% . 9etal( and metal) d. 9etal) and metal,
DE; If metalG and metalH are used for the power in H metal layer process
design then which metals you will use for clock ?
a. 9etal6 and metal2 +. 9etal! and metal% . 9etal% and metal( d. 9etal) and metal,
DF; In a reg to reg timing path !clocktoq delay is 7.Fns and !(ombo delay is
Fns and !setup is 7.Fns then the clock period sould be CCC.
a. 6ns +. !ns . (ns d. )ns
DG; 'ifference between (lock buff0inverters and normal buff0inverters is CC.
a. *lo5 +uff.in'erters are faster than normal +uff.in'erters +. *lo5 +uff.in'erters are
slower than normal +uff.in'erters . *lo5 +uff.in'erters are ha'ing equal rise and fall
times with high dri'e strengths ompare to normal +uff.in'erters d. "ormal +uff.in'erters
are ha'ing equal rise and fall times with high dri'e strengths ompare to *lo5
+uff.in'erters.
DH; Which configuration is more preffered during floorplaning ?
a. Dou+le +a5 with flipped rows +. Dou+le +a5 with non flipped rows . >ith hannel
spaing +etween rows and no dou+le +a5 d. >ith hannel spaing +etween rows and
dou+le +a5
DI; What is the effect of high drive strength buffer when added in long net ?
a. Delay on the net inreases +. *apaitane on the net inreases . Delay on the net
dereases d. Aesistane on the net inreases.
DJ; 'elay of a cell depends on which factors ?
a. /utput transition and input load +. Input transition and /utput load . Input transtion
and /utput transtion d. Input load and /utput @oad.
E7; "fter the final routing the violations in the design CCC.
a. &here an +e no setup, no hold 'iolations +. &here an +e only setup 'iolation +ut no
hold . &here an +e only hold 'iolation not Setup 'iolation d. &here an +e +oth
'iolations.
E6; >tilisation of the chip after placement optimisation will be CCC.
a. *onstant +. Derease . Inrease d. "one of the a+o'e
EA; What is routing congestion in the design?
a. Aatio of required routing tra5s to a'aila+le routing tra5s +. Aatio of a'aila+le routing
tra5s to required routing tra5s . Depends on the routing layers a'aila+le d. "one of the
a+o'e
ED; What are preroutes in your design?
a. Power routing +. Signal routing . Power and Signal routing d. "one of the a+o'e.
EE; (lock tree doesn5t contain following cell CCC.
a. *lo5 +uffer +. *lo5 In'erter . A/I ell d. "one of the a+o'e
"nswers2
6$+ 2$ !$+ %$ ($+ )$d ,$a -$ 4$d 67$+ 66$d 62$d 6!$+ 6%$ 6($+ 6)$a 6,$ 6-$a 64$d
27$a 26$+ 22$+ 2!$d 2%$d 2($ 2)$+ 2,$a 2-$ 24$d !7$ !6$d !2$ !!$d !%$ !($d !)$
!,$a !-$ !4$+ %7$d %6$ %2$a %!$a %%$
Lackend :/hysical 'esign; Interview 4uestions and "nswers
8elow are the sequene of questions as5ed for a physial design engineer.
In which field are you interested?
Answer to this question depends on your interest, e1pertise and to the requirement
for whih you ha'e +een inter'iewed.
>ell..the andidate ga'e answer: @ow power design
(an you talk about low power techniques? #ow low power and latest J7nm0GFnm
technologies are related?
Aefer here and +rowse for different low power tehniques.
'o you know about input vector controlled method of leakage reduction?
@ea5age urrent of a gate is dependant on its inputs also. Iene find the set of
inputs whih gi'es least lea5age. 8y applyig this minimum lea5age 'etor to a
iruit it is possi+le to derease the lea5age urrent of the iruit when it is in the
stand+y mode. &his method is 5nown as input 'etor ontrolled method of
lea5age redution.
#ow can you reduce dynamic power?
-Aedue swithing ati'ity +y designing good A&@
-*lo5 gating
-Arhitetural impro'ements
-Aedue supply 'oltage
-;se multiple 'oltage domains-9ulti 'dd
What are the vectors of dynamic power?
2oltage and *urrent
#ow will you do power planning?
Aefer here for power planning.
If you have both I< drop and congestion how will you fi= it?
-Spread maros
-Spread standard ells
-Inrease strap width
-Inrease num+er of straps
-;se proper +lo5age
Is increasing power line width and providing more number of straps are the only
solution to I< drop?
-Spread maros
-Spread standard ells
-;se proper +lo5age
In a reg to reg path if you have setup problem where will you insert buffernear to
launching flop or capture flop? Why?
#+uffers are inserted for fi1ing fanout 'oilations and hene they redue setup
'oilationZ otherwise we try to fi1 setup 'oilation with the si<ing of ellsZ now Lust
assume that you must insert +uffer T$
"ear to apture path.
8eause there may +e other paths passing through or originating from the flop
nearer to lauh flop. Iene +uffer insertion may affet other paths also. It may
impro'e all those paths or degarde. If all those paths ha'e 'oilation then you may
insert +uffer nearer to launh flop pro'ided it impro'es sla5.
#ow will you decide best floorplan?
Aefer here for floor planning.
What is the most challenging task you handled? What is the most challenging Bob in
/$< flow?
-It may +e power planning- +eause you found more IA drop
-It may +e low power target-+eause you had more dynami and lea5age power
-It may +e maro plaement-+eause it had more onnetion with standard ells or
maros
-It may +e *&S-+eause you needed to handle multiple lo5s and lo5 domain
rossings
-It may +e timing-+eause si<ing ells in E*/ flow is not meeting timing
-It may +e li+rary preparation-+eause you found some inonsistany in li+raries.
-It may +e DA*-+eause you faed thousands of 'oilations
#ow will you synthesi)e clock tree?
-Single lo5-normal synthesis and optimi<ation
-9ultiple lo5s-Synthesis eah lo5 seperately
-9ultiple lo5s with domain rossing-Synthesis eah lo5 seperately and
+alane the s5ew
#ow many clocks were there in this proBect?
-It is speifi to your proLet
-9ore the lo5s more hallenging T
#ow did you handle all those clocks?
-9ultiple lo5s--Esynthesi<e seperately--E+alane the s5ew--Eoptimi<e the lo5
tree
"re they come from seperate e=ternal resources or /LL?
-If it is from seperate lo5 soures #i.e.asynhronousZ from different pads or pins$
then +alaning s5ew +etween these lo5 soures +eomes hallenging.
-If it is from P@@ #i.e.synhronous$ then s5ew +alaning is omparati'ely easy.
Why buffers are used in clock tree?
&o +alane s5ew #i.e. flop to flop delay$
What is cross talk?
Swithing of the signal in one net an interfere neig+ouring net due to ross
oupling apaitane.&his affet is 5nown as ros tal5. *ross tal5 may lead setup
or hold 'oilation.
#ow can you avoid cross talk?
-Dou+le spaingKEmore spaingKEless apaitaneKEless ross tal5
-9ultiple 'iasKEless resistaneKEless A* delay
-ShieldingKE onstant ross oupling apaitane KE5nown 'alue of rosstal5
-8uffer insertionKE+oost the 'itim strength
#ow shielding avoids crosstalk problem? What e=actly happens there?
-Iigh frequeny noise #or glith$is oupled to 2SS #or 2DD$ sine shilded layers
are onneted to either 2DD or 2SS.
*oupling apaitane remains onstant with 2DD or 2SS.
#ow spacing helps in reducing crosstalk noise?
width is moreKEmore spaing +etween two ondutorsKEross oupling
apaitane is lessKEless ross tal5
Why double spacing and multiple vias are used related to clock?
>hy lo5?-- +eause it is the one signal whih hages it state regularly and more
ompared to any other signal. If any other signal swithes fast then also we an
use dou+le spae.
Dou+le spaingKEwidth is moreKEapaitane is lessKEless ross tal5
9ultiple 'iasKEresistane in parellelKEless resistaneKEless A* delay
#ow buffer can be used in victim to avoid crosstalk?
8uffer inrease 'itims signal strengthZ +uffers +rea5 the net lengthKE'itims are
more tolerant to oupled signal from aggressor.
/hysical 'esign 4uestions and "nswers
I am getting se'eral emails requesting answers to the questions posted in this
+log. 8ut it is 'ery diffiult to pro'ide detailed answer to all questions in my
a'aila+le spare time. Iene i deided to gi'e Mshort and sweetM one line answers
to the questions so that readers an immediately +enefited. Detailed answers will
+e posted in later stage.I ha'e gi'en answers to some of the physial design
questions here. EnLoy T
What parameters :or aspects; differentiate (hip 'esign and Llock level design?
*hip design has I./ padsZ +lo5 design has pins.
*hip design uses all metal layes a'aila+leZ +lo5 design may not use all metal
layers.
*hip is generally retangular in shapeZ +lo5s an +e retangular, retilinear.
*hip design requires se'eral pa5agingZ +lo5 design ends in a maro.
#ow do you place macros in a full chip design?
=irst he5 flylines i.e. he5 net onnetions from maro to maro and maro to
standard ells.
If there is more onnetion from maro to maro plae those maros nearer to
eah other prefera+ly nearer to ore +oundaries.
If input pin is onneted to maro +etter to plae nearer to that pin or pad.
If maro has more onnetion to standard ells spread the maros inside ore.
A'oid risross plaement of maros.
;se soft or hard +lo5ages to guide plaement engine.
'ifferentiate between a #ierarchical 'esign and flat design?
Iierarhial design has +lo5s, su++lo5s in an hierarhyZ =lattened design has no
su++lo5s and it has only leaf ells.
Iierarhial design ta5es more run timeZ =lattened design ta5es less run time.
Which is more complicated when u have a EI *#) and F77 *#) clock design?
(77 9I<Z +eause it is more onstrained #i.e.lesser lo5 period$ than %- 9I<
design.
1ame few tools which you used for physical verification?
Ierulis from Synopsys, *ali+er from 9entor 3raphis.
What are the input files will you give for primetime correlation?
"etlist, &ehnology li+rary, *onstraints, SPE= or SD= file.
If the routing congestion e=ists between two macros3 then what will you do?
Pro'ide soft or hard +lo5age
#ow will you decide the die si)e?
8y he5ing the total area of the design you an deide die si<e.
If lengthy metal layer is connected to diffusion and poly3 then which one will affect
by antenna problem?
Poly
If the full chip design is routed by H layer metal3 why macros are designed using
FL* instead of using HL*?
8eause top two metal layers are required for glo+al routing in hip design. If top
metal layers are also used in +lo5 le'el it will reate routing +lo5age.
In your proBect what is die si)e3 number of metal layers3 technology3 foundry3
number of clocks?
Die si<e: tell in mm eg. 6mm 1 6mm Z reme+er 6mmK6777miron whih is a +ig
si<e TT
9etal layers: See your teh file. generally for 47nm it is , to 4.
&ehnology: Again loo5 into teh files.
=oundry:Again loo5 into teh filesZ eg. &S9*, I89, AA&ISA" et
*lo5s: @oo5 into your design and SD* file T
#ow many macros in your design?
Jou 5now it well as you ha'e designed it T A So* #System /n *hip$ design may
ha'e 677 maros also TTTT
What is each macro si)e and number of standard cell count?
Depends on your design.
What are the input needs for your design?
=or synthesis: A&@, &ehnology li+rary, Standard ell li+rary, *onstraints
=or Physial design: "etlist, &ehnology li+rary, *onstraints, Standard ell li+rary
What is S'( constraint file contains?
*lo5 definitions
&iming e1eption-multiyle path, false path
Input and /utput delays
#ow did you do power planning?
#ow to calculate core ring width3 macro ring width and strap or trunk width?
#ow to find number of power pad and I, power pads?
#ow the width of metal and number of straps calculated for power and ground?
3et the total ore power onsumptionZ get the metal layer urrent density 'alue
from the teh fileZ Di'ide total power +y num+er sides of the hipZ Di'ide the
o+tained 'alue from the urrent density to get ore power ring width. &hen
alulate num+er of straps using some more equations. >ill +e e1plained in detail
later.
#ow to find total chip power?
&otal hip powerKstandard ell power onsumption,9aro power onsumption
pad power onsumption.
What are the problems faced related to timing?
Prelayout: Setup, 9a1 transition, ma1 apaitane
Post layout: Iold
#ow did you resolve the setup and hold problem?
Setup: upsi<e the ells
Iold: insert +uffers
In which layer do you prefer for clock routing and why?
"e1t lower layer to the top two metal layers#glo+al routing layers$. 8eause it has
less resistane hene less A* delay.
If in your design has reset pin3 then itMll affect input pin or output pin or both?
/utput pin.
'uring power analysis3 if you are facing I< drop problem3 then how did you avoid?
Inrease power metal layer width.
3o for higher metal layer.
Spread maros or standard ells.
Pro'ide more straps.
'efine antenna problem and how did you resolve these problem?
Inreased net length an aumulate more harges while manufaturing of the
de'ie due to ionisation proess. If this net is onneted to gate of the 9/S=E& it
an damage dieletri property of the gate and gate may ondut ausing damage
to the 9/S=E&. &his is antenna pro+lem.
Derease the length of the net +y pro'iding more 'ias and layer Lumping.
Insert antenna diode.
#ow delays vary with different /V! conditions? Show the graph.
P inrease-Edealy inrease
P derease-Edelay derease
2 inrease-Edelay derease
2 derease-Edelay inrease
& inrease-Edelay inrease
& derease-Edelay derease
%=plain the flow of physical design and inputs and outputs for each step in flow.
*li5 here to see the flow diagram
What is cell delay and net delay?
9ate delay
&ransistors within a gate ta5e a finite time to swith. &his means that a hange on
the input of a gate ta5es a finite time to ause a hange on the output.C9agmaF
3ate delay Kfuntion of#i.p transition time, *netS*pin$.
*ell delay is also same as 3ate delay.
(ell delay
=or any gate it is measured +etween (7Q of input transition to the orresponding
(7Q of output transition.
Intrinsi delay
Intrinsi delay is the delay internal to the gate. Input pin of the ell to output pin
of the ell.
It is defined as the delay +etween an input and output pair of a ell, when a near
<ero slew is applied to the input pin and the output does not see any load
ondition.It is predominantly aused +y the internal apaitane assoiated with
its transistor.
&his delay is largely independent of the si<e of the transistors forming the gate
+eause inreasing si<e of transistors inrease internal apaitors.
1et 'elay :or wire delay;
&he differene +etween the time a signal is first applied to the net and the time it
reahes other de'ies onneted to that net.
It is due to the finite resistane and apaitane of the net.It is also 5nown as wire
delay.
>ire delay Kfn#Anet , *netS*pin$
What are delay models and what is the difference between them?
@inear Delay 9odel #@D9$
"on @inear Delay 9odel #"@D9$
What is wire load model?
>ire load model is "@D9 whih has estimated A and * of the net.
Why higher metal layers are preferred for Vdd and Vss?
8eause it has less resistane and hene leads to less IA drop.
What is logic optimi)ation and give some methods of logic optimi)ation.
;psi<ing
Downsi<ing
8uffer insertion
8uffer reloation
Dummy +uffer plaement
What is the significance of negative slack?
negati'e sla5KKE there is setup 'oilationKKE deisgn an fail
What is signal integrity? #ow it affects !iming?
IA drop, Eletro 9igration #E9$, *rosstal5, 3round +oune are signal integrity
issues.
If Idrop is moreKKEdelay inreases.
rosstal5KKEthere an +e setup as well as hold 'oilation.
What is I< drop? #ow to avoid? #ow it affects timing?
&here is a resistane assoiated with eah metal layer. &his resistane onsumes
power ausing 'oltage drop i.e.IA drop.
If IA drop is moreKKEdelay inreases.
What is %* and it effects?
Due to high urrent flow in the metal atoms of the metal an displaed from its
origial plae. >hen it happens in larger amount the metal an open or +ulging of
metal layer an happen. &his effet is 5nown as Eletro 9igration.
Affets: Either short or open of the signal line or power line.
What are types of routing?
3lo+al Aouting
&ra5 Assignment
Detail Aouting
What is latency? 9ive the types?
Source Latency
It is 5nown as soure lateny also. It is defined as Mthe delay from the lo5 origin
point to the lo5 definition point in the designM.
Delay from lo5 soure to +eginning of lo5 tree #i.e. lo5 definition point$.
&he time a lo5 signal ta5es to propagate from its ideal wa'eform origin point to
the lo5 definition point in the design.
1etwork latency
It is also 5nown as Insertion delay or "etwor5 lateny. It is defined as Mthe delay
from the lo5 definition point to the lo5 pin of the registerM.
&he time lo5 signal #rise or fall$ ta5es to propagate from the lo5 definition
point to a register lo5 pin.
What is track assignment?
Seond stage of the routing wherein partiular metal tra5s #or layers$ are
assigned to the signal nets.
What is congestion?
If the num+er of routing tra5s a'aila+le for routing is less than the required
tra5s then it is 5nown as ongestion.
Whether congestion is related to placement or routing?
Aouting
What are clock trees?
Distri+ution of lo5 from the lo5 soure to the syn pin of the registers.
What are clock tree types?
I tree, 8alaned tree, D tree, *lustering tree, =ish +one
What is cloning and buffering?
*loning is a method of optimi<ation that dereases the load of a hea'ily loaded
ell +y repliating the ell.
8uffering is a method of optimi<ation that is used to insert +effers in high fanout
nets to derease the dealy.

What is difference between normal buffer and clock buffer?
Answer:
*lo5 net is one of the Iigh =anout "et#I="$s. &he lo5 +uffers are designed with
some speial property li5e high dri'e strength and less delay. *lo5 +uffers ha'e equal
rise and fall time. &his pre'ents duty yle of lo5 signal from hanging when it passes
through a hain of lo5 +uffers.
"ormal +uffers are designed with >.@ ratio suh that sum of rise time and fall time is
minimum. &hey too are designed for higher dri'e strength.
What is difference between #&1 synthesis and (!S?
"nswer2
#&1s are synthesi<ed in front end also.... +ut at that moment no plaement information
of standard ells are a'aila+le... hene +a5end tool ollapses synthesi<ed I="s. It
resenthesi<es I="s +ased on plaement information and appropriately inserts +uffer.
&arget of this synthesis is to meet delay requirements i.e. setup and hold.
=or clock no synthesis is arried out in front end #why.....????..+eause no plaement
information of flip-flops T So synthesis won0t meet true s5ew targets TT$ ... in +a5end
lo5 tree synthesis tries to meet Ms5ewM targets...It inserts lo5 +uffers #whih ha'e
equal rise and fall time, unli5e normal +uffers T$... &here is no s5ew information for any
I="s.
Is it possible to have a )ero skew in the design?
"nswer2
&heoretially it is possi+le....T
Pratially it is impossi+le....TT
Pratially we ant redue any delay to <ero.... delay will e1ist... hene we try to ma5e
s5ew MequalM #or same$ rather than M<eroM......now with this optimi<ation all flops get the
lo5 edge with same delay relati'e to eah other.... so 'irtually we an say they are
ha'ing M<ero s5ew M or s5ew is M+alanedM.