ELECTRICAL AND ELECTRONIC ENGINEERING

Intel 8086 Microprocessor

General Operation
The internal functions of the 8086 processor are partitioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the !ecution Unit (U) as shown in the "loc# diagra$ of %igure &.
These units can interact directly "ut for the $ost part perfor$ as separate asynchronous operational processors.
The "us interface unit pro'ides the functions related to instruction fetching and (ueuing) operand fetch and
store) and address relocation. This unit also pro'ides the "asic "us control. The o'erlap of instruction pre*
fetching pro'ided "y this unit ser'es to increase processor perfor$ance through i$pro'ed "us "andwidth
utili+ation. Up to 6 "ytes of the instruction strea$ can "e (ueued while waiting for decoding and e!ecution.
The instruction strea$ (ueuing $echanis$ allows the BIU to #eep the $e$ory utili+ed 'ery efficiently.
,hene'er there is space for at least - "ytes in the (ueue) the BIU will atte$pt a word fetch $e$ory cycle. This
greatly reduces ..dead ti$e// on the $e$ory "us. The (ueue acts as a %irst*In*%irst*Out (%I%O) "uffer) fro$
which the U e!tracts instruction "ytes as re(uired. If the (ueue is e$pty (following a "ranch instruction) for
e!a$ple)) the first "yte into the (ueue i$$ediately "eco$es a'aila"le to the U.
The e!ecution unit recei'es pre*fetched instructions fro$ the BIU (ueue and pro'ides un*relocated operand
addresses to the BIU. 0e$ory operands are passed through the BIU for processing "y the U) which passes
results to the BIU for storage. 1ee the Instruction 1et description for further register set and architectural
descriptions.
%igure &2 3rchitectural layout
&
%igure -2 1i$plified 8086 0icroprocessor
0icroprocessors ha'e two $a4or co$ponents
The !ecution unit (U)
The Bus interface unit (BIU)
The Execution unit
(U) is used $ainly to e!ecute instructions. It contains a circuit called the arith$etic and logic unit (35U). The
35U perfor$s arith$etic (6) * ) 7) 8) and logic (39:) O;) 9OT) operations. The data for operations are stored
in circuit called ;egisters. 3 register is li#e a $e$ory location e!cept that we nor$ally refer to it "y a na$e
rather than address. The U has eight registers for storing data< their na$es are 3=) B=) >=) :=) 1I) :I) B?)
1? and %53G1 register.
Bus interfce unit !BI"#
BIU facilitates co$$unication "etween the U and $e$ory or I8O circuits. It is responsi"le for trans$itting
address) data) and control signals on the "uses. Its registers are na$ed >1) :1) 1) 11) I?< they hold addresses
of $e$ory locations. The I? contains the address of ne!t instruction to "e e!ecuted "y the U.
The E" n$ the BI"
3re connected 'ia an internal "us and they wor# together. ,hile the U is e!ecuting an instruction) the BIU
fetches up to si! "ytes of the ne!t instruction and places the$ in the instruction (ueue. This operation is called
Instruction pre*fetch. The purpose is to speed up the processor.
I%O &orts'
I8O de'ices are connected to the co$puter through I8O circuits. ach of these circuits contains se'eral register
called I8O ?orts. 1o$e are used for data while others are used control co$$ands. 5i#e $e$ory locations) the
I8O ports ha'e address and they are connected to the "us syste$. These addresses are #nown as I8O address and
can only "e use in input (I9) or output (OUT) instructions.
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T(E )LAG REGI*TER !)R# AND BIT )IELD*
The flag register is a &6*"it register so$eti$es referred as the status register. 3lthough the register is &6*"it) not
all the "its are used. >onditional flags2 1i! (6) of the flags are called the conditional flags) $eaning that they
indicate so$e condition that resulted after an instruction was e!ecuted. These 6 are2 >%) ?%) 3%) @%) 1%) and O%.
The +6 ,its of the fl- re-isters'
C). the Crr/ )l-' This flag is set whene'er there is a carry out) either fro$ dA after an 8*"it operation) or
fro$ d&B after a &6*"it data operation.
&). the &rit/ )l-' 3fter certain operations) the parity of the resultCs low*order "yte is chec#ed. If the "yte has
an e'en nu$"er of &s) the parity flag is set to &< otherwise) it is cleared.
A). the Auxilir/ Crr/ )l-' If there is a carry fro$ dD to dE of an operation this "it is set to &) otherwise
cleared (set to 0).
0). the 0ero )l-' The @% is set to & if the result of the arith$etic or logical operation is +ero) otherwise) it is
cleared (set to 0).
*). the *i-n )l-' 01B is used as the sign "it of the "inary representation of the signed nu$"ers. 3fter
arith$etic or logical operations the 01B is copied into 1% to indicate the sign of the result.
T). the Trp )l-' ,hen this flag is set it allows the progra$ to single step) $eaning to e!ecute one instruction
at a ti$e. Used for de"ugging purposes.
I). Interrupt En,le )l-' This "it is set or cleared to ena"le or disa"le only the e!ternal interrupt re(uests.
D). the Direction )l-' This "it is used to control the direction of the string operations.
O). the O1erflo2 )l-' This flag is set whene'er the result of a signed nu$"er operation is too large) causing
the high*order "it to o'erflow into the sign "it.
%igure D2 8086 %lag ;egisters
D