Presented by: Nishma-USN: 4CB12LEL08

Circuit Design Process

Design processes are aided by simple concepts such as stick and symbolic diagrams but the
key element is a set of design rules. Design rules usually specify the minimum allowable line
widths for physical objects on-chip such as metal and polysilicon interconnects or diffusion areas,
minimum feature dimensions, and minimum allowable separations between two such features.
If a metal line width is made too small, for example, it is possible for the line to break during the
fabrication process or afterwards, resulting in an open circuit. If two lines are placed too close to
each other in the layout, they may form an unwanted short circuit by merging during or after the
fabrication process.

MOS Layer:
MO circuits are formed on four basic layers!
"-diffusion
#-diffusion
#olysilicon
Metal
$hese layers are isolated by one another by thick or thin silicon dioxide insulating %ayers.$hin
oxide mask region includes n-diffusion & p-diffusion and transistor channel.
Stick diagrams:
tick diagrams may be used to con'ey layer information through the use of a colour code.
(or example! n-diffusion --green
poly -- red
blue -- metal
)ellow --implant
*lack --contact areas
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Presented by: Nishma-USN: 4CB12LEL08
+ncodings for "MO process!
Figure 1: NMOS encodings
(igure shows the way of representing different layers in stick diagram notation and mask
layout using nMO style.
(igure, shows when a n-transistor is formed! a transistor is formed when a green line -n.
diffusion/ crosses a red line -poly/ completely. (igure also shows how a depletion mode
transistor is represented in the stick format.
Encodings for CMOS process:
Figure 2: CMOS encodings
(igure 0 shows when a n-transistor is formed! a transistor is formed when a green line
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-n. diffusion/ crosses a red line -poly/ completely. (igure 0 also shows when a p-
transistor is formed! a transistor is formed when a yellow line -p. diffusion/ crosses a red
line -poly/ completely.
Encoding for !" and MOSFE"s:

Figure #: i CMOS encodings
$here are se'eral layers in an nMO chip!
1 p-type substrate

paths of n-type diffusion
a thin layer of silicon dioxide
paths of polycrystalline silicon

a thick layer of silicon dioxide

paths of metal -usually aluminium/

a further thick layer of silicon dioxide
2ith contact cuts through the silicon dioxide where connections are re3uired.$he three
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layers carrying paths can be considered as independent conductors that only interact
where polysilicon crosses diffusion to form a transistor. $hese tracks can be drawn as
stick diagrams with
diffusion in green

polysilicon in red

metal in blue
using black to
indicate contacts between layers and yellow to mark regions of implant inthe channels of
depletion mode transistors.
2ith 4MO there are two types of diffusion! n-type is drawn in green and p-
type in brown. $hese are on the same layers in the chip and must not meet. In fact,
the method of fabrication re3uired that they be kept relati'ely far apart.
Modern 4MO processes usually support more than one layer of metal. $wo are
common and three or more are often a'ailable.
1ctually, these con'entions for colors are not uni'ersal5 in particular, industrial
-rather than academic/ systems tend to use red for diffusion and green for polysilicon.
Moreo'er, a shortage of colored pens normally means that both types of diffusion in
4MO are colored green and the polarity indicated by drawing a circle round p-type
transistors or simply inferred from the context. 4olorings for multiple layers of metal are
e'en less standard.
$here are three ways that an nMO in'erter might be drawn!
Figure $: nMOS dep%etion %oad in&erter
(igure6 shows schematic, stick diagram and corresponding layout of nMO depletion
load in'erter
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Figure ': CMOS in&erter
(igure 7 shows the schematic, stick diagram and corresponding layout of 4MO in'erter
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