VLSICore deals with VLSI design on SoC / ASIC / FPGA design flows.

It includes,
Digital Logic design, Full-Custom/Semi-Custom design.
Microprocessors, DSP, Telecom more.
Technology: 32nm, 20nm, 14nm and beyond.
Foundry: TSMC, GF, UMC, IBM, Tower
Standard / IO Cell library preparation, Intellectual Property [Memories, SRAMs, DRAMs,
PCI, USB, Audio/Video CODEC], VDSM/UDSM.
Verilog, PLI, VHDL, EDIF, System Verilog, SystemC
Design Entry, Simulation, Formal Verification, Synthesis.
Floorplanning, HF Net Synthesis, Placement, Clock Tree Synthesis, Routing, Physical
Verification, RC Extraction, DFM, OPC, Tape-Out.
Shell, Perl, Tcl, Python, Tk/Tix, Scheme, C/C++, API, ...
Analog design, SPICE, Simulation, RF, PLL, High Speed CMOS, MEMS, ...
DFM (Design for Manufacturing)
EDA: Synopsys, Cadence, Mentor, Magma, ATopTech, Oasys, Xilinx, Altera, Atmel, ...
Open Source EDA tools, Open Source : ASIC design and technology.
Saturday, July 15, 2006
SoC EDA Tools
EDA Tools used at Various stages of SoC Design Flow
Source: http://groups.yahoo.com/group/VLSICore

SoC Flow
Architecture & Specification
Layout & Library Development
CosmosLE/SE [Synopsys]
Virtuoso [Cadence]
ICstation [Mentor Graphics]
L-Edit [Tanner]
MicroWind [MicroWind]
LASI [University of Berkeley]
Magic []
Electric []
Alliance [open source, Pierre et Marie Curie University, Paris]
Library Characterization
Star-MTB [Synopsys]
Nano Char [Synopsys]
NLG
Library Characterizer [Nangate]
FRONTEND Flow
RTL Coding
vi/emacs Editor [unix]
Cadence Composer [Cadence]
HDL - Verilog/VHDL/System Verilog
Actel Libero
Altera Quartus II
Altium Nexar
ArchPro MVSIM
Arithmatica CellMath Designer
Axiom @Verifier
Calypto SLEC
Certess Certitude
CLKDA Amber
Concept Engineering RTLVision PRO
DAFCA ClearBlue
DeFacTo Scan Insertion
EVE ZeBu
GateRocket RocketDrive
HDL Works HDL Companion
Jasper JasperGold
Lattice ispLEVER
Liga Systems NitroSIM
Magma Quartz Formal
NEC CyberWorkBench
Philips ED&T RTL DfT
ProDesign CHIPit
Prover eCheck, sCheck
Real Intent Verix
S2C TAI IP
Sequence Power Theater
Silicon Navigator Rocket
Tenison VTOC
Tharas Systems Hammer
Theseus Logic NCL-shell
Scan Insertion
DFT Compiler [Synopsys]
DFT Advisor [Mentor Graphics]
Formal Verification
VCS [Synopsys]
Formality [Synopsys]
Conformal LEC [Cadence]
Verplex [Verplex]
FormalPro [Mentor Graphics]
Simulation
VCS - Vera [Synopsys]
NC-Verilog / Verilog XL [Cadence]
finsim [Fintronics]
Event Simulation - MTI VHDL Model Sim [Mentor]
Event Simulation - VSS {VHDL} [Synopsys]
Event Simulation - Verilog - Verilog XL [Cadence]
Event Simulation - Verilog - MTI Model Sim Plus [Mentor]
Event Simulation - Verilog - VCS [Synopsys]
Veriloger []
Synthesis
RTL Compiler [Cadence]
Design Compiler [Synopsys]
DC Expert for ASIC [Synopsys]
Blast RTL [Magma]
Exempler for FPGA
Leornado Spectrum [Mentor]
Alliance [open source, Pierre et Marie Curie University, Paris]
FPGA Synthesis
Quartus []
Xilinx [Xilinx]
DC-FPGA [Synopsys]
Precision Synthesis [Mentor Graphics]
ATPG and Tests
Tetra Max [Synopsys]
DFT Compiler [Synopsys]
SynTest
Test Compiler [Synopsys]
Testbench [IBM]
Vera / NTB [Synopsys]
Fast Scan [Mentor Graphics]
Logic BIST
LBIST Architect [Mentor Graphics]
Memory BIST
MBIST Architect [Mentor Graphics]
Boundary Scan Insertion
BSD Architect [Mentor Graphics]
STA - Static Timing Analysis
PrimeTime [Synopsys]
Showtime [Sequence]
Design Time [Synopsys]
CoolTime [Sequence]
Pearl [Cadence]
Transistor Level Analysis & Verification
PathMill [Synopsys]
BACKEND Flow
Hierarchical Design Planning
upiterXT [Synopsys]
PKS [Cadence]
First Encounter (FE) [Cadence]
BlastPlan [Magma]
Place & Route
Apollo/Astro [Synopsys]
IC Compiler [Synopsys]
Pinnacle / Olympus-SoC [Mentor]
<> - [Atop Tech]
Physical Compiler [Synopsys]
Gate/Silicon Ensemble [Cadence]
First Encounter/Nano Encounter [Cadence]
SoC Encounter [Cadence]
Blast Fusion [Magma]
Montery Dolphin (placer acquired by Synopsys)
AutoCells [Mentor Graphics]
Clock Tree Synthesis (CTS)
CTGen [Cadence]
Clock Tree Compiler (CTC) [Synopsys] #
Astro/Apollo/ICC [Synopsys]
Physical Verification [DRC/LVS/ERC/OPC]
Calibre [Mentor]
Hercules [Synopsys]
Assura [Cadence]
Dracula [Cadence]
Vampire [Cadence]
Diva [Cadence]
Mojave [MAGMA (Mojave)]
Parasitics/RC Extraction
Star-RCXT [Synopsys]
Arcadia [Synopsys]
Columbus Turbo [Sequence : RC Extraction]
Columbus Gold [Sequence : RLC Extraction]
Fire&Ice [earlier called as Simplex]
CalibreRC [Mentor]
Power Analysis
RTL/Gate Power Analysis
PowerTheater Analyst [Sequence : predicts rtl and netlist power] * earlier known as Sente
Wattwatcher
Power Compiler [Synopsys]
PrimePower [Synopsys]
AstroRail - Static [Synopsys]
PrimeRail - Dynamic & Static [Synopsys]
Power Compiler [Synopsys]
Signal Integrity / Crosstalk
PrimeTime SI [Synopsys]
AstroXtalk [Synopsys]
CeltIC [Cadence]
Physical Studio [Sequence]
Glitch Analysis
Physical Studio [Sequence]
PTSI/PrimePower [Synopsys]
Electro Migration (EM Analysis)
Prime-Rail [Synopsys]
AstroXtalk (EM) [Synopsys]
Analog/Mixed Signal Simulation [Tr. Level]
HSPICE [Synopsys]
Nanosim [Synopsys]
HSIM [Synopsys]
Spectre [Cadence]
X-Eldo [Mentor]
Win-SPICE [Free Tool]
Columbus RF [Sequence : RLC Extraction - Analog]
B2SPICE [Beige Bag]
ngspice [open source, gEDA]
Pattern Conversion to Hardware Test
TSSI Advantest Wavebridge
TDS6000 [IBM]
IC Packaging

Foundry Flow
OPC/FAB Process
Tauras [Synopsys]
CATS [Synopsys]
Calibre OPC / RET / MDP [Mentor Graphics]
Mask Verification
Tape-Out (Post Silicon)