Microprocessor Basic Programming

Unit I
1. Evolution of Microprocessors
2. History of computers
3. Timing and control
4. Semiconductor memory organization, Category of memory
5. 8-bit Microprocessor (8085),
6. Architecture
7. Instruction set
8. Addressing modes
9. Assembly Language Programming
Unit II
1. 8086 Architecture
2. Physical address
3. Segmentation
4. Memory organization
5. Bus cycle
6. Addressing modes
7. Difference between 8086 and 8088
8. Introduction to 80186 and 80286
9. Assembly Language Programming of 8086/8088
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Unit III
1. Introduction & Types of transmission 8257 (DMA)
2. 8255 (PPI)
3. Serial Data transfer (USART 8251)
4. Keyboard-display controller (8279)
5. Programmable Priority Controller (8259)
Unit IV
1. Programmable Interval Timer/ Counter (8253/8254)
2. Introduction, modes & Interfacing of 8253
3. Introduction to ADC and DAC
4. DAC methods
5. ADC converters
6. Types of ADC, ADC IC (0808/0809)
7. DAC and ADC Interfacing and Applications.
Unit V
1. Introduction to 32-bit and 64-bit microprocessors
2. PowerPC
3. Microcontroller (8051), Introduction, Architecture, Instruction set
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Reference Books:
S. Gaunkar: Microprocessor Architecture, Programming and
Applications with 8085/8080, Penram Publication
B.Ram: Microprocessor Architecture, Programming and
Applications, PHI Publication
R. Singh and B. P. Singh : Microprocessor Interfacing and
Application, New Age Publishers, 2nd Edition.
B.P. Singh and R. Singh : Advanced Microprocessor and
Microcontrollers, New Age Publishers, 2nd Edition.
D.V Hall : Microprocessors Interfacing, TMH (2nd Edition).
Y.C. Liu and G.A. Gibson : Microcomputer Systems: The
8086/8088 Architecture Programming, PHI 2nd Edition,
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Harvard & Von Neumann (Princeton)
Architecture
HARVARD & PRINCETON ARE THE UNIVERSITIES OF UNITED STATE.
VON NEUMANN IS THE SCIENTIST NAME IN PRINCETON UNIVERSITY.
Harvard Architecture: -
Program & data memory are separate.
Can fetch the next instruction when current
Instruction is in execution.
Von Neumann (Princeton) Architecture: -
Memory interface unit is responsible for access
of memory space between reading & passing
data between register.
Memory interface unit is the bottle neck unit.
Adv: -
1. Simplify to design the processor.
2. Content of memory can be used for variable
Storage &programstorage.
Praveen Kr. Malik, Sr. Lecturer
RGEC, Meerut Ph. 9719437711
RISC & CISC Architecture
RISC: REDUCED INSTRUCTION SET COMPUTERS.
In RISC instruction are bare as minimum possible to allow the user to
design its own application. (We can say that 8085 is RISC processor)
Ex: - MOV B,A
LDA 2000 H
MUL B (First transfer the data from B to A, then
Multiply)
CISC: COMPLEX INSTRUCTION SET COMPUTERS.
In CISC processor there tends to be large number of instructions, each
carrying out a different permutation of the same operations. (We can
say that 8085 is CISC processor)
Ex: - MUL AX, BX (Direct Multiplication can take place)
In general it is observed that RISC are faster then CISC. But, there are
some CISC processor which are faster then RISC. i.e. we cannot say always
that this one is faster.
Real Time Operating System (RTOS): -
RTOS is a background program that control the execution of a number of
application and facilitates communication between the subtasks/task.
*. If more then one task is running at one time the operating system is known as
multitasking operating system. Each task is given small time slice of the
processor.
*. In simple PC operating system, console I/O, command interpreter and file
system processes are loaded with the kernel & everything is optimized to run in
PC environment.
*. In RTOS, the actual application task are loaded in with the kernel with priority
given to the task that are critical to the desired application.
Introduction to Microprocessor
The CPU is a unit that fetches and processes a set of general-purpose instructions.
The CPU instruction set includes instructions for data transfer, ALU operations, stack
operations, input and output operations and program control, sequencing and
supervising operations
A microprocessor is a single VLSI chip that has a CPU and may also have other units
(e.g. caches, floating point processing arithmetic unit, pipelining and super-scaling
units) that are additionally present and result in faster processing of instructions.
A system designer need not be concerned about the design of the microprocessor,
only needs to understand the architecture related to the programming of the processor's
memory to carry out the required functionality i.e. implement the software
Examples: Intel 8085, Intel x86 processors, Motorola 68HCxxx, Sun Sparc, IBM
PowerPC etc.
Time-to-market and NRE costs are lower when systems are designed with
microprocessors
as the designer must only write a program. Flexibility is also high.
Unit cost may be low in small quantities compared with designing a dedicated chip.
Performance varies by application, unit cost may be high for larger volumes, size and
power might be higher due to unnecessary processor hardware
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Introduction to Microcontroller
A microcontroller is a single chip unit which, though having limited computational
capabilities, possesses enhanced input-output capabilities and a number of on-chip
functional units. Particularly suited for use in embedded systems for real-time control
applications. with on-chip program memory and devices. Common peripherals include
serial communication devices, timers, counters, pulse width
modulators, analog-to-digital and digital-to-analog converters. Enables single-chip system
implementation and hence smaller and lower-cost products. Examples: Motorola
68HC11xx, HC12xx, HC16xx, Intel 8051, 80251, PIC 16F84, PIC18, ARM9, ARM7, Atmel
AVR etc.
8085: (1977)
8-bit microprocessor - upgraded version of the 8080, 64KB main memory, 1.3
microseconds clock cycle time; 769,230, instructions/sec, 246 instructions, Intel sold 100
million copies of this 8-bit microprocessor.
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80x86 Evolution
In this course we focus on the Intel x86 architecture, associated peripherals and assembly
language programming. However, concepts covered apply to other logic families.
4004:
4-bit microprocessor. 4KB main memory.
45 instructions. PMOS technology. 50 KIPS
8008: (1971)
8-bit version of 4004. 16KB main memory.
48 instructions. NMOS technology.
8080: (1973)
8-bit microprocessor. 64KB main memory.
2 microseconds clock cycle time; 500,000 instructions/sec. 10X faster than 8008.
8086: (1978) 8088 (1979)
16-bit microprocessor, 1MB main memory, 2.5 MIPS (400 ns).
4- or 6-byte instruction cache, Other improvements included more registers and additional
instructions.
80286: (1983)
16-bit microprocessor very similar in instruction set to the 8086.
16MB main memory, 4.0 MIPS (250 ns/8MHz).
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80386: (1986)
32-bit microprocessor. 4GB main memory. 12-33MHz.
Memory management unit added.
Variations: DX, EX, SL, SLC (cache) and SX.
80386SX: 16MB through a 16-bit data bus and 24 bit address bus.
80486: (1989)
32-bit microprocessor, 32-bit data bus and 32-bit address bus.
4GB main memory. 20-50MHz. Later at 66 and 100MHz
Incorporated an 80386-like microprocessor, 80387-like floating point
coprocessor and an 8K byte cache on one package.
About half of the instructions executed in 1 clock instead of 2 on the
386.
Variations: SX, DX2, DX4.
DX2: Double clocked version:
66MHz clock cycle time with memory transfers at 33MHz.
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Accumulator Flags
B C
D E
H L
Program Counter
Stack Pointer
Data Address 8 16
GENERAL DESCRIPTION OF 8085 MICROPROCESSOR
The Intel 8085 microprocessor is an 8-bit device.
16 address bits provide access to 65,536 bytes of 8 bits data.
8 bi-directional data lines provide access to a data bus.
Control is provided by a variety of lines which support memory and I/O interfacing,
Requiring only a 5 volt supply.
The 8085 comes in two models, the 8085A and the 8085A-2. The 8085A expects clock
frequency of 3 MHz, while the 8085A-2 expects clock frequency of 5 MHz. This clock is
generated by a crystal externally.
The 8085 make use of multiplexing of the lower 8 bits of the address with the data bits on
the same 8 pins. This requires that the external circuitry be able to catch and hold the A0-
A7 lines for later use.
The upper 8 bits of the address have their own pins, however.
The General Purpose Register Array contains the B, C, D, E, H, and L registers, each 8 bits
wide. The B and C, D and E, and H and L registers may be grouped into 16-bit register
pairs. The H & L register pair may be used to store indirect addresses.
An address generation system consisting of the Program Counter, Stack Pointer, address
latches, and incremented / decremented.
The array also contains the Program Counter (PC) and Stack Pointer (SP). These 16-bit
registers contain the address of the next instruction part to be fetched, and the address of
the top of the stack, respectively.
Microprocessor / Microcontroller & Embedded System
Praveen Kr. Malik, RGEC Eng. College, Meerut +91-9719437711
A mathematical and logical subsystem composed of the Arithmetic Logic Unit (ALU) and
associated registers, which handle the math and logic functions of the machine.
An Instruction Register and decoder system which interpret the programmers
instructions
A timing and control package which provides the bodily functions of power and clock
circuits, and handles the wait, interrupt, and hold functions of the system
An 8-bit internal data bus, which provides the data path between functional elements, and
to the outside world via the Address/Data Buffer.
Two serial data lines, Serial Input Data and Serial Output Data, which feed the internal
data bus directly
ADDRESS LINES A8 - A15: These tristate lines are outbound only. They provide the
upper 8 bits of the 16-bit-wide address which identifies one unique 8-bit byte within the
MPs address space, or the 8-bit address of an I/O device. Sixteen address lines provide
an address space of 65,536 locations.
ADDRESS-DATA LINES AD0 - AD7: These tristate lines may by either inbound or
outbound. They provide a multiplexing between the lower 8 bits of the 16-bit-wide
address early in a machine cycle and 8 data bits later in the cycle. When containing
addresses.
ADDRESS LATCH ENABLE (ALE): This signal appears outbound early in a machine
cycle to advise the external circuitry that the AD0 - AD7 lines contain the lower 8 bits of a
memory address
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STATUS LINES so, S1, & I-O/M: These three status lines serve to indicate the
general status of the processor with respect to what function the MP will perform
during the machine cycle
READ & WRITE (/RD & /WR): These lines indicate which direction the MP expects to
pass data between itself and the external data bus.
READY: This is an input line which may be used as a signal from external RAM that a
wait state is needed.
HOLD & HOLD ACKNOWLEDGE (HOLD & HLDA): These lines provide the 8085 with
a DMA capability by allowing another processor on the same system buses to request
control of the buses.
INTERRUPT & INTERRUPT ACKNOWLEDGE (INTR & INTA): These lines provide a
vectored interrupt capability to the 8085. Upon receipt of INTR, the 85 will complete
the instruction in process, then generate INTA as it enters the next machine cycle.
RST 5.5, 6.5, 7.5: These three lines are additional interrupt lines which generate an
automatic Restart.
RESET IN & RESET OUT: These lines provide for both MP and systemreset.
X1 & X2: These two pins provide connection for an external frequency determining
circuit to feed the 8085s clock. This is normally a crystal.
CLOCK (CLK): This line provides a system clock signal to external circuits which need
to be in synchronization with the MP.
Vcc & Vss: These are the power connections for +5 volts and ground, respectively.
STATUS FLAG REGISTER
The Status Flags of the 8085 indicate the logical conditions that existed as a
result of the execution of the instruction just completed.
S Z x A C x P x C
ZERO FLAG: This flag is set to a 1 by the instruction just ending if the A Register
contains a result of all 0s.Otherwise 0.
SIGN FLAG: This flag is set to a 1 by the instruction just ending if the leftmost,
bit of the A Register is set to a 1. Otherwise 0.
PARITY FLAG: This flag is set to a 1 by the instruction if the A Register is left
with an even number of bits set on, i.e., in even parity. Otherwise 0.
CARRY FLAG: This flag is set to a 1 by the instruction just ending if a carry out
of the leftmost bit occurred during the execution of the instruction. Otherwise 0.
AUXILIARY CARRY FLAG: This flag is set to a 1 by the instruction just ending if
a carry occurred from bit 3 to bit 4 of the A Register. Otherwise 0.
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Instruction of 8085: -
DATA TRANSFER: -
1. MOV r1, r2 Move contents of register (A, B, C, D, E, H, L) r2 to r1.
Eg. MOV A, BMove the contents of B to A
2. MVI r, data Move the data to the specify register
Eg. MVI C, F0H Move the data F0 to the reg C
3. LDA 2000H Load the contents of memory location 2000 to Accu. A
4. LXIH 2000H Load the 20 to H Load the 00 to L
5. MOV A, M Load the value of data from memlocation 2000 to A.
6. MOV M, A Load the value of A to the memory pointed by HL pair.
7. MVI M, F0H Load F0 to the memory pointed by HL pair.
8. STA 2000H Store the data of Accu. A to the memory 2000H
9. LHLD 2000H Data of 2000 to L, Data of 2001 to H
10. SHLD 2000H Store the value of L to 2000 & H to 2001
11. LDAX D If DE=2000H, then load the value of 2000 to Accu. A
12. STAX D if DE=3000H, Store the value of A to the 3000H
13. XCHG Exchange the value of DE with HL pair.
ARITHMETIC: -
1. ADD C A+C=A
2. ADD M A+[H-L]=A
3. ADI F0H A+F0=A
4. ADC C A+C+[CF]=A
5. ADC M A+[H-L]+[CF]=A
6. ACI F0H A+F0+[CF]=A
7. DAD D H-L+D-E=H-L
8. SUB B A-B=A
9. SUB M A-[H-L]=A
10. SUI F0H A-F0=A
11. SBB B A-B-[CF]=A
12. SBB M A-[H-L]-[CF]=A
13. SBI F0H A-[F0]-[CF]=A
14. INR D Increment the content of D by one
15 INX D Increment the content of DE pair by one
16. DCR L Decrement the content of L by one.
17. DCR H Decrement the content of HL pair by one.
1. DAA It is used just after the addition instruction. And it
Convert the result in decimal system.
LOGICAL GROUP: -
1. ANA D Logical AND Between the contents of A and D
2. AND M Logical AND Between the contents of A and [H-L]
3. ANI F0 H Logical AND Between the contents of A and F0 H
4. ORA C Logical OR Between the contents of A and C
5. ORA M Logical OR Between the contents of A and [H-L]
6. ORI F0 H Logical OR Between the contents of A and F0 H
7. XRA C Logical XOR Between the contents of A and C
8. XRA M Logical XOR Between the contents of A and [H-L]
9. XRI 0F H Logical XOR Between the contents of A and 0F H
10. CMA Complement the contents of A only.
11. CMC Complement the carry status.
12. STC Set the carry flag.
13. CMP D Compare the contents of A and D. i.e. A-D. But the contents of A and D
are not changed.
14. CMP M Compare the contents of A and [H-L]. i.e. A-[HL]. But the contents of A
and [HL] are not changed.
15. CPI F0 H Compare the contents of A and F0. i.e. A-F0. But the contents of A and
F0 are not changed.
16. RLC Rotate Accu. Left.
17. RRC Rotate Accu. Right
18. RAL Rotate Accu. Left through carry.
RAR Rotate Accu. right through carry.
BRANCH GROUP: -
Unconditional
1. J MP 2000 J ump to the location 2000
2. CALL 2000 J ump to the location 2000
Conditional
1. J Z 2000 J ump to the location 2000 if there is zero in result i.e. in Accu.
2. J NZ 2000 J ump to the location 2000 if there is non zero in result i.e. in Accu.
3. J C 2000 J ump to the location 2000 if there is carry in result i.e. in Accu.
4. J NC 2000 J ump to the location 2000 if there is no carry in result i.e. in Accu.
5. J P 2000 J ump to the location 2000 if result is positive in Accu.
6. J M 2000 J ump to the location 2000 if result is negative in Accu.
7. J PE 2000 J ump to the location 2000 if result contain even parity in Accu.
8. J PO 2000 J ump to the location 2000 if result contain odd parity in Accu.
9. RET Return from the subroutine.
10. PUSH C Push the contents of C reg. into stack.
11. POP D Retrieve the contents of stack top into reg C.
12. HLT End of the program.
13. NOP No operation.
OPCODE FORMAT
Registered code Register pair code
B 000 BC 00
C 001 DE 01
D 010 HL 10
E 011
H 100
L 101
M 110
A 111
ADDRESSING MODES
THE VARIOUS WAY OF SPECIFYING THE DATA TO BE OPERATED ON ARE CALLED AS ADDRESSING
MODES. 8085 PROVIDE THE FOLLOWING ADDRESSING MODES.
IMMEDIATE ADDRESSING MODE:-
THE DATA TO BE USED IS GIVEN IN THE INSTRUCTION ITSELF. IMMEDIATE ADDRESSING
MODEINSTRUCTION ARE EITHER 2 BYTE OR 3 BYTE LONG.
EX. MVI A, 20H ADI 30H LXI H, C200H
REGISTER ADDRESSING MODE
THIS MODE OF ADDRESSING SPECIFY THE REGISTER OR REGISTER PAIR THAT CONTAIN THE DATA.
EX. MOV A, B ADD B
DIRECT ADDRESSING MODE
IN THIS MODE THE OPERAND IS GIVEN BY A DIRECT ADDRESS WHERE THE DATA IS PRESENT. THE
DIRECT ADDRESSING MODE INSTRUCTION IS A 3 BYTE INST.
EX. LDA 2000H STA 2000H
INDIRECT ADDRESSING MODE
HERE INST. DOES NOT HAVE ADDRESS OF THE DATA. BUT THE INSTRUCTION POINT WHERE THE
ADDRESS IS STORED
EX. MOV A, M MOV M, A
IMPLIED OR INHERENT ADDRESSING MODE
THIS MODE DOES NOT REQUIRED ANY OPERAND. THE DATA IS SPECIFIED WITHIN THE OPCODE
ITSELF.
EX. RAL RAR
INSTRUCTION TYPE
The first part of the instruction is called opcode and the second part is called operand. The operand may be either
8 bit data or memory location. Depending upon the number of bytes required to specify an operation the
instruction are of 3 bytes.
ONE BYTE INSTRUCTION:-
A 1 byte instruction include the opcode and the operand in the 8 bits only i.e. One byte
MOV A, B 01 111 000 =78H
MOV A, C 01 111 001 =79H
ADD B 1000 0 000 =80H
TWO BYTE INSTRUCTION:-
The 2 byte instruction uses first byte to specify the operation and second byte to specify the operand.
MVI A, 20 0011 1110 0010 0000
MVI B, 30 0000 0110 0011 0000
THREE BYTE INSTRUCTION:-
The 3 byte instruction uses first byte to specify the operation, second and third bytes are used to specify the
operand. Generally those instruction are used to specify memory address.
LDA ADDRESS
LDA 2000H 0011 1010 0010 0000 0000 0000
INSTRUCTION SET
They are classified in to following group.
DATA TRANSFER OPERATION
This group of instruction copies data from source to destination
MOV A, B MOV A, M MVI R, DATA LDA 2000H LXI H 2000H
LHLD 2000H LDAX 2000
ARITHEMATIC OPERATION
This group of instruction perform arithematic operation like addition subtraction
. ADD R ADD M ADC D ADC M ADI F0
DAD R INR R INX H DCR R DCX H
LOGICAL OPERATION
This group of instruction perform logical operation such as and, or, not etc
ANA R ANA M ANI DATA ORA R
XRA R CMA CMP R RAL
BRANCH OPERATION
This group of instruction change the path of program execution or sequence.
a) CONDITIONAL b) UNCONDITIONAL
J C ADD. J NC ADD. CALL ADDRESS
J Z ADD. J NZ ADD J MP ADDRESS
STACK AND MACHINE OPERATION
This group of instruction perform stack and machine control function.
PUSH R POP R NOP HLT
IO DATA TRANSFER TECHNIQUE
THE I/O MODULE IS USED TO TRANSFER DATA BETWEEN MICROPROCESSOR AND
EXTERNAL DEVICE. ALL DEVICES SHOULD BE COMPATIABLE IN SPEED TO THAT OF
MICROPROCESSOR. BUT ALL DEVICE ARE NOT SPEED COMPATIABLE. TO SOLVE THE
PROBLEM OF SPEED MISMATCH THE FOLLOWING DATA TRANSFER TECHNIQUE ARE TO
BE USED.
MICROPROCESSOR CONTROLED:-
HERE DATA IS TRANSFERRED BY MICROPROCESSOR, TO TRANSFER ONE BYTE OF DATA
BETWEEN MEMORY AND IO, IT IS REQUIERD TO EXECUTE SEVERAL INST. THIS TYPE OF
TRANSFER WILL BE USED WHEN THE SPEED OF IO IS LESS THAN OR EQUAL TO THA M.P.
PROGRAMMED I/O:-
HERE I/O TRANSFER IS DONE COMPLETELY UNDER THE CONTROL OF THE PROGRAM.
THE M.P EXECUTE I/O OR MEMORY BASED INST. TO ACCESS THE I/O DEVICE.
INTERRUPT I/O
THE PROGRAMMED I/O TECH. WASTE THE MAX. TIME OF M.P. TO OVER COME THE DRAW
BACK, IN INTERRUPT I/O M.P DOES NOT CHECK STATUS OF I/O DEVICE BUT THE I/O
DEVICE SENDS REQUEST TO THE M.P WHENEVER IT IS READY TO ACCEPT DATA OR TO
TRANSFER DATA.
DMA CONTROLLED
THIS TRANSFER WILL BE USED WHEN SPEED OF I/O IS MORE THAN THE SPEED OF M.P.
HERE DATA IS TRANSFERRED BETWEEN MEMORY AND I/O DIRECTLY. THIS TYPE OF
TECH. IS USED WHEN THE LARGE AMOUNT OF DATA IS PRESENT.
I/O mapped I/O: -
In this data transfer technique 8085 uses IO/M signal to distinguish
between I/O and memory operation. IN instruction is used to read the data
from specified port address to the accumulator only. OUT instruction is
used to transfer the data from accumulator to specified port address only.
When 8085 execute any IN or OUT instruction it place device address (Port
number) on the de multiplexed low order address bus as well as the high
order address bus. The address or port number can be any of the 256 i.e. from 00 to FF.
In this method I/O address is 8 bit (IN F0 H). IOW & IOR signals are used to control read
& write operation. Instructions are only IN & OUT. Data transfer is between any
accumulator and I/O device. Maximum numbers of I/O devices are 256.
Memory mapped I/O: -
In this data transfer technique 8085 assigned any identified 16-bit address.
The memory related instruction transfer the data between I/O devices. In
this method every instruction that refer to a memory location can control
I/O also. In this method device address is 16 bit. Thus A0 to A 15 lines are
used to generate device address. MEMR & MEMW control the read &
write operation. Instruction LDA, STA, LDAX Rp, STAX Rp, MOV r, M, MOV M, r. are the
Data transfer is between any register and I/O device. Maximum numbers of I/O devices are
65,536.
To find the addition
of two eight bit
numbers sum is 8
bits.
LXIH 2501 H
MOV A,M
INX H
ADD M
STA 2503 H
HLT
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ADDITION OF TWO 8-BIT NUMBER,
SUM 16 BITS
LXI H,2501H
MVI C,00
MOV A,M
INX H
ADD M
J NC HEAD
INR C
HEAD STA 2503H
MOV A,C
STA 2504H
HLT
To find the subtraction
of two eight bit
numbers
LXIH 2501 H
MOV A,M
INX H
SUB M
INX H
MOV M,A
HLT
DECIMAL ADDITION OF TWO 8-
BIT NUMBER ; SUM 16-BITS
LXI H,2501H
MVI C,00
MOV A,M
INX H
ADD M
DAA
J NC AHEAD
INR C
AHEAD STA 2503H
MOV A,C
STA 2504H
HLT
Decimal substraction of two 8-bit
number
LXI H,2501H
MVI C,00
MOV A,M
INX H
SUB M
DAA
J NC AHEAD
INR C
AHEAD STA 2503H
MOV A,C
STA 2504H
HLT
To shift an 8-bit number to
left by two bits
LXIH 2501 H
MOV B,M
MOV A,M
ADD B
ADD B
STA 2502 H
HLT
To shift an 16 bit number left
by two bit
LHLD 2501
DAD H
DAD H
SHLD 2503
HLT
ADDITION OF 2 16 BIT
NUMBER. SUM IS 16 BIT OR
MORE.
LHLD 2501 H
XCHG
LHLD 2503 H
MVI C, 00 H
DAD D
J NC HEAD
INR C
HEAD SHLD 2505 H
MOV A, C
STA 2507
HLT
To mask off 4 LSB's of
8 bit number
LDA 2501 H
ANI F0 H
STA 2502 H
HLT
To mask off 4 MSB's of
8 bit number
LDA 2501 H
ANI 0F H
STA 2502 H
HLT
To mask ON 4 LSB's
of 8 bit number
LDA 2501 H
ORI 0F H
STA 2502 H
HLT
To mask ON 4 MSB's
of 8 bit number
LDA 2501 H
ORI F0 H
STA 2502 H
HLT
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To find square from look up table
2600 00 LDA 2500 H
2601 01 MOV L, A
2602 04 MVI H, 26
2603 09 MOV A, M
2604 16 STA 2501 H
2605 25 HLT
2606 36
2607 49
2608 64
2609 81
To find the largest of two numbers
LXIH 2500
MOV A, M
INX H
CMP M
J NC HEAD
MOV A, M
HEAD STA 2502
HLT
To find the smallest of two numbers
LXIH 2500
MOV A, M
INX H
CMP M
J C HEAD
MOV A, M
HEAD STA 2502
HLT
WAP in 8085 to add 16 bit data
1234H & 4321H.
MVI B, 12 H
MVI C, 34 H
MVI D, 43 H
MVI E, 21 H
MOV A, E
ADD C
MOV L, A
MOV A, D
ADC B
MOV H, A
HLT
To find the largest number in data array
LXIH 2500 H
MOV C,M
INX H
MOV A,M
DCR C
BACK INX H
CMP M
J NC LOOP
MOV A,M
LOOP DCR C
J NZ BACK
STA 2450 H
HLT
To find the smallest number in data array
LXIH 2500 H
MOV C,M
INX H
MOV A,M
DCR C
BACK INX H
CMP M
J C LOOP
MOV A,M
LOOP DCR C
J NZ BACK
STA 2450 H
HLT
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To find the smallest number in data array from 2501 to 2509.
Total no. are 8. and the count is stored in 2500.
LXIH 2500 H
MOV C,M
INX H
MOV A,M
DCR C
BACK INX H
CMP M
J C LOOP
MOV A,M
LOOP DCR C
J NZ BACK
STA 2450 H
HLT
Sum of series of 8 bits numbers, sum is 16 bits
LXI H 2500 H
MOV C, M
MVI A, 00 H
MOV B, A
Loop INX H
ADD M
JNC Head
INR B
Head DCR C
JNZ Loop
STA 2450 H
MOV A, B
STA 2451 H
HLT
To arrange the array in descending order. Data is stored from 2500 onwards.
Count is in the location 2500. Store the result on 2601 location.
LXI D, 2601 H To store result
LXI H, 2500 H Count address
MOV B, M
Start CALL 2200 H
To find largest number STAX D
2200 LXIH 2500 CALL 2050 H
MOV C, M INX D
MVI A, 00 H DCR B
LOOP INX H JNZ Start To replace A with 00 H
CMP M HLT 2050 LXI 2500 H
JNC HEAD MOV C, M
MOV A, M Back INX H
HEAD DCR C CMP M
JNZ Loop JZ Go
RET DCR C
JNZ Back
Go MVI A, 00 H
MOV M, A
RET
TO ARRANGE THE ARRAY IN ASCENDING ORDER
LXI D, 2601 H To store result
LXI H, 2500 H Count address
MOV B, M
Start CALL 2200 H
To find smallest number STAX D
2000 LXIH 2500 CALL 2050 H
MOV C, M INX D
MVI A, FF H DCR B
Loop INX H JNZ Start To replace A with FF H
CMP M HLT 2050 LXI 2500 H
JC HEAD MOV C, M
MOV A, M Back INX H
HEAD DCR C CMP M
JNZ Loop JZ Go
RET DCR C
JNZ Back
Go MVI A, FF H
MOV M, A
RET Microprocessor / Microcontroller & Embedded System
Register B=75 H is interpreted as packed BCD. Unpack the BCD digit
and save them in D & E REGISTER.
PACKED BCD = XY UNPACKED BCD1 = 0X, BCD2 = 0Y
MVI B, 75 H
MOV A, B
ANI F0 H
RRC
RRC
RRC
RRC
MOV D, A
MOV A, B
ANI 0F
MOV E, A
HLT
MULTI BYTE ADDITION MULTI BYTE SUBTRACTION
3A9C8A67 3A9C8A67
+9B476C8B -9B476C8B
LXI H 2500 H LXI H 2500 H
MOV C, M MOV C, M
INX H INX H
LXI D 2601 H LXI D 2601 H
ORA A // To set carry flag to 0 ORA A // To set carry flag to 0
Loop LDAX D Loop LDAX D
ADC M SBB M
MOV M, A MOV M, A
INX H INX H
INX D INX D
DCR C DCR C
J NZ Loop J NZ Loop
HLT HLT
Multi byte decimal addition Multi byte decimal subtraction
3A9C8A67 3A9C8A67
+9B476C8B -9B476C8B
MOV C, M MOV C, M
INX H INX H
LXI D 2601 H LXI D 2601 H
ORA A ORA A
Loop LDAX D Loop LDAX D
ADC M SBB M
DAA DAA
MOV M, A MOV M, A
INX H INX H
INX D INX D
DCR C DCR C
J NZ Loop J NZ Loop
HLT HLT
MOVE A BLOCK OF DATA FROM ONE SECTION OF MEMORY
TO ANOTHER SECTION OF MEMORY.
Alternate Method
LXI H 2000 H LXI 2000 H
MOV C, M LDAX D
INX H MOV C, A
LXI D 2201 INX D
Loop MOV A, M LXI H 2201H
XCHG Loop LDAX D
MOV M ,A MOV M ,A
XCHG INX H
INX H INX D
INX D DCR C
DCR C J NZ Loop
J NZ Loop HLT
HLT
ONE'S COMPLEMENT OF TWO'S COMPLEMENT OF
A 16 BIT NUMBER A 16 BIT NUMBER
MOV A, M MVI B, 00 H
CMA MOV A, M
STA 2503 H CMA
INX H ADI 01
MOV A , M STA 2503 H
CMA J NC GO
STA 2504 INR B
HLT GO INX H
MOV A, M
CMA
ADD B
STA 2504 H
HLT
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Looping for large data
MVI D, FF H
LOOP MVI C, FF H
BACK DCR C
J NZ BACK
DCR D
J NZ LOOP
HLT
Find the negative numbers in a block of data.
LDA 2200 H
MOV C, A Count in C
MVI B, 00 H
LXI H, 2201 H First data
BACK MOV A, M
ANI 80 H Check MSB is 1
J Z LOOP
INR B
LOOP INX H
DCR C
J NZ BACK
MOV A,B
STA 2300 H
HLT
FIND THE POSITIVE NUMBERS IN A BLOCK
OF DATA.
LDA 2200 H
MOV C, A Count in C
MVI B, 00 H
BACK MOV A, M
ANI 80 H Check MSB is 1
J NZ LOOP
INR B
LOOP INX H
DCR C
J NZ BACK
MOV A,B
STA 2300 H
HLT
TO COUNT NUMBERS OF 1S IN A DATA
MVI D, 0A H Given data
MVI B, 00 H
MVI C, 08 H Total bit count
BACK RAR
J NC LOOP
INR B
LOOP DCR C
J NZ BACK
HLT
TO COUNT NUMBERS OF 0S IN A DATA
MVI D, 0A H Given data
MVI B, 00 H
MVI C, 08 H Total bit count
BACK RAR
J NC LOOP
INR B
LOOP DCR C
J NZ BACK
SBI A, 08 H
HLT
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CALCULATE THE SUM OF SERIES OF EVEN NUMBERS
LDA 2200 H
MOV C, A Count in C
MVI B, 00 H
BACK MOV A, M
ANI 01 H
J NZ LOOP
MOV A, B Initially first making A = 00 H
ADD M
MOV B, A
LOOP INX H
DCR C
J NZ BACK
STA 2210 H
HLT
Separate even numbers from a given numbers
LXI H, 2200 H // To retrieve data
LXI D, 2300 H // To store the data
MVI C, 32 H // From 50 numbers
BACK MOV A, M
ANI 01 H // Check LSB = 1
J NZ LOOP
MOV A, M
STAX D // Store A in DE Location
INX D
LOOP INX H
DCR C
J NZ BACK
HLT
MULTIPLICATION OF TWO NUMBERS: -
LHLD 2501 H // Get Multiplicand
XCHG // Multiplicand In HL
LDA 2503 H //Multiplier in Accu.
LXI H, 0000 H // Initial product = 00 H
MVI C, 08 H // Eight times
LOOP DAD H // Shift product by 1 bit
RAL // Rotate multiplier left by one bit. Is MSB = 1?
J NC HEAD
DAD D // Product =product+multiplicendHEAD
DCR C
J NZ LOOP
SHLD 2504 H
HLT
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PIN DIAGRAM / BLOCK DIAGRAM 8086
8086 is a 16-bit microprocessor with a 16-bit data bus & 20 bit Address bus.
AD15-AD0 Multiplexed address(ALE=1)/data bus(ALE=0).
A19/S6-A16/S3 (multiplexed)
High order 4 bits of the 20-bit address OR status bits S6-S3.
M/IO Indicates if address is a Memory or IO address.
RD When 0, data bus is driven by memory or an I/O device.
WR If 0, Microprocessor is driving data bus to memory or an I/O device.
ALE (Address latch enable)
When 1, address data bus contains a memory or I/O address.
DT/R (Data Transmit/Receive) Data bus is transmitting/receiving
DEN (Data bus Enable) Activates external data bus buffers.
S5: Indicates condition of IF flag bits.
INTR When 1 and IF=1, microprocessor prepares to service interrupt. INTA
becomes active after current instruction completes.
INTA Interrupt Acknowledge generated by the microprocessor in response
to INTR. Causes the interrupt vector to be put onto the data bus.
NMI Non-maskable interrupt. Similar to INTR except IF flag bit is not consulted and
interrupt is vector
MN/ MX Select minimum (5V) or maximum mode (0V) of operation.
BHE Bus High Enable. Enables the most significant data bus bits (D 15 -D 8 )
during a read or write operation.
READY Used to insert wait states (controlled by memory and IO for reads/writes) into
the microprocessor.
RESET Microprocessor resets if this pin is held high for 4 clock periods.
TEST An input that is tested by the WAIT instruction.
HOLD Requests a direct memory access (DMA). When 1, microprocessor stops and
places address, data and control to the DMA.
HLDA Indicates that the microprocessor has entered the hold state.
R0/GT1 & R0/GT0 Request/grant pins request/grant direct memory accesses (DMA)
during maximum mode operation.
LOCK Lock output is used to lock peripherals off the system. Activated by using the
LOCK: prefix on any instruction.
QS1 and QS0 The queue status bits show status of internal instruction queue. Provided for
access by the numeric coprocessor (8087).
8086 INTERNAL ARCHITECTURE
Its internal register r 16 bit wide and its data bus, 16 bit wide and can perform arithmetic
operation on 16 bit numbers. It uses 16 bit instructions. The m.p can read or write a 16 bit data
from or to memory. It can also read or write 16 bit data from or to i/o device. The address bus is
20 bit wide i.e. It can access 1 Mb of memory location.it consist of two independent parts,
execution unit (EU) & bus interface unit (BIU).
The EU contain an instruction decoder, a 16 arithmetic and logic unit, a 16 bit flag register, 8
eight bit GPR, two pointer register and two index register.
The BIU have FIFO based register of size 6 bytes in length called queue. The BIU pre fetch the
instruction from memory and store them in queue. The EU get the next instruction from queue.
This tech. Is called pipelining.
It uses only 9 bits, in flag register, six of which are known as conditional and remaining three
are known as general flags.
OV OVERFLOW FLAG DF - DIRECTION FLAG
IF - INTERRUPT FLAG TF - TRAP FLAG
SF - SIGN FLAG ZF - ZERO FLAG
AF - AUX. CARRY FLAG
CF - CARRY FLAG PF - PARITY FLAG
|---------------- 8086 FLAGS REGISTER (16-BITS) ----------------|
-- -- -- -- OF DF IF TF SF ZF -- AF -- PF -- CF
8086 REGISTERS
GENERAL PURPOSE REGISTERS
AX - 16-BIT ACCUMULATOR, CONTAINS AH AND AL
BX - BASE G.P. REGISTER, CONTAINS BH AND BL SUBREGISTERS.
CX - 16-BIT COUNTER REGISTER, CONTAINS CH AND CL
DX - DATA REGISTERR, CONTAINS DH AND DL SUBREGISTERS.
POINTER REGISTERS
IP - THE INSTRUCTION POINTER REGISTER.
SP - THE STACK POINTER REGISTER.
BASE REGISTERS
BX - BASE G.P. REGISTER (ALSO A GENERAL PURPOSE REGISTER).
BP - BASE POINTER REGISTER.
INDEX REGISTERS
SI - SOURCE INDEX REGISTER.
DI - DESTINATION INDEX REGISTER.
SEGMENT REGISTERS
CS - CODE SEGMENT REGISTER.
SS - STACK SEGMENT REGISTER.
DS - DATA SEGMENT REGISTER - DEFAULT FOR DATA ACCESS.
ES - EXTRA SEGMENT REGISTER.
COMMON SEGMENT/OFFSET PAIRS
SS:SP - THE STACK POINTER.
CS:IP - THE PROGRAM COUNTER.
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Memory Segmentation of 8086: -
Q.1 FIND THE PHYSICAL ADDRES OF FIRST AND LAST LOCATION OF AS
SEGMENT. SEGMENT BASE IS 1000H.
PHYSICAL ADDRESS OF FIRST LOCATION IS 1000:0000H i.e.
1000H X 10H + 0000H = 10000H
PHYSICAL ADDRESS OF LAST LOCATION IS 1000:FFFFH i.e.
1000H X 10H + FFFFH = 1FFFFH
Q.2 FIND THE PHYSICAL ADDRES OF FIRST LOCATION OF SEGMENTS
BASE 1000H AND 1001H.
1000H X 10H + 0000H = 10000H
1001H X 10H + 0000H = 10010H
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Instruction of 8086: -
DATA TRANSFER: -
MOV AX, CX Move the contents of reg CX to AX.
MOV DH, CL Move the contents of reg DH to CL.
MOV DL, 08 H Move the data 08 H to DL reg.
MOV CX, 0AFF H Move the data 0AFF H to the reg CX.
MOV DX, [08 H] Move the data from the PA calculated from 0008
+ DS to reg DX. Eg. DS=2000. Then PA =20008. i.e.
20008 to DH and 20009 to DL.
MOV AX, [09FA H] Move the data from the PA calculated from 09FA
+ DS to reg AX.
MOV CX, [BX] if BX=2000. Then 2000 + [DS]=PA
MOV AX, [SI] if SI=2000. Then 2000 + [DS]=PA
MOV AX, [BX+0008H] i.e. EA/offset=0008+value of BX. Then added
with DS to obtain PA.
MOV CX, [SI+0A2H]
MOV DX, [BX+SI+0AH]
PUSH CX Decrement SP by 2, copy CX to stack.
PUSH 2000 [BX] Decrement SP by 2, copy a word from Data segment
(PA =EA+ DS, EA=2000+[BX]) to stack.
POP CX Copy word from stack to CX, increment the SP by 2
POP 2000 [BX] Copy a word from stack to memory in DS.
(PA=EA+DS) EA=2000+[BX]
XCHG AL, CL Exchange byte with AL and CL
XCHG AX, BX Exchange bytes with AX and BX
XCHG AL, 2000[BX] Exchange byte with AL (PA=EA+DS,
EA=2000+[BX])
LEA CX, 2100 H Load CX with offset of 2100 H in DS
LEA AX, [BX][DI] Load AX with EA=[BX]+[DI] in DS
LDS CX, [391A H] Copy contents from offset 391A & 391B to CX & then
copy contents at offset 391C & 391D in DS
LES CX, [391A H] Copy data from offset 391A & 391B to CX & then copy
content at offset 391C & 391D in DS to ES register.
IN AL, 95 H Copy a byte from port 95 to AL.
IN AX, 95 H Copy a word from port 95 H to AX.
OUT F8 H, AL Copy contents of AL to 8 it port address F8 H
OUT F8 H, AX Copy contents of AX to 16 it port address F8 H
ARITHMETIC INSTRUCTION: -
ADD AL, F0 H Add the data of AL with F0 H data. AL+F0=AL
ADD AX, 2000[BX] Add the contents of AX with EA=2000+Contents of BX. PA
=EA+DS.
ADD DL, CL DL+CL=DL.
ADD AX, CX AX+CX=AX.
INC CL CL=CL+1 INC CX CX=CX+1
DEC DL DL=DL-1 DEC DXDX=DX-1
DAA Decimal adjustment after addition takes place.
ADC AL, CL ADC AX, CX ADC BX, 2000[BX]
SUB AL, F0 H AL=AL-F0 H
SUB AX, CX AX=AX-CX
SUB AX, 2000[BX] AX=AX-(PA(EA=2000+[BX]))
SBB AL, CL SBB AX, CX SBB BX, 2000[BX]
CMP AL, 01 Compare AL with data 01.
CMP AX, CX AX-CX, But contents of AX & CX are not changed.
Only status flag is set accordingly.
CMP CX, 2000 H PA=EA+(2000+[DS])
DAS Decimal adjustment after subtraction.
MUL BL AX = AL x BL (unsigned)
MUL BX AX x BX = high word in DX low word in AX (unsigned)
IMUL BL AX = AL x BL (signed)
IMUL BX AX x BX = high word in DX low word in AX (signed)
DIV CL AX/CL = Quotient in AL, reminder in AH
DIV CX (DX + AX)/CX Quotient in AX, reminder in DX
LOOP 2050 Decrement the contents of reg. CX by one & jump to
2050. If CX if not zero.
LOGICAL INSTRUCTION: -
NEG AL NEG AX Takes 2s complement of given data in register.
NOT AL NOT CX Takes 1s complement of given data in register.
AND BL, CL AND CX, DX AND AX, [000F H]
OR CL, BL OR DX, CX OR CX, [FFF0 H]
ROL CX, 01H Rotate value of register left with specifies count.
MOV CL, 03 H
ROL BL, CL
ROR CX, 01H Rotate value of register right with specify count.
MOV CL, 03 H
ROR BL, CL
RCL CX, 01H Rotate value of register left with specifies count
with carry.
MOV CL, 03 H
RCL BL, CL
RCR CX, 01H Rotate value of register right with specify count
with carry.
MOV CL, 03 H
RCR BL, CL
8086 Program Example
NAME MAIN PROGRAM
DATA SEGMENT
DATA ENDS
CODE SEGMENT
ASSUME CS: 2000
ASSUME DS: 3000
MOV SI, 1100 H
MOV AX, [SI]
MOV BX, []
HLT
CODE ENDS
END
ADDITION OF TWO 16 BIT DATA. RESULT IS 16 BIT OR MORE.
NAME MAIN PROGRAM
DATA SEGMENT
ORG 1000 H
SUM DW 00H
CARRY DB 00H
DATA ENDS
CODE SEGMENT
ASSUME CS: 2000
ASSUME DS: 3000
ORG 1000 H
MOV AX, 20FF H
MOV BX, 40FF H
MOV CL, 00 H
ADD AX, BX
MOV SUM, AX
J NC LOOP
INC CL
LOOP MOV CARRY, CL
HLT
CODE ENDS
END
LARGEST 16 BIT NUMBER IN DATA ARRAY: -
DS=1000H, SI=0200H Count at 10200H =0A H
MOV AX, 0000 H // Initially Ax = 0000 H
MOV SI, 0200 H
MOV CX, [SI] // Count in reg Cx
BACK INC SI
INC SI // Point next data of 16 bit
CMP AX, [SI]
J NC GO
MOV AX, [SI]
GO LOOP BACK // Decrement Cx & J ump to back
MOV [0300], AX
HLT
SMALLEST 16 BIT NUMBER IN DATA ARRAY: -
MOV AX, 0000 H
MOV SI, 0200 H
MOV CX, [SI]
BACK INC SI
INC SI
CMP AX, [SI]
J C GO
MOV AX, [SI]
GO LOOP BACK
MOV [0300], AX
HLT
LARGEST 8 BIT NUMBER IN 8 BIT DATA ARRAY:
MOV AL, 00 H
MOV SI, 0200 H
MOV CX, [SI]
INC SI
BACK INC SI
CMP AL, [SI]
J NC GO
MOV AL, [SI]
GO LOOP BACK
MOV [0250], AL
HLT
SMALLEST 8 BIT NUMBER IN 8 BIT DATA ARRAY:
MOV AL, 00 H
MOV SI, 0200 H
MOV CX, [SI]
INC SI
BACK INC SI
CMP AL, [SI]
J C GO
MOV AL, [SI]
GO LOOP BACK
MOV [0250], AL
HLT
Sum of series of 16 bit numbers sum is 16 bit: -
MOV AX, 0000 H
MOV SI, 0200 H
MOV CX, [SI]
BACK INC SI
INC SI
ADD AX, [SI]
LOOP BACK
MOV [0300], AX
HLT
Sum of series of 16 bit numbers sum is 32 bit: -
MOV AX, 0000 H
MOV BX, 0000 H
MOV SI, 0200 H
MOV CX, [SI]
BACK INC SI
INC SI
ADD AX, [SI]
J NC GO
INC BX
GO LOOP BACK
MOV [0300], AX
MOV [0400], BX
HLT
MOVE A BLOCK OF DATA (BYTES) FROM ONE LOCATION TO OTHER
DS=1000 H ES = 2000H
MOV SI, 0200 H
MOV DI, 0302 H
MOV CX, [SI]
INC SI
INC SI
BACK MOV SB // Interchange byte from SI & DI
INC SI
INC DI
LOOP BACK
HLT
MOVE A BLOCK OF DATA (WORDS) FROM ONE LOCATION TO OTHER
DS=1000 H ES = 2000H
MOV SI, 0200 H
MOV DI, 0300 H
MOV CX, [SI]
INC SI
INC SI
BACK MOV SW // Interchange word from SI & DI
INC SI INC SI
INC DI INC DI
LOOP BACK
HLT
ADD TWO 16 BIT NUMBER SUM IS 16 BIT OR MORE: -
DS=1000H, SI=0200H
MOV CH, 00 H // Initially carry is 0
MOV SI, 0200 H
MOV AX, [SI] // First data in AX
INC SI
INC SI
MOV CX, [SI] // Second data in CX
ADD AX, CX
INC SI
INC SI // To store result
J NC GO
INC CH // Increment carry
GO MOV [SI], AX // Store result
INC SI
MOV [SI], CH // Store carry
HLT
ONES COMPLEMENT OF A 8 BIT NUMBER: -
MOV AH, [SI]
NOT AH
INC SI
MOV [SI], AH
HLT
ONES COMPLEMENT OF A 16 BIT NUMBER: -
MOV AX, [SI]
NOT AX
INC SI
INC SI
MOV [SI], AX
HLT
SHIFT AN 8 BIT NUMBER LEFT BY TWO BITS: -
MOV AL, [SI]
ADD AL, AL
ADD, AL, AL
INC SI
MOV [SI], AL
HLT
SHIFT AN 16 BIT NUMBER LEFT BY TWO BITS: -
MOV AX, [SI]
ADD AX, AX
ADD, AX, AX
INC SI
INCSI
MOV [SI], AX
HLT
TWOS COMPLEMENT OF A 8 BIT NUMBER: -
DS=1000H, SI=0200H
MOV AH, [SI]
NEG AH
INC SI
MOV [SI], AH
HLT
TWOS COMPLEMENT OF A 16 BIT NUMBER: -
DS=1000H, SI=0200H
MOV AX, [SI]
NEG AX
INC SI
INC SI
MOV [SI], AX
HLT
MASK ON 8 LSBS OF A 16 BIT NUMBER: -
DS=1000H, SI=0200H
MOV AX, [SI]
OR AX, 00FF H
INC SI
INC SI
MOV [SI], AX
HLT
MASK ON 8 MSBS OF A 16 BIT NUMBER: -
DS=1000H, SI=0200H
MOV AX, [SI]
OR AX, FF00 H
INC SI
INC SI
MOV [SI], AX
HLT
MASK OFF 8 LSBS OF A 16 BIT NUMBER: -
DS=1000H, SI=0200H
MOV AX, [SI]
AND AX, FF00 H
INC SI
INC SI
MOV [SI], AX
HLT
MASK OFF 8 MSBS OF A 16 BIT NUMBER: -
DS=1000H, SI=0200H
MOV AX, [SI]
AND AX, 00FF H
INC SI
INC SI
MOV [SI], AX
HLT
Difference between 8086 & 8088 M.P
8088 8086
1. It has only 8 data lines 1. It has 16 data lines
2. It has 4 byte instruction Q. 2. It has 6 byte instruction Q.
3. Its pin 34 is SS0 bar. 3. Its pin 34 is BHE bar.
4. In min mode pin 28 is IO/M bar 4. In min mode pin 28 is M/IO bar
5. It does not have BHE bar. 5. It has BHE bar for higher order
address bus.
Introduction to 80186: -
1. 80186 is a 16 bit M.P.
2. It is a 68 pin IC with +5 V supply.
3. It consist of 2 8086 CPU.
4. It has 20 bit address bus.
5. It can operate on two different clock speed i.e. 8
MHz & 6 MHz.
6. It has 10 new instruction compared with 8086.
7. It has on chip timer, interrupt controller, DMA &
clock generator.
8. It has all the register same with 8086.
9. It has same address modes, instruction as of 8086.
1. It is a 16 bit microprocessor.
2. Especially designed for multitasking & multiuser.
3. It can access upto16 MByteof memory.
4. It can operate from 8 MHz to 12.5 MHz.
5. It is a 68 pin DIP IC.
6. It has 24 address lines & 16 bit data lines.
7. It has same address modes, instruction as of 8086.
8. It consist of 4 units (Execution unit, bus unit, Instruction unit, address unit)
9. In protected mode of operation it can access upto1 gigabyte of memory.
Power PC
It is a RISC microprocessor designed to meet a standard which was jointly designed
by Motorola, IBM, and Apple Computer. The PowerPC standard specifies a
common instruction set architecture (ISA), allowing anyone to design and fabricate
Power PC processors. The PowerPC architecture is based on the IBM POWER
architecture used in IBM's workstations. Currently IBM and Motorola are working
on PowerPC chips. The PowerPC standard specifies both 32-bit and 64-bit data
paths. Early implementations were 32-bit (e.g. PowerPC 601); later higher-
performance implementations were 64-bit (e.g. PowerPC 620). A PowerPC has 32
integer registers (32- or 64 bit). The POWER CPU chip and PowerPC have a (large)
common core, but both have instructions that the other doesn't.
The PowerPC offers the following features that POWER does not:
The real time clock (upper and lower) was replaced with the timebase registers
(upper and lower)
64-bit instruction operands, registers, etc. (in 64 bit processors).
1. It is 32 bit & improved version of 8086,80186 & 80286 M.P
2. Its register & ALU is 32 bit. As well its address & data bus is 32 bit.
3. Instruction, data read & write operation are two times faster then 80286.
4. Maximum size of physical memory is 64 MB.
5. It is available in two version: - 80386 DX & 80386 SX.
6. 80386 DX has 32 bit address & data bus.
7. 80386 SX has 16 bit data bus & 24 bit address bus.
8. It consist of timer, counter, interrupt, DMA on chip.
9. It can work in three modes: -
a) Real addressing modes
b) Protected virtual address modes
c) Virtual 8086 modes.
10. Internal architecture is same as of 80286.
1. It is a 32 bit M.P with higher performance then 80386.
2. It consist of 1.2 million transistor & works three times faster
then 80386.
3. It has five stages of pipelining.
4. It has 30 bit address bus & 32 bit data bus.
5. It consist of timers, counters, DMA, interrupt controller on chip.
6. It can operate on 100 MHz.
7. It is software compatible with 80386.
8051 Microcontroller & Embedded System: -
What is Embedded System?
Embedded System is a collection of pure electronics
hardware & software to perform few dedicated task on
real time fashion.
Major components of Embedded System:-
1. Microcontroller (8051, AVR, PIC, ARM)
2. ADC/DAC/RTC
3. Motor(AC/DC/Stepper)
4. Sensor (Light/IR/Finger/Voice)
8051 is a general purpose 8 bit micro controller. 8 bit means its data bus & CPU is 8 bit wide.
Intel 8051 micro controller was designed by the company Intel. But is rarely available & costly
also. Therefore most of the company are using Atmel 89C51/89C52/89S51/89S52 micro
controller, which is having 100 % same configuration as of Intel 8051.
Major companies manufacturing the 8051 series micro controller : -
1. Intel / Atmel / Philips / Motorola / Dallas
Main features of 8051 series micro controller: -
1. 40 pin IC package DIP (Dual in line package)
2. 4K byte of flash memory (EEPROM) 000 H to FFF H
3. 128 byte of RAM 00H to 07 F
4. 4 Port, P0, P1, P2, P3 Each port of 8 bits, like P10, P11,P12, P13, P14, P15, P16 &
P17
P30, P31, P32..P37.
1. 2 Timers T0, T1
2. 2 Counters
3. 1 Serial Communication (UART)
Atmel 89C51 4K, 128, 2 Timer (4K Means 000H to FFFH)
Atmel 89C52 8K, 256, 3 Timer (8K Means 0000H to 1FFFH)
Atmel 89S51 4K, 128, 2 Timer, 1 Watch dog timer
Atmel 89S52 8K, 256, 3 Timer, 1 Watch dog timer
RAM ORGANISATION OF 8051
The 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip
on the 8051 so it is the fastest RAM available, and it is also the most flexible in terms of
reading, writing, and modifying its contents.
The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8
bytes (00h - 07h) are "register bank 0". Bit Memory also lives and is part of internal RAM.
Bit memory actually resides in internal RAM, from addresses 20h through 2Fh.
The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used
by user variables that need to be accessed frequently or at high-speed. This area is also
utilized by the microcontroller as a storage area for the operating stack.
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The 8051 is a flexible microcontroller with a relatively large number of modes of
operations. Your program may inspect and/or change the operating mode of the 8051 by
manipulating the values of the 8051's Special Function Registers.
SFRs are accessed as if they were normal Internal RAM. The only difference is that
Internal RAM is from address 00h through 7Fh whereas SFR registers exist in the address
range of 80h through FFh.
Each SFR has an address (80h through FFh) and a name. The following chart provides a
graphical presentation of the 8051's SFRs, their names, and their address.
Program status (PSW) word of 8051
Cy Ac F0 RS1 RS0 OV x P
Cy Carry
Ac Auxiliary carry
P Parity
RS1 RS0
0 0 bank 0
0 1 bank 1
1 0 bank 2
1 1 bank 3
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SFR OF 8051 MICROCONTROLLER
The Accumulator The Accumulator, as its name suggests, is used as a
general register to accumulate the results of a large number of instructions. It
can hold an 8-bit (1-byte) value and is the most versatile register
The " R" registers The "R" registers are a set of eight registers that are
named R0, R1, etc. up to and including R7.
The " B" Register The "B" register is very similar to the Accumulator in
the sense that it may hold an 8-bit (1-byte) value.
The Program Counter (PC) The Program Counter (PC) is a 2-byte
address which tells the 8051 where the next instruction to execute is found in
memory
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ADDRESSING MODES: -
An "addressing mode" refers to how you are addressing a given memory location. In
summary, the addressing modes are as follows, with an example of each:
Immediate Addressing
MOV A,#20H MOV R4,#64H MOV B,40H
Direct Addressing
MOV A,30H MOV 56,A MOV B,04H
Indirect Addressing
MOV A,@R0 MOV @R1,B
Register Addressing
MOV A,R0 MOV R2,A ADD A,R7
STACK Addressing
Push 05 = Push R5 Pop 02 = Pop R2
ADC & DAC
A ADC, inputs an analog voltage or current and output the binary signal. In block diagram
form, it looks like this:
A DAC, on the other hand, inputs a binary number and outputs an analog voltage or
current signal. In block diagram form, it looks like this:
Together, they are often used in digital systems to provide complete interface
with analog sensors and output devices for control systems such as those used
in automotive engine controls:
Flash ADC
Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of a
series of comparators, each one comparing the input signal to a unique reference voltage. The
comparator outputs connect to the inputs of a priority encoder circuit, which then produces a binary
output. The following illustration shows a 3-bit flash ADC circuit. Vref is a stable reference voltage
provided by a precision voltage regulator as part of the converter circuit, not shown in the
schematic. As the analog input voltage exceeds the reference voltage at each comparator, the
comparator outputs will sequentially saturate to a high state. The priority encoder generates a
binary number based on the highest-order active input, ignoring all other active inputs.
Digital ramp ADC
Also known as the stairstep-ramp, or simply counter A/D converter. The basic idea is to
connect the output of a free-running binary counter to the input of a DAC, then compare
the analog output of the DAC with the analog input signal to be digitized and use the
comparator's output to tell the counter when to stop counting and reset. As the counter
counts up with each clock pulse, the DAC outputs a slightly higher (more positive) voltage.
This voltage is compared against the input voltage by the comparator. If the input voltage
is greater than the DAC output, the comparator's output will be high and the counter will
continue counting normally. Eventually, though, the DAC output will exceed the input
voltage, causing the comparator's output to go low. This will cause two things to happen:
first, the high-to-low transition of the comparator's output will cause the shift register to
"load" whatever binary count is being output by the counter, thus updating the ADC
circuit's output; secondly, the counter will receive a low signal on the active-low LOAD
input, causing it to reset to 00000000 on the next clock pulse.
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Successive approximation ADC
One method of addressing the digital ramp ADC's shortcomings is the so-called
successive-approximation ADC. The only change in this design is a very special counter
circuit known as a successive-approximation register. Instead of counting up in binary
sequence, this register counts by trying all values of bits starting with the most-significant
bit and finishing at the least-significant bit. Throughout the count process, the register
monitors the comparator's output to see if the binary count is less than or greater than the
analog signal input, adjusting the bit values accordingly. The way the register counts is
identical to the "trial-and-fit" method of decimal-to-binary conversion, whereby different
values of bits are tried from MSB to LSB to get a binary number that equals the original
decimal number. The advantage to this counting strategy is much faster results: the DAC
output converges on the analog signal input in much larger steps than with the 0-to-full
count sequence of a regular counter.
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Tracking ADC
A third variation on the counter-DAC-based converter theme is, in my estimation, the most
elegant. Instead of a regular "up" counter driving the DAC, this circuit uses an up/down
counter. The counter is continuously clocked, and the up/down control line is driven by the
output of the comparator. So, when the analog input signal exceeds the DAC output, the
counter goes into the "count up" mode. When the DAC output exceeds the analog input,
the counter switches into the "count down" mode. Either way, the DAC output always
counts in the proper direction to track the input signal.
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Programmable Peripheral Interface (PPI) 8255:
-
Used to interface the I/O devices
It consist of three ports : -
Port A of 8 bits (PA0, PA1PA8)
Port B of 8 bits (PB0, PB1PB8)
Port C of 8 bits (PC0, PC1PC8)
Control Register is used to program
the functions of three ports.
Chip select (CS) : -Active low input pin
used to select the chip.
Read (RD) : -Active low signal used to
send the data to CPU through data lines.
Write (WR) : -Active low input signal
used to write the data to 8255 from CPU
D0-D7: -Bi-directional data lines for data
transfer between the CPU & 8255.
A1 A0 Select
0 0 PA (Port A)
0 1 PB (Port B)
1 0 PC (Port C)
1 1 Control register
Group A=PA + PC upper
Group B=PB + PC lower
Port C can be used individually
or it can be used as a hand
shake signal with PA & PB.
Control Register is selected
when A0=1, A1=1, CS=0 &
WR=0.
Read operation is not allowed
in control register.
There are two control word format for 8255: - 1. BSR 2. I/O Mode
If D7 bit of control register = 0 i.e. BSR mode, if D7 =1 I/ O mode
Bit Set Reset MODE: -
D
3
D
2
D
1
X X X
D3 D2 D1
Port C
0
0 0 PC0
0 0 1
0
1
0
1
0
1
PC1
0 1 PC2
0 1 PC3
1 0 PC4
1 0 PC5
1 1 PC6
1 1 PC7
1 Set
0 - Reset
0 BSR mode
1 I/O mode
I/O Mode: -
Mode 0=Basic I/O mode
Mode 1=Strobed I/O mode
Mode 2=Bi-directional I/O
Group B can be act as
mode 0 OR mode 1
Group A can be act as
mode 0, mode 1 or mode 2
*When the reset out of
8085 is is high, as it is
connected to the reset of
the 8255, 8255 will be
rested. It will clear control
word & all the ports are
set to input port.
Q: -Write a set of instruction to perform the following: -
Set the bit 4 of PC, Set the bit 1 of PC, Reset the bit 4 of PC
Assume the PA=10H, PB=11H & PC=12H & Control reg=13H
Ans: - MVI A, 09 MVI A, 03H MVI A,08
OUT 13H OUT 13H OUT 13 H
Reset the bit 4 of PC, Reset the bit 1 of PC, Set the bit 4 of PC
Assume the PA=10H, PB=11H & PC=12H & Control reg=15H
Ans: - MVI A, 09 MVI A, 03H MVI A,08
OUT 15H OUT 15H OUT 15 H
Port A as i/p port, Port B as o/p port, Port C upper o/p, Port C lower i/p.
Ans: - MVI A, 91
OUT CWR
Mode 0, Simple Input/Output Mode: -
1. All three port (PA, PB & PC provide simple input & output operation)
2. Simply the data will be written to the port or read from the port.
3. If the port is programmed as output, the outputs are latched.
4. If the port is programmed as input, the inputs are buffered.
5. When the CPU wants to send some data to output port, the CPU will first send
the address of the port on address lines, so CS & A0 & A1 will select the
appropriate port.
After selecting the port CPU will send data & control signal WR to write data
to port through data busses.
Q : Write a program to initialize port A and port C as output to send the
data to external devices and port B as input to receive the data from
input device.
Ans :First define the Control word
0 0 0 0 0 1 0 1 = 82 H
To access I/O devices IO/M must be
set. CS must be zero to enable the
PPI 8255.A0 and A1 are used to
select the ports and control registers
8086
8255
PAO
PBO
PCO
A0
A1
CS
D0 D7
A2
A14
A15
PA7
PB7
PC7
IO/M
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0= 8000H PortA
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1= 8001H PortB
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0= 8002H PortC
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1= 8003H CReg
MOV AL , 82H
MOV DX , 8003 ; Control register
OUT DX , AL ; load control word in control register
MOV AL , DATA
MOV DX , 8000 ; port A
OUT DX , AL ; load a data into port A
MOV DX , 8002 ; port B
OUT DX , AL ; load a data into port B
MOV DX , 8001 ; port B
IN AL , DX ;read data from port B and store in AL
HLT
Mode 1, Strobed Input/Output Mode: -
1. Both group A & group B can operate in mode 1.
2. Each group use 8 bit port (Either A or B) along with 3 bits of PC, which gives
the status of 8 bit port.
3. In group A, Port A in input port works with PC3, PC4, PC5.
4. In group A, Port A in output port works with PC3, PC6, PC7.
5. In group B, Port B in input & output port works with PC0, PC1, PC2.
6. If we use both port A & B simultaneously, then only 6 bits of PC will be used
& remaining 2 bits of PC can be used as simple I/O.
Mode 2, Strobed bi-directional I/O: -
1. Group A can be operate in Mode 2. This mode is used as input & output.
2. Port C is used as handshake signal (5 bits of Port C).
3. Group B can be used as Mode 0& Mode 1.
Mode 1 input mode: -
Handshake Signals are STB, IBF & INTR.
STB (Strobe input): - Active low input signal, peripheral will generate this
signal to indicate that it is going to transmit the data to the specified port.
With this signal peripheral will send the data to the specified port & will
go on checking the IBF signal.
IBF (Input buffer full): - Active high output signal, this signal is generated by
8255 in response to STB signal to indicate the peripheral devicethat data
is present in input port. If IBF signal is high peripheral will not send the
next data. IBF is reset when CPU reads input port.
INTR (Interrupt request): - Active high output signal given by 8255 to
interrupt the CPU. If STB=1, IBF=1 & INTE=1 then INTR=1, for all
other communication INTR=0.
INTE (Interrupt Enable): - It is internal flip flop, used to enable or disable
interrupt signal. IF INTE is set the interrupt will be generateddepending
upon STB & IBF.
Mode 1 output mode: -
Handshake Signals are ACK, OBF & INTR.
OBF (Output buffer full): - Active low output signal & input for peripheral,
When CPU write the data to output port it is indicated by OBF signal that
the data is available in output port. In response to the OBF peripheral
reads the data from port & acknowledge the CPU by ACK. Receivingthe
ACK 8255 removes OBF signal.
ACK (Acknowledgement): - Active low input signal for 8255 & output for
peripherals, When OBF is active indicating that data is available in output
port, the peripheral read the data & indicate by ACK.
INTR (Interrupt request): - Same as previous
INTE (Interrupt Enable): - Same as previous
Interrupt Driven & Status Driven I/P: -
Interrupt driven I/O: - INTR signal is connected as interrupt input to 8085. When
STB signal is received by 8255 generate IBF & put data on
data bus. In response to INTR signal, 8085 read data from
8255. The read will reset IBF & INTR. If I/O device want to
send next data it will check the IBF, if it is low it will repeat
the above steps.
Status driven I/O: - Port C is used as status word which give the status of
handshake signal. INTR signal is not used & INTE bit will be
reset. The service to 8255 is given by polling the status
register. CPU check IBF signal if it is high then data is read, if
IBF is low CPU will go on reading & checking the IBF signal.
Status Word
D7 D6 D5 D4 D3 D2 D1 D0
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Q: -What will be the control word for following: -
PA=Mode 1, Input, PB=Output & PC=Input
Ans: - BC H
Q: -Explain how the control word can be formed for a mixed mode: -
a) Port A Mode 1 Input, Port B Mode 0 Output, Port C upper & lower
both Input.
b) Port A Mode 2 Bi-directional, Port B Mode 0 Input, Port C upper &
lower both Input.
Ans: - a) B9 H
b) C3 H
Q: -Interface 8255 to 8085 using I/O mapped I/O. Give the address of
8255 ports & control register. Give detail of decoder design also.
Ans: -In I/O mapped I/O address of I/O ports is of 8 bits.
Contents of A0-A7 are copied on A8-A15
IO/M can be used as chip select.
1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 = 88 H PA
1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 = 89 H PB
1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 = 8A H PC
1 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 = 8B H CW
Q: -Interface 8255 to 8085 using memory mapped I/O. Give the address of
8255 ports & control register. Give detail of decoder design also.
1. In memory mapped I/O address of I/O ports is of 16 bits.
2. In memory mapped I/O control signal used for I/O device are
MEMW & MEMR. These can be generated by IO/M, RD & WR.
3. IO/M can be used as chip select.
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 8000H PA
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 = 8001H PB
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = 8002H PC
1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = 8003H CW
Q: -Interface two LEDs using common anode & common cathode.
Design the circuit & draw the interface. WAP to blink them
alternately. Ports address in I/O mapped I/O
Let LEDs are connected to PA0 &PA1. Let Control word = 40 H
1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 = 80H PA
1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 = 81H PB
1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 = 82H PC
1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 = 83H CW
MVI A, 80 H 80 to Accu.
OUT 83 H Accu. to CWR
AGAIN MVI A, 03 H 03 to Accu.
OUT 80 H Accu. to PA
CALL Delay
MVI A, 00 H 03 to Accu.
OUT 80 H Accu. to PA
CALL Delay
JMP AGAIN
Applications of 8255
1. Interfacing of Stepper motor
2. Interfacing of ADC and DAC
3. Interfacing of matrix Key board
4. Interfacing of Seven segment LED
5. Interfacing of sensors
6. Interfacing of various home appliances and
Industrial control elements
What are the various registers in 8085? - Accumulator register, Temporary register,
Instruction register, Stack Pointer, Program Counter are the various registers in
8085 .
In 8085 name the 16 bit registers? - Stack pointer and Program counter all have 16
bits.
What are the various flags used in 8085? - Sign flag, Zero flag, Auxillary flag, Parity
flag, Carry flag.
What is Stack Pointer? - Stack pointer is a special purpose 16-bit register in the
Microprocessor, which holds the address of the top of the stack.
What is Program counter? - Program counter holds the address of either the first
byte of the next instruction to be fetched for execution or the address of the
next byte of a multi byte instruction, which has not been completely fetched. In
both the cases it gets incremented automatically one by one as the instruction
bytes get fetched. Also Program register keeps the address of the next
instruction.
Which Stack is used in 8085? - LIFO (Last In First Out) stack is used in 8085.In this
type of Stack the last stored information can be retrieved first.
What happens when HLT instruction is executed in processor? - The Micro
Processor enters into Halt-State and the buses are tri-stated.
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What is meant by a bus?
A bus is a group of conducting lines that carriers data, address, & control signals.
Give an example of one address microprocessor? - 8085 is a one address microprocessor.
In what way interrupts are classified in 8085?
In 8085 the interrupts are classified as Hardware and Software interrupts.
What are Hardware interrupts? - TRAP, RST7.5, RST6.5, RST5.5, INTR.
What are Software interrupts? - RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.
Which interrupt has the highest priority? - TRAP has the highest priority.
Name 5 different addressing modes? - Immediate, Direct, Register, Register indirect, Implied
addressing modes.
How many interrupts are there in 8085? - There are 12 interrupts in 8085.
What is clock frequency for 8085? - 3 MHz is the maximum clock frequency for 8085.
What is the RST for the TRAP? - RST 4.5 is called as TRAP.
In 8085 which is called as High order / Low order Register? - Flag is called as Low order
register & Accumulator is called as High order Register.
Can an RC circuit be used as clock source for 8085? - Yes, it can be used, if an accurate clock
frequency is not required. Also, the component cost is low compared to LC or Crystal.
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Why crystal is a preferred clock source? - Because of high stability, large Q (Quality Factor) & the frequency that
doesnt drift with aging. Crystal is used as a clock source most of the times.
What does Quality factor mean? - The Quality factor is also defined, as Q. So it is a number, which reflects the lossless
of a circuit. Higher the Q, the lower are the losses.
What are level-triggering interrupt? - RST 6.5 & RST 5.5 are level-triggering interrupts.
How many bits does 8086 microprocessor have?
What is the size of data bus in 8086?
What is the size of address bus in 8086?
What is the max memory addressing capacity of 8086?
Which are the basic parts of 8086?
What are the functions of BIU?
What are the functions of EU?
What is the size of instruction queue in 8086?
What is the size of instruction queue in 8088?
Which are the registers present in 8086?
What is pipelining in 8086?
How many 16 bit registers are available in 8086?
Specify addressing modes for any instruction?
What is assembler directives?
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What is the size of flag register in 8086? Explain all.
Which is faster- Reading word size data whose starting address is at even or at odd address of
memory in 8086?
Which are the default segment base: offset pairs?
Which are the base registers in 8086?
Which is the index registers in 8086?
What is segment override prefix?
Whether macro reduces memory requirements?
What .model small stands for?
What is the supply requirement of 8086?
What is the relation between 8086 processor frequency & crystal frequency?
Functions of Accumulator or AX register?
Functions of BX register?
Functions of CX register?
Functions of DX register?
How Physical address is generated?
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What is the difference between near and far procedure?
What is the difference between Macro and procedure?
Which are pointers present in this 8086?
Which is by default pointer for CS/ES?
How many segments present in it?
What is the size of each segment?
Basic difference between 8085 and 8086?
Which operations are not available in 8085?
What is the difference between min mode and max mode of 8086?
What is the difference between instructions RET & IRET?
What is the difference between instructions MUL & IMUL?
What is the difference between instructions DIV & IDIV?
What is difference between shifts and rotate instructions?
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Which are strings related instructions?
Which are addressing modes and their examples in 8086?
What does u mean by directives?
What does u mean by Prefix?
What is macro?
What is diff between macro and procedure?
Types of procedure?
What do u mean by assembler?
What do u mean by linker?
What do u mean by loader?
What do u mean by compiler?
What do u mean by emulator?
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Which no. representation system you have used?
What is LEA?
What is @data indicates in instruction- MOV ax, @data?
What is maximum size of the instruction in 8086?
What is mul BX and div BX? Where result goes?
Where queue is present?
Stack related instruction?
Which flags of 8086 are not present in 8085?
What is the size of flag register?
Can you perform 32 bit operation with 8086? How?
Whether 8086 is compatible with Pentium processor?
How does U differentiate between positive and negative numbers?
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What is the advantage of using internal registers?
What is SI, DI and their functions?
Which are the pointers used in 8086 and their functions?
What is a type of queue in 8086?
What is minimum mode of 8086?
What is maximum mode of 8086?
Which are string instructions?
In string operations which is by default string source pointer?
In string operations which is by default string destination pointer?
What is IC 8251?
How many pins does IC 8251 have?
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Define baud rate.
Define bit rate.
Define mode word register of 8251 for asynchronous mode..
Define mode word register of 8251 for sync mode..
What is the significance of SYNC DETECT signal in 8251?
What is the significance of BREAK DETECT signal in 8251?
What is USART?
Why 8251 is called a USART?
What is simplex half & full duplex modes of communication?
What is the difference between asynchronous & synchronous mode of communication?
Explain control word format of 8251?
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Define command word register of 8251.
Define status word register of 8251.
What are the applications of 8251?
Whether write operation is possible with status word register?
What is hunt mode in 8251?
Explain block diagram IC 8251?
Explain the logic of 8251 program.
Explain the interfacing of 8251 with 8086.
Whether operation read is possible with command word register?
What is parity error in 8251?
What is over run error in 8251?
What is frame error in 8251?
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Unit 1: -
What are the building blocks of any microprocessor? (CPU, ALU, Reg, T & C)
Give the evolution of microprocessor. History of M.P) (First, Sec, Third, Fourth
generation)
Explain the timing diagram of LXI H, 2000 H.
Draw & explain the pin configuration of 8085 M.P.
Draw & explain the architecture/Block diagram of 8085 M.P.
What is status flag? How it is important in 8085 M.P. Give its detail also. (PSW. Program
status word)
What is the role of PC & SP in 8085 M.P.
What is multiplexing? How it takes place in 8085 M.P. (AD0-AD7, ALE)
What are the status code of 8085. (S1, S0)
How the DMA data transfer takes place in 8085 M. P using HOLD & HLDA.
What are the addressing modes of 8085. Explain it?
What are the instruction set of 8085. Explain it?
What are the instruction types of 8085. Explain it?
How Instruction, Execution, Fetch cycle are related. Explain?
Also give how to calculate the execution time of an instruction w.r.t its T State.
Give the brief detail of Intel Microprocessors.
Explain the difference between Intel Microprocessors & Intel Microcontrollers.
Write a short note on Hardware, Software & Firmware w.r.t any microprocessor.
Explain the schematic connection of memory and I/O to any microprocessor.
What are the differences between Neumann architecture & Harvard architecture.
What are the differences between RISC architecture & CISC architecture.
Write a short notes on registers (8 bit & 16 bit) of 8085 microprocessor.
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UNIT I Continue.
How does HLDA & HOLD works with 8085 M.P. Also explain the status signal of 8085.
What is the difference between CALL & J UMP instruction.
What is the difference between IN F0 H & IN 00F0 H instruction.
What is instruction types of 8085 M.P.
Write a short notes on instruction cycle. Also calculate the time to execute the instruction MOV
A, B. If crystal value is 10 MHz.
Explain the timing diagram of LXI H, 2000 H If data at 2000 H is AA H
Explain the difference between instructions, SHLD 2000 H & STAX H.
Explain the difference between instructions, STC & CMC.
Explain the difference between instructions, PCHL & RST 0.
Explain the difference between instructions, RIM & SIM.
WAP to perform multi byte decimal addition of a series 9D5F12EF H & 0D98ECA3 &
9856CFA6.
What is multiplexing? How it takes place in 8085 M.P.
WAP for 8 bit subtraction to consider positive as well as negative result in 8085.
WAP to unpack the BCD digit and save them in D & E Register.
WAP to generate the delay of 1ms using 8085 M.P.
WAP to glow & off the LED connected at port address F0 H after some delay.
WAP to calculate the sum of series (10 numbers) of even numbers.
What is op code format for 8085 microprocessor for different 8 bit & 16 bit register.
Interface a 8Kx8 EEPROM memory to 8085 M.P, if 2Kx8 memory is given.
Explain the importance of decode while designing of any memory.
What is programmed I/O & interrupt I/O data transfer technique in 8085 microprocessor.
What is memory mapped I/O & I/O mapped I/O data transfer technique in 8085 microprocessor.
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Unit 2: -
Give the difference between short jump, near jump & far jump.
Draw the schematic & explain how the 8086 is interfaced in Minimum mode.
Draw the schematic & explain how the 8086 is interfaced in Maximum mode.
Give the difference between 8086 & 8088 microprocessor.
How the memory is arranged in 8086 microprocessor? What is Physical address? How it
is calculated from offset?
Explain the main features of 8086 over 8085 M.P
Explain the pin description of 8086 in minimum mode of operation.
Explain the pin description of 8086 in maximum mode of operation.
Explain different status signal & their state in 8086 M.P
Explain the status flag of 8086
What is the difference between STD & CLD instruction.
STD = higher memory address to lower memory address
CLD = lower memory address to higher memory address
What is the use of LOCK in 8086 M.P
What are the addressing modes of 8086 M.P
What are the instruction sets of 8086 M.P
Give the difference between rotate & shift instruction (Put 0 in the LSB)
Explain the string instruction (MOVS/MOVSB/MOVSW)
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Unit 2 Continue.
Explain the main features of 8086 M.P as compare to 8085 M.P.
What is the importance of segment register in 8086 M.P. How they are related with their
offset.
Explain the importance of even & odd addressing of memory in 8086 M.P.
Give the difference between short jump, near jump & far jump
Which is faster- Reading word size data whose starting address is at even or at odd
address of memory in 8086? Why?
What is segment override prefix? Also explain whether macro reduces memory
requirements?
Explain the pin description & schematic for 8086 in maximum mode.
Find the physical address of first and last location of as segment. Segment base is 1000H.
Write a short notes for index & pointer register of 8086 microprocessor.
Explain the importance of STD & CLD instruction w.r.t direction flag in PSW.
Explain the importance of LOCK instruction.
Explain the difference between MOV [BX+SI], 38 H & MOV [BX], 38 H
Explain the difference between RET & IRET instruction.
Explain the difference between LOOP & MOV SW instruction.
WAP to move 10 words from location 10200 H to 10300 H using rep instruction.
Write a short notes following assembler directives. (Assume, DW, DT, ENDP, ENDM,
EQU, ORG)
Explain the main features of 80186 w.r.t 8086 M.P
Explain the main features of 80286 w.r.t 8086 M.P
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Unit 3: -
How does the keyboard matrix & LED Matrix works.
Explain the condition why & where DMA can be used.
Explain the pin/block diagram of 8257.
Explain the DMA request & DMA acknowledgement lines.
What are the differences between 8257 & 8237.
Explain the count set register of 8257.
Explain the mode set register of 8257.
Explain the status register of 8257.
Explain the pin/block configuration of 8259 PIC.
What are the IRR, ISR & IMR in 8259.
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Unit 4: -
What are the features of 0808/0809 ADC.
Explain the working & pin/block diagram of ADC 0808 w.r.t Vref.
Explain the working & pin/block diagram of ADC 0800 w.r.t Vref.
Give the typical circuit for interfacing of 0808 ADC with 8085 M.P.
Give the typical circuit for interfacing of 0800 DAC with 8085 M.P.
What is data acquisition system? How we acquire it.
What is clock? Why it is important for any ADC. What are the ranges of frequency in 0808
& 0809 ADC. (10 KHz to 1280 KHz)
What is the difference between differential input & single ended input of ADC.
What is the difference between free running & controlled mode interfacing.
Give the difference between unipolar & bipolar conversion. (-5 FF to +5 00)
Give some example & differences of serial & parallel ADC.
What is the output of a DAC. (I or V)
Give the expression of current for any DAC.
Iout = Iref (1/2 B7+1/4 B6.1/256 B0))
Explain the importance of OPAMP and DAC 0800.
What is R/2R ladder? Give its importance in ADC & DAC.
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Unit 5: -
What are the differences between Pentium & Power PC processor?
What is the protection in 80386 & 80486? How many bank of memory & segment are
there in 80386 & 80486?
How the Reset of 8051 works? What is watchdog timer in Micro controller?
How the RAM of 8051 M.C is arranged in different banks & general-purpose
storage.
How the RAM of 8051 M.C is arranged in different banks & general-purpose storage.
Explain the difference between instruction set & addressing modes of 8051. Explain
any one of them?
What is the importance of ports in any micro controller. Which port is used for special
purpose function in 8051 micro controller.
Explain the architecture of 8051 micro controller in detail?
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Pre Fetching: -
Time required to execute a given instruction can be used to fetch the next
instruction.
Interrupt Handler/Interrupt Service Routine: -
These are small program located at special location in memory. When an interrupt
is called, the program control is jumped to that specify location.
*. Some micro controller also have the ring oscillator built in, which allow to run
without any external component other then power supply.
*. 8051 compatible micro controller require 4 clock cycle per instruction cycle with
some instruction taking a different number of instruction cycle.
*. 8051 micro controller is a combination of both RISC & CISC processor.
*. 8051 micro controller is Harvard based with external memory capability.
*. Volatile memory lose the content when power is taken away.
*. Non Volatile memory does not lose the content when power is taken away.
8259 Programmable Interrupt Controller
Features:
8 levels of interrupts. Can be cascaded in master-slave configuration to handle 64 levels
of interrupts.
Internal priority resolver. Fixed priority mode and rotating priority mode. Individually
maskable interrupts.
Modes and masks can be changed dynamically. Accepts IRQ, determines priority,
checks whether incoming priority > current level being serviced, issues interrupt signal.
In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector
number.
Polled and vectored mode. Starting address of ISR or vector number is programmable.
No clock required.
D0-D7:- Bi-directional, tristated, buffered data lines. Connected to data bus directly or
through buffers
RD-bar:- Active low read control
WR-bar:- Active low write control
A0: - Address input line, used to select control register
CS-bar: - Active low chip select
CAS0: - 2Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on
these lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may
be regarded as slave-select.
INT: - Interrupt line, connected to INTR of microprocess or INTA-barInterrupt ack,
received active low from microprocessor
IR0-7: - Asynchronous IRQ input lines, generated by peripherals.
The 8259 Programmable Interrupt Controller
Introduction
Most personal computers (PCs) contain an 8259A programmable interrupt controller (PIC)
to manage interrupt signals received from devices. A single 8259A PIC can handle 8
separate interrupts and multiple PICs can be cascaded to handle up to 64 interrupts.
Today, most PCs contain two interrupt controllers, with the secondary controller chained
(cascaded) unto the first controller (on most PCs, the secondary controller is chained to
the second interrupt line of the primary controller) making it unavailable to other devices.
Communicating with the 8259A
Communication with the 8259A is facilitated by sending various commands over the bus
to the two I/O ports (port A and port B) of the controller. Port A and B of the primary
controller is located at I/O addresses 20H and 21H respectively. Port A and B of the
secondary controller can be accessed at I/O addresses A0H and A1H.
Initializing the 8259A
The 8259A PIC is initialized by sending a sequence of initialization control words (ICWs)
to the controller. ICW-1 must be sent to port A while ICW-2, ICW-3 and ICW-4 are sent to
port B. Systems containing more than one PIC must send ICWs to both the primary
and secondary controllers.
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8257 (Direct Memory Access)
8257 is a 40-pin DIP IC package. Normally data is transferred from
CPU to I/O devices through microprocessor controlled technique.
But if there is a large amount of data or the speed of I/O device are
more then the speed of processor then we used DMA. A DMA
controller temporarily borrow the address, data, control buses
from microprocessor and transfer the data to & from the CPU. 8257
is having 4 channel and so it can be used to provide DMA to four
I/O devices.
Main features: -
Maximum clock frequency to 8257 is 5 MHz.
When READY input is tied to low, the 8257 enter to a wait state. This is
used to get extra time in DMA machine cycle to transfer data between slow
memory & I/O devices.
HRQ: - It is the hold request signal send by 8257 to the processor HOLD
pin.
HLDA: - It is a hold acknowledge signal to be send by the processor to
inform the acceptance of the HOLD signal.
DACK3 to DACK0: - These are active low output signal from 8257 to
the I/O devices to inform the acceptance of DMA request.
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Programmable Keyboard/Display Interface - 8279
8279 (Keyboard & display Interface)
The 8279 is a 40 pin DIP IC package. Having two internal addresses decided by the
logic level A0. If A0 is low then the processor can read or write the data to data
register of 8279. If A0 is high then processor can write to control register or read
from status register.
It can work in either memory mapped or I/O mapped method. The two operating mode
of keyboard section are 2-Key lockout and N Key rollover. 2 key lockout means if
two keys are pressed simultaneously only the first key is recognized. In N key
rollover simultaneously key are recognized and their codes are stored in FIFO.
A0 RD WR Operation
0 1 0 Data from CPU to 8279
0 0 1 Data to CPU from 8279
1 1 0 Command word from CPU to 8279
1 0 1 Status word to CPU from 8279
BD: Output that blanks the displays. CLK: Used internally for timing. Max is 3 MHz.
CN/ST: Control/strobe, connected to the control key on the keyboard.
CS: Chip select that enables programming, reading the keyboard, etc.
DB7-DB0: Consists of bidirectional pins that connect to data bus on micro.
IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.
OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant
nibble of display.
RESET: Connects to system RESET.
SL3-SL0: Scan line outputs scan both the keyboard and displays.
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Microprocessor Basic Programming

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Microprocessor Basic Programming

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Unit I

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