Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University
ECEN620: Network Theory
Broadband Circuit Design
Fall 2013
Lecture 1: Introduction
Why Broadband Circuits?
Broadband circuits are used in many wireline and
wireless communication systems
Trends in processor design and the growing
demand for digital connectivity are pushing data
rates and bandwidth requirements in these
systems
In this class, we will study key clocking, amplifier,
and logic circuits that enable these
communication systems to scale in performance
2
Class Topics
Broadband circuit design methodologies
Clocking circuits
Phase-Locked Loops (PLLs)
Clock-and-Data Recovery systems (CDRs)
Broadband amplifiers
Transimpedance, limiting, and variable-gain amplifers
High-Speed Logic
Design techniques for high-speed CMOS and CML logic
3
Analog Circuit Sequence
326
Pre/Co-Requisite
4
Administrative
Instructor:
Sam Palermo
315E WERC Bldg., 845-4114, spalermo@ece.tamu.edu
Office hours: MW 2:00pm-3:30pm
Lectures: MWF 10:20am-11:10am, ZACH 223A
Class web page
http://www.ece.tamu.edu/~spalermo/ecen620.html
5
Class Material
Textbook: Class Notes and Technical Papers
Key References
Phaselock Techniques, F. Gardner, J ohn Wiley & Sons, 2005.
Design of Integrated Circuits for Optical Communications, B.
Razavi, McGraw-Hill, 2003.
Phase-Locked Loops: Design, Simulation, & Applications, R. Best,
McGraw-Hill, 1997.
Broadband Circuits for Optical Fiber Communication, E. Sackinger,
Wiley, 2005.
Design of Analog CMOS Integrated Circuits, B. Razavi, McGraw-
Hill, 2001.
Class notes
Will hand out hard copies in class
6
Grading
Exams (60%)
Three midterm exams (20% each)
Homework (20%)
Collaboration is allowed, but independent simulations and write-ups
Need to setup CADENCE simulation environment
No late homework will be graded
Final Project (20%)
Groups of 1-2 students
Report and PowerPoint presentation required
7
Prerequisites
Circuits
ECEN474 or approval of instructor
Basic knowledge of CMOS gates, flops, etc
Circuit simulation experience (HSPICE, Spectre)
Systems
Basic knowledge of s- and z-transforms
MATLAB experience
8
Simulation Tools
Matlab
Cadence
90nm CMOS device models
Can use other technology models if they are a
130nm or more advanced CMOS node
Other tools, schematic, layout, etc are
optional
9
Preliminary Schedule
Dates may change with reasonable notice
10
High-Speed Electrical Link System
TX
Channel
TX
data
S
e
r
i
a
l
i
z
e
r
PLL
ref clk
RX
D
e
s
e
r
i
a
l
i
z
e
r
RX
data
TX clk RX clk
D[n+1] D[n] D[n+2] D[n+3] TX data
TX clk
RX clk
CDR
11
PLL Performance TxPLL RxPLL
Min freq (GHz) 8.98 8.96
Max freq (GHz) 13.54 13.47
Mean freq (GHz) 11.26 11.22
Lock range (GHz) 4.56 4.52
+/-20.2% +/-20.1%
Fine tune hold range 5.8% 5.8%
Quarter rate clock phase noise
@ 10MHz offset (dBc/Hz)
-117.8 -117.7
J itter, 1MHz-100MHz (ps rms) 1.5 1.4
J itter, fc/1667-100MHz (ps rms) 0.64 0.64

-20
-15
-10
-5
0
5
0.1 1 10
Frequency (MHz)
G
a
i
n

(
d
B
)
(2MHz,-3dB)
Measured Jitter Transfer Function
10GHz PLL Example
100mW Power consumption
(with clock distribution)
[Meghelli (IBM) ISSCC 2006]
12
High-Speed Logic Example:
Divide-by-2 with CML FF
High-speed logic blocks are required in numerous high-
speed circuits, such as PLLs, CDRs, and equalizers
Relative to CMOS logic, current-mode logic (CML) circuits
can achieve higher bandwidth due to lower self-loading
Additional bandwidth extension can be achieved with the
addition of passives (inductors) and feedback
[Razavi]
13
Detailed Serial-Link Receiver Architecture
Key Features:
- Half-rate design
- 5-tap continuously adaptive DFE
- Variable gain amplifier
- Digital CDR
- ESD protection (HBM & CDM)
- 130mW (with DFE and CDR logic)
T-Coil Compensation
Network
50
In_P
In_N
(
1
0
G
b
/
s
)
ESD
VGA
Vcm
PI PI
Phase rotator
2:8
DMUX
8:16
DMUX
CDR
logic
I-Clock control
Q-Clock control
I
Q
DFE
logic
Tap weights
C2-I C2-Q
Edge
Data
Amp
From on-chip PLL (5GHz)
CML
CMOS logic V
DDA
=1.2V
8
2
D
0
D
1
D
2
D
3
2
2
2
(
2
.
5
G
b
/
s
)
1
1
1
1
V
DDIO
=1V
DFE
Block
Phase
detector
V
DD
=1.0V
Data
Amp
Edge
Clock
[Meghelli (IBM) ISSCC 2006]
14
CDR Loop
Data
Z
-1
Z
-1
DMUX XORs
D
E
D
E
Early
Late
Digital
Filter
I Rotator
Control
Q Rotator
Control
PI D/A
PI D/A
C2-I
C2-Q
F
r
o
m

o
n
-
c
h
i
p

P
L
L
Data Clock
Edge Clock
Key Features:
- Fully digital loop
- Can handle up to +/- 4000ppm
frequency offset
- Independent I,Q control
Jitter Tolerance
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09
Modul ati on Frequency
S
i
n
e

J
i
t
t
e
r

(
U
I

p
p
)
Receiver J itter tolerance curve ( BER<1e-9)
Tracking bandwidth ~9MHz
[Meghelli (IBM) ISSCC 2006]
15
Variable-Gain Amplifier (VGA) Example
Key Features:
Dual Diff Amps
Half/Full Amplitude
Switched R Degen
7 Bit Thermometer
Multi-bit Slewrate
Glitchless Operation
Continuous Adjustment
Optimized with GA
[Sorna (IBM) ISSCC 2005]
Optical Receiver Front-End
[Razavi]
Transimpedance amplifiers (TIAs) convert an input
current signal into an output voltage with a
transimpedance gain
Limiting amplifier amplifies the TIA output to a
reliable level to achieve a given BER with a certain
decision element (comparator)
17
Next Time
Linear circuit analysis review
18