EE520 ASIC Design PDF

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2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

ECE 520 Class Notes
1. Introduction to ASIC Design
Dr. Paul D. Franzon
Outline
1. The wonderful world of Silicon
2. Application Specific Integrated Circuits (ASICs)
Typical applications, types, decision making
3. ASIC Design Flow
4. Trends
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ECE 520 Class Notes
Module Objectives and Motivation
Objectives:
Understand Moores Law and its impact on the semiconductor industry.
Identify the defining attributes of full custom, standard cell and gate ASICs
from a design and fabrication cost perspective.
Identify the key steps in designing an ASIC
Identify the challenges facing the semiconductor industry
Reasons for module:
Relate to global context of the course, alternative technologies, and
underlying trends
Put this class in context of entire design flow
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ECE 520 Class Notes
References
Ciletti:
Ch. 1. (Design and CAD flow)
Section 8.9.1 (FPGA market)
S&F:
None for this section
Other:
EE Times www.eetimes.com
Electronic Design www.electronicdesign.com
Electronic Products www2.electronicproducts.com
Deep Chip www.deepchip.com
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ECE 520 Class Notes
Employment Trends
US Employment Growth
US employment growth in chip design is still strong, esp. system on chip
integration, verification
Skill set largely in design, verification and test side, not layout and backend
Source: EDN Global Survey
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ECE 520 Class Notes
Systems Perspective
Roughly 15% of engineers are systems engineers
Likely to grow (in US)
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ECE 520 Class Notes
System On a Chip (SOC)
ITRS 2009
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ECE 520 Class Notes
Mobile System On a Chip (SOC)
nVidea
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ECE 520 Class Notes
The Wonderful World of Silicon
Moores Law
About every eighteen months, the number
of transistors on a CMOS silicon chip
doubles and the clock speed doubles
Transistors/Chip increasing by 50% per year
(by 4 in 3.5 years)
Gate Delay decreasing by 13% per year (by
in 5 years)
This rate of improvement will continue
until about 2020 at least.
but
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ECE 520 Class Notes
Technology Drivers
Decreasing lithographic feature size, e.g. measured by the
transistor gate length:
90 nm, 65 nm, 45 nm, 28 nm, 22 nm, 14 nm, 5 nm(?)
Increasing wafer size:
8 inch diameter.. 12 in, 18 in?
Increasing number of metal
interconnect layers:
6 .. 8 9 .
Source: Intel
c/- Intel
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ECE 520 Class Notes
Cost Scaling
Cost per transistor scales down:
Approximately constant cost per wafer to manufacture (in
volume):
About $1,000 - $2,000 per wafer
Increasing IC yields for large (> 1 sq. cm.chips): 60% . 90%
But cost to first chip scales up!
Design cost increases with transistor count
Mask cost increases with each new family
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ECE 520 Class Notes
Semiconductor Roadmap
ITRS 2009
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ECE 520 Class Notes
ITRS 2009
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ECE 520 Class Notes
ITRS 2009
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ECE 520 Class Notes
Other Scaling Trends
The impact of the wiring increases with each generation
Source: Sakurai, IEEE
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ECE 520 Class Notes
ASICs vs. What?
Application Specific Integrated Circuit
A chip designed to perform a particular operation as opposed
to General Purpose integrated circuits
An ASIC is generally NOT software programmable to perform
a wide variety of different tasks
An ASIC will often have an embedded CPU to manage
suitable tasks
An ASIC may be implemented as an FPGA (see later)
Sometimes considered a separate category
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ECE 520 Class Notes
ASICs vs. What? (contd)
General Purpose Integrated Circuits:
Examples:
Programmable microprocessors (e.g. Intel Pentium Series,
Motorola HC-11)
Used in PCs to washing machines
Programmable Digital Signal Processors (e.g. TI TMS 320
Series)
Used in many multimedia, sensor processing and
communications applications
Memory (dRAM, SRAM, etc.)
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ECE 520 Class Notes
Examples of ASICs
Video processor to decode or encode MPEG-2
digital TV signals
Graphics processor
Low power dedicated DSP/controller /
convergence device for mobile phones
Encryption processor for security
Many examples of graphics chips
Network processor for managing packets,
traffic flow, etc.
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ECE 520 Class Notes
ASIC Styles
Full Custom ASICs
Every transistor is designed and drawn by
hand
Typically only way to design analog portions of
ASICs
Gives the highest performance but the longest
design time
Full set of masks required for fabrication
Source: NCSU.
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ECE 520 Class Notes
ASIC Styles (contd)
Standard-Cell-Based ASICs
or Cell Based IC (CBIC) or semi-custom
Standard Cells are custom designed and then inserted
into a library
These cells are then used in the design by being placed
in rows and wired together using place and route
CAD tools
Some standard cells, such as RAM and ROM cells, and
some datapath cells (e.g. a multiplier) are tiled
together to create macrocells
D-flip-flop:
NOR gate:
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ECE 520 Class Notes
Standard Cell ASICs (contd)
Sample ASIC floorplan:
Standard Cell designs are usually synthesized from an
RTL (Register Transfer Language) description of the
design
Full set of masks (22+) still required
Standard Cell rows
Datapath
RAM
ROM
CPU
core
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ECE 520 Class Notes
Chip Fabrication
Chip is made by successive imaging
and processing of a silicon wafer
through a set of masks
Layout
c/- NASA
2 8 inch wafers
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ECE 520 Class Notes
Fabless semiconductor company model
Company does design only. Fab performed by another
company (e.g. TSMC, UMC, Global Semiconductor,
IBM).
Back-end (place and route, etc.) might be performed at
that company or with their assistance
Cell based ASICs (contd)
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ECE 520 Class Notes
ASIC Styles (contd)
Gate-Array Based ASICs
In a gate array, the transistors level masks are
fully defined and the designer can not change
them
The design instead programs the wiring and vias
to implement the desired function
Gate array designs are slower than cell-based
designs but the implementation time is faster as
less time must be spent in the factory
RTL-based methods and synthesis, together with
other CAD tools, are often used for gate arrays.
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ECE 520 Class Notes
Gate Array (contd)
Examples:
Chip Express
Wafers built with sea of macros + 4 metal
layers
2 metal layers customized for application
Only 4 masks!
Triad Semiconductor
Analog and Digital Macros
1 metal layer for customization (2 week
turnaround)
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ECE 520 Class Notes
ASIC Styles (contd)
Programmable Logic Devices (PLDs and FPGAs)
FPGA= Field Programmable Gate Array
Are off-the-shelf ICs that can be programmed by the user to capture
the logic
There are no custom mask layers so final design implementation is a
few hours instead of a few weeks
Simple PLDs are used for simple functions.
FPGAs are increasingly displacing standard cell designs.
Capable of capturing 100,000+ designed gates
High power consumption
High per-unit cost
FPGAs are also slow (< 100 MHz)
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ECE 520 Class Notes
FPGA (contd)
Sample internal architecture:
Store logic in look-up table (RAM)
Programmable interconnect
Source: XILINX Application notes
Programmable Interconnect Array:
Configurable Logic Block (CLB):
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ECE 520 Class Notes
Standard Cell ASIC Gate Array FPGA
Positives
Highest performance: ~1
Billion transistors at multi-
GHz rates. Often only way
to meet a spec.
Lowest high volume cost
($ per die)
Fairly Low
design, CAD and
up-front costs
Time from design
ready to first part 1-
2 weeks
Lowest mid-
volume price
Low design, CAD
and up-front costs
Time from design
ready to first part
almost zero
Negatives
High design, CAD and
wafer costs
Long time to first-product
to market (long design time
+ >4 weeks for fab)
Performance not
much more than
FPGA
Low performance
(Millions of
implemented logic
gates @ 10s to 100s
of MHz)
High unit cost
($1,000s)
Comments Often used for
FPGA shrink
Especially useful
in markets that
change fast or have
low volumes
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ECE 520 Class Notes
Example
Total cost calculation:
Source: AMI
(
A
v
e
r
a
g
e

S
e
l
l
i
n
g

P
r
i
c
e
)
NRE = Non Recurring Enginnering (cost)
(cost of design, masks, etc.)
ASP=
Average
Selling
Price
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ECE 520 Class Notes
Comments
Market currently dominated by standard cell ASICs and FPGAs
Ideally standard cell designs would be used for higher volume applications
that justify the NRE
Many consider FPGAs separate from ASICs
Why?
Different level of design skills required, especially in back end (place and
route or physical design)
Reduced level of verification required before sending to factory
Again reduces sophistication required of team
Low-cost (barrier) of entry to FPGAs
Often different, lower cost Design Automation (CAD) tools
Lower performance of FPGAs
However, front-end design (RTL coding) is virtually identical for each
implementation style
Sometimes FPGA done first and standard cell ASIC done later
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ECE 520 Class Notes
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ECE 520 Class Notes
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ECE 520 Class Notes
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ECE 520 Class Notes
ASIC Design Flow
Major Steps:
1. High Level Design
Specification Capture
Design Capture in C, C++, SystemC or SystemVerilog (etc.)
HW/SW partitioning
IP selection (choose from pre-existing designs or Intellectual Property)
2. RTL Design
Major topic of this course
3. System, Timing and Logic Verification
Is the logic working correctly?
4. Physical Design
Floorplanning, Place and Route, Clock insertion
5. Performance and Manufacturability Verification
Extraction of Physical View
Verification of timing and signal integrity
Design Rule Checking
Front end
Back end
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ECE 520 Class Notes
ASIC Design Methodology
Most ASICs are designed using a RTL/Synthesis based
methodology
Design details captured in a simulatable description of the
hardware
Captured as Register Transfer Language (RTL)
Simulations done to verify design
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ECE 520 Class Notes
Methodology (contd)
Automatic synthesis is used to turn the RTL into a gate-level
description
ie. AND and OR gates, etc.
Chip-test features are usually inserted at this point
Gate level design verified for correctness
Output of synthesis is a net-list
i.e. List of logic gates and their implied connections
NOR2 U36 ( .Y(n107), .A0(n109), .A1(\value[2] ) );
NAND2 U37 ( .Y(n109), .A0(n105), .A1(n103) );
NAND2 U38 ( .Y(n114), .A0(\value[1] ), .A1(\value[0] ) );
NOR2 U39 ( .Y(n115), .A0(\value[3] ), .A1(\value[2] ) );
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ECE 520 Class Notes
Methodology (contd)
Physical Design tools used to turn the
gate-level design into a set of chip
masks (for photolithography) or a
configuration file for downloading
to an FPGA
Floorplanning
Positioning of major functions
Placement
Gates arranged in rows
2
5
2
0

m
2524 m
Instruction
SRAM
CPU 1
CPU 2
Data Memory
Controller
Wishbone
Traffic
Cop SRAMAddress Pins
Power
Stripe
Power
Rings
CPU 2
CPU 1
Wishbone
Traffic Cop
Data Memory
Controller
Instruction
SRAM
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ECE 520 Class Notes
Methodology (contd)
Clock and buffer Insertion
Distribute clocks to cells and locate buffers for use as
amplifiers in long wires
Routing
Logic Cells wired together
(Figures c/- Schoenfloss, Davis, Rao)
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ECE 520 Class Notes
Methodology (contd)
Subflow example:
Timing Closure:
Front end of design process
= Design capture, simulation and
synthesis
Assumes abstract information about
impact of wires
Back end of design process
Place and route
Requires accurate wiring models
Start
Load, link, and
constrain design in
Primetime
Verilog structural
description of
design (post clock
tree synthesis)
Post-route SPEF
file from SoC
Encoutner
Back-annotate
wiring parasitics in
Primetime
Report timing in
Primetime
Finish
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ECE 520 Class Notes
Future Issues
Increased cost of custom fab
Cost to first chip rising ~60% with every generation
Design Cost + Cost of making masks ($4M+)
Solutions:
Increased use of shared fabrication facilities
Increased number of fabless semiconductor companies
Increased cost of design
Must be addressing > $1B market to justify a new chip run
Globalization
Time-to-market and other competitive issues
Increased complexity of design
Impact of interconnect increasing
Increasing process variations leading to timing variation
Decreased reliability
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ECE 520 Class Notes
Future Issues (contd)
Trends
Increased use of FPGA and Gate Arrays
Increased use of platform solutions
Multi-core embedded CPU + ASIC accelerators
Configurable systems
Existing designs (IP or Intellectual Property)
Increased use of SystemVerilog, SystemC and other
system modeling tools
Complexity shifting from design to logical and
performance verification
Logical verification = function; Performance = speed
Cost to first silicon getting so high that the total
addressable market must be very large and product risk
low
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ECE 520 Class Notes
Design Cost
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ECE 520 Class Notes
FPGA (volume; update cycle)
Summary Questions
What is the impact of Moores Law on the Semiconductor Industry?
ASIC, FGPA or Gate Array?
Processor to process HD video information for new Camcorder line.
Network security processor that requires constant updates.
Specialized Controller for seismic survey equipment
Exponential growth in capability constant innovation and new product capabilities
Standard Cell ASIC (performance requirement; volume)
FPGA (volume), followed possibly by Gate Array shrink
Standard Cell (performance, power, volume)
FGPA (volume, updates)
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ECE 520 Class Notes
Summary Questions
Is logic design, RTL coding and verification front end or back end
design in the CAD flow?
Is place and route front end or back end design in the CAD flow?
What is the impact of Moores law on product development costs (design
and first lot)?
Front End
Back End
Smaller technology node Greater design complexity, CAD costs
and wafer costs

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2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

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