V.

Vishnu Ganesh
2113049

Microprocessor and Microcontroller

Assignment II
ARM Architecture

Introduction

ARM, is the acronym for Advanced RISC Machines. Where RISC means Reduced
Instruction Set Computer. ARM microprocessors have a optimized set of instruction set that
reduces instruction execution cycles. ARM processors are low power consuming devices,
thus used in a variety of applications such as mobile phones, PDAs, digital media players,
calculators etc. ARM architecture was developed and is owned by ARM Holdings and is
licensed for use by several companies such as Apple, Intel, Texas Instruments, Yamaha.
ARM Holdings develop architecture cores while these companies develop microcontrollers
for their field of application. ARM architecture is the most widely used 32 bit RISC
architecture in mobile devices and embedded systems.
RISC
Reduced Instruction Set Computer architecture unlike Complex Instruction Set
Computer (CISC) has a less number of instructions, with the objective of having a single
cycle execution time for each instruction. Data processing on memory is done through
registers by load/store instructions.
ARM Architecture
The ARM architecture is also similar to the RISC architecture as it has these typical
RISC architecture features.

A uniform register file load/store architecture, where data processing operates only
on register contents, not directly on memory contents.

Simple addressing modes, with all load/store addresses determined from register
contents and instruction fields only.

Enhancements to a basic RISC architecture enable ARM processors to achieve a good

balance of high performance, small code size, low power consumption and small silicon area.

ARM7TMDI processor
The ARM7TMDI core is a moember of the ARM family of general-purpose 32-bit
microprocessors.

The Instruction Pipeline

The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions
to the processor. This allows several operations to take place simultaneously, and the
processing and memory systmes to operate simultaneously.
A three stage pipeline is used, so instructions are executed in three stages:
1. Fetch
2. Decode
3. Execute
During normal operation, while one instruction is being executed, its successor is being
decoded and a third instruction is being fetched from memory. The program counter points to
the instruction being fetched rather than to the instruction being executed. This is important
because it means that the Program Counter value used in an executing instruction is always
two instructions ahead of the address.

Memory access

The ARM7TDMI core has Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Only load, store and swap instructions can access data
from memory. Data can be 8bit, 16bit or 32bit.

Instruction Sets
The AMR7TDMI processor has two instruction sets:

The 32-bit ARM instruction set

The 16-bit Thumb instruction set

The thumb instruction set is a subset of the most commonly used 32-bit ARM instructions.
Thumb instructions are each 16 bits long, and have a corresponding 32bit AMR instruction
that has the same effect on the processor model. On execution, 16bit thumb instructions are
transparently decompressed to full 32bit ARM instructions in real time, without performance
loss. Thumb offers a long branch range, powerful arithmetic operations and a large address
space.

References
1.ARM Ltd.
http://www.arm.com/products/processors/instruction-set-architectures/index.php
2.Atmel
http://www.atmel.in/Images/DDI0029G_7TDMI_R3_trm.pdf

ARM7TDMI Architecture