Assignment

VLSI
Name:
Hina imtiaz(1526)
Submitted to:
Mam fareeha
Date:
3-10-2014

Solution to the questions:

Total questions=15

Q no 1:
Write down 4 different parameters to b taken care of while designing a circuit in VLSI?
Solution::
The important parameters to b taken care of while designing a circuit in VLSI are:

power consumptio
cost
robustness
functionality
size

Q no 2:
Write down 2 isssues in modern digital circuit design?
Solution:

low amplification
complex design

Q no 3:
Define moores law?
Solution:
'Moore's Law' states that the number of transistors per square inch on integrated circuits had doubled
every year since their invention.

Moore's law predicts that this trend will continue into the foreseeable future.
Q no 4:
Write down designs level of abstraction in digital circuits?
Solution:
There are five Levels of abstraction :

system
module
gate
circuit
device

Q no 5:
Draw and label CMOS transistor?
Answer:

Q no 6:
How PN junction works? Draw physical diagram and graphs?
Solution:
A p-n junction consists of two semiconductor regions with opposite doping type as shown in Figure. The
region on the left is p-type with an acceptor density Na, while the region on the right is n-type with a
donor density Nd. The dopants are assumed to be shallow, so that the electron (hole) density in the n-type
(p-type) region is approximately equal to the donor (acceptor) density.

The junction is biased with a voltage Va as shown. Free electrons on the n-side and free holes on the p-side can
initially wander across the junction. When a free electron meets a free hole it can 'drop into it'. So far as charge
movements are concerned this means the hole and electron cancel each other and vanish. As a result, the free
electrons and holes near the junction tend to eat each other, producing a region depleted of any moving charges. This
creates what is called the depletion zone.
Graphically it is defined as:

Q no 7:
Draw complete diode model showing all parameters?
Solution:
Model of diode :

The simple DC equation you know is the well known Shockley equation, that is:
Id= Is{(expV/Vt)-1}
Where IS is the diodes reverse saturation current, Vis the applied voltage bias, Vt is the thermal voltage
(equal to kT/q which is about 25mV at room temperature) and ID is the current through the device.

More factors in pn junction:

Junction capacitance: All PN junction diodes exhibit a junction capacitance. The depletion region is the
dielectric spacing between the two plates which are effectively formed at the edge of the depletion region
and the area with majority carriers. The actual value of capacitance being dependent upon the reverse
voltage which causes the depletion region to change (increasing reverse voltage increases the size of the
depletion region and hence decreases the capacitance)
Forward voltage drop (Vf): Any electronics device passing current will develop a resulting voltage
across it and this diode characteristic is of great importance, especially for power rectification where
power losses will be higher for a high forward voltage drop.
Leakage current: If a perfect diode were available, then no current would flow when it was reverse
biased. It is found that for a real PN junction diode, a very small amount of current flow in the reverse
direction as a result of the minority carriers in the semiconductor
Q no 8:
What are the symbols of nMOS and pMOS transistors?
Solution:

Q no 9:
What is physical significance of Vt in MOSFETs?
Solution:
Vt is the thereshold voltage, below this voltage gate is not formed. In order to turn on the gate we must
give voltage obove the thereshold voltage
Q no 10:
Explain saturation region of transistor:
Solution:
Saturation Region:

Emitter-Base junction is forward biased

Collector- base junction is forward biased

. The transistor is operated in this mode, when it is used as a closed switch.

Q no 11:
What is ment by latchup? Describe it with layout and diagram?
Solution:
A latchup is a type of short circuit which can occur in an improperly designed integrated circuit (IC).
More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of
a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly
even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.

Q no 12:
What are different types of parasitic capacitances in transistor?
Answer:
Parasitic capacitances in transistor are:

Gate capacitance
Gate overlap capacitance
Source/drain overlap capacitance

Q no13:
what is difference between via and tub-tie?
Answer:
via is define as a cut.
The connection of p-tub to vss & connection of n-tub to vdd is done through wire.This connection is
called tub-tie.

Q no 14:
solution:
As we increase the voltage current passes through transistor increases so collision of electron
increases.with this increase in collisions the metal elements disturb.this is called electron migrations.
Q no 15:

What are the different fabrication errors?

solution:
Fabrication errors are:

Via is not prominent

Wires are open or short
Doping is done too wide or too narrow