EE 6303: Digital Systems Testing

(Spring 2005, Tuesday and Thursday: 5:30–6:45 p.m., CB 1.110)

1 General Information
Instructor: Mehrdad Nourani
Office & Phone: ECSN 4.924, 972-883-4391
E-mail (Webpage): nourani@utdallas.edu (http://www.utdallas.edu/˜nourani)
Office Hours: Tuesday and Thursday 3:30–4:30 p.m., or by appointment.
Required Text: Testing of Digital Systems, Niraj Jha and Sandeep Gupta,
Cambridge University Press, 2003.
Other References: Essentials of Electronic Testing, Michael Bushnell and Vishwani Agrawal,
Kluwer Academic Publishers, 2000.
Digital Systems Testing and Testable Design, M. Abramovici,
M. Breuer and A. Friedman, IEEE Press 1990.
Course Web Page: http://webct.utdallas.edu/
Teaching Assistant: To be announced.

2 Catalog Description
EE 6303 Digital Systems Testing (3 semester hours).
Fault modeling, fault simulation, testing the stuck at faults, automatic test generation, random test generation, testing
the bridging faults, functional testing, design for testability, full/partial scan, boundary scan, compression techniques,
built in self test, BIST architectures, PLA/memory testing, core testing, system-level testing.
Prerequisite: Digital design (e.g. EE 4320) and basic knowledge of computer architecture, VLSI and HDL.

3 Grading
Grading will be based on two tests and homeworks as follows:


Homeworks and Projects: 25%
Test 1: 35% (Thurs. 3/3/2005, 5:30 p.m.)
Test 2: 40% (University schedule: Thurs. 4/28/2005, 5:00 p.m.)

4 Course Policy


Homeworks will be assigned throughout the semester, and will be due approximately once every two weeks
at 5:30 p.m. at the beginning of the lecture period.


A homework is considered late if it is turned in after 5:30 p.m. of the due date. There will be 20% per day
penalty for late homeworks up to 3 days excluding weekends and holidays. Late homeworks and reports won’t
be accepted after 3 days.


Some of the homeworks are mini-projects and require C-programming or using CAD tools for implementation,
simulation and analysis. These tools are available on almost all Unix machines in ECSN building such as
Solarium Lab (ECSN 4.324) and VLSI CAD lab (ECSN 4.308). To have enough time start as early as possible.

1
 

Copying on examinations, assignments and projects is cheating and is prohibited. Any instances of cheating
or plagiarism is considered academic dishonesty and will be subject to disciplinary penalties according to the
UT Dallas policy on scholastic dishonesty. The penalties include the possibility of failure in the course and/or
dismissal from the University. Since such dishonesty harms the individual, all students and the integrity of
the University, policies on scholastic dishonesty will be strictly enforced. Please read carefully this policy in
http://www.utdallas.edu/ student/slife/dishonesty.html.


Make-up tests will not be given unless the student has obtained permission from the instructor before the
scheduled test. Permission will not be given without documentation of exceptional circumstances.


If a student has to be absent for several classes because of job related obligations, (s)he will not be eligible for
an incomplete grade. In such cases, the student is advised to withdraw the course.


Announcements and complementary materials will be posted on the course web page. However, regular
attendance and taking notes are highly recommended.

5 Syllabus & Tentative Lecture Plan

Weeks Readings Topics Coverage

Tues. Thur.
1/11 Ch 1 Introduction: course introduction; test technology evolution; cost of testing;
1/13 linking design and test.IC testing: VLSI fabrication; testing at the IC level.
1/18 Ch 1 VLSI testing process: test process; automatic test equipment;
1/20 Test economics: cost analysis; rule of ten; test data analysis; quality measure.
1/25 Ch 2 Fault modeling: failure mechanisms and characteristics; fault detection
1/27 and redundancy; fault equivalence and dominance; fault models.
2/1 Ch 3 Fault simulation techniques: serial, parallel, deductive and concurrent
2/3 fault simulations; fault sampling; statistical fault analysis.
2/8 Ch 4 Test generation for combinational circuits: boolean difference;
2/10 D-algorithm; PODEM algorithm; FAN algorithm; testing the bridging faults;
2/15 Ch 5 Test generation for sequential circuits: single clock synchronous model;
2/17 time-frame expansion method; difficulties in sequential circuit testing.
2/22 Ch 11 Design for testability: controllability and observability metrics;
2/24 ad-hoc methods; full and partial scan; variations of scan;
3/1 Ch 11 Boundary Scan: full and partial scan; boundary scan standard;
3/3 TEST 1 (Ch 1–5).
3/8 Spring Break – University Holiday
3/10
3/15 TAP Controller; test instructions BSD Language;
3/17 Ch 12 Bulit-in self-test: BIST concept; test pattern generation for BIST;
3/22 Ch 12 compression techniques; various BIST architectures; test point selection;
3/24 memory BIST; delay fault BIST;
3/29 Ch 14 Memory test: memory density and defects; fault modeling;
3/31 March algorithms; testing RAM, ROM and cache.
4/5 Ch 6 IDDQ test: target faults; testing methods; fault coverage metrics;
4/7 instrumentation problems; current limit setting;
4/12 Ch 8 Delay test: path delay testing; transition faults; at-speed testing.
4/14
4/19 Ch 16 System test and core based design: using embedded microprocessor in testing;
4/21 literature core-based design and test; SoC test architecture; test for signal integrity;
4/26
4/28 TEST 2 (Ch 6, 8, 11, 12, 14, 16; selected literature).