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EE 3320: DIGITAL CIRCUITS

Fall 2005 TR 3:30pm – 4:45pm and 5:30pm – 6:45pm ECSS 2.412, ECSN 2.112

Instructor: Poras T. Balsara TA: to be announced


(972) 883-2557, poras@utdallas.edu
Office Hrs: TR 2:00pm – 3:15pm or by appointment
Room ECSN 4.928 / 4.612
http://www.utdallas.edu/~poras/courses/ee3320/

● Course Overview
The importance of digital circuits and systems cannot be overestimated in present day and age. Digital
circuits form the basis for most of the electronic devices ranging from small electronic toys to large scale
computers. Hence it is useful to understand how these circuits are designed and operate. All digital circuits
operate using the same concepts that will be presented in this class. The only difference is in the complexity
of the circuits.
All announcements and homework assignments will be posted on the web page for this course. It is the
responsibility of each student to check this web page at least once a week for new announcements and
homeworks.
Prerequisites: EE 2310 Co-requisite: EE 3120.

● Course Material.
o Text Book:
o S. Brown and Z. Vranesic, Fundamentals of Digital Logic With Verilog
Design, McGraw-Hill Publishing, 2003. 0-07-283878-7.
o References:
o M. Morris Mano, Digital Design, Third Edition, 2002. Prentice Hall,
Upper Saddle River, NJ.
o John F. Wakerly, Digital Design Principles and Practices, Third Edition,
2001. Prentice Hall

EE 3320 1 PTB 8/22/05


● Tentative List of Topics (with Section #s from the text book)

1. Logic Gates and Implementations


a. Review: Basic logic functions (2.1-2.4)
b. Electrical properties of logic gates (CMOS) (3.3, 3.8)
2. Digital Logic Design Fundamentals
a. Review: Truth tables, Boolean algebra and algebraic proofs (2.1-2.5)
b. AND-OR, OR-AND, NAND, NOR circuits (2.6-2.8)
c. Combinational logic design using Verilog (2.10, 4.12, 6.6)
d. Karnaugh Map based minimization (SOP and POS forms) (4.1-4.5)
e. Programmable Logic Devices (3.6, 3.10, Appendix E)
3. Combinational Logic Analysis and Design
a. Functional and Timing analysis
b. Decoders and Encoders (6.2, 6.3)
c. Multiplexers and Demultiplexers (6.1)
d. ROM based logic design (6.2.1)
e. Field Programmable Gate Arrays (3.6, 3.10)
f. Tristate Logic
4. Sequential Logic Elements
a. Latches and Flip-flops (7.1-7.7, 7.10)
b. Latch and flip-flop timings (7.3)
5. Sequential Logic Analysis and Design
a. Sequential logic analysis (8.1, 8.9)
b. Sequential logic design (7.14, 8.1)
c. Sequential logic design using Verilog (7.12, 7.13, 8.4)
d. Counters and Registers (7.8-7.11, 8.7)
e. Sequential logic circuit timing (10.3)
f. State minimization and assignment (8.2, 8.6)
6. Arithmetic Circuits
a. Review: Number system (5.1)
b. Signed number representation (5.3)
c. Adders and Subractors (5.2, 5.4)
d. Combinational Shifter
e. Multipliers (5.6)
f. Floating-Point Numbers (5.7)
7. Digital Design Examples (5.5, 10.1-10.4)
8. Miscellaneous Topics
a. Metastability
b. Dynamic Hazards in digital circuits (9.6.2)
c. Testable design (11.6.1)

EE 3320 2 PTB 8/22/05

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