Ss

ECE 224 and MTE 325
Embedded Microprocessor Systems

Lecture Notes
Fall 2014
ECE224 - 001 William D. Bishop, PEng wdbishop@uwaterloo.ca
ECE224 - 002 Otman Basir, obasir@uwaterloo.ca
f2014-1.0
Copyright (c) 2014 by the University of Waterloo and William D. Bishop, PEng, Robert B. Gorbet, PEng, Carol C.W.
Hulls, PEng and Wayne M. Loucks, PEng. All Rights Reserved.
Contents
This part of the notes contains the following sections.
Course Introduction (starting on page 5) including people, marking scheme, course outline, and
an introduction to interfacing ideas.
Embedded Systems (starting on page 20) The ideas associated with embedded systems, although
not fundamental to the course content, are always present in the system examples. As a result a
small amount of time is spent introducing some of the general terms associated with embedded
systems.
Interfacing Software, Introduction to Synchronization, and Device Drivers (starting on page 33)
(the actual order of the content is different from this list). This section of the notes provides
some new and some review material to provide a common framework to discuss the material
later in the course.
Synchronization, Data Generation and Data Transfer (starting on page 50) Synchronization is
a key component of most, if not all, sections of this course. This section, in combination with
the next one, introduces synchronization requirements in a fairly general model.
Computer Structure (starting on page 80) Processor Structure. A summary of how the processor
executes an instruction and how external interfaces can detect requests by the processor.
Parallel Interfacing (starting on page 150) Examines the role of the interface to match the bus
timing and signalling characteristics with a devices timing and signalling characteristics.
-1
Error Detection and Correction (starting on page 196) Error Detection and Correction including
an introduction to error types, differences in detection and correction and one example of an
error correcting code (the Hamming code). The error environment, the general methods for
dealing with some errors (detection and/or correction), the limitations to error handling, and an
introduction to data words and code words.
Serial Interfacing (starting on page 229) Introduction to serial communication interfacing;
asynchronous communication techniques, synchronous techniques; and serial device interfacing
techniques.
Analog Interfaces (starting on page 321) Digital-to-analog interfacing, Analog-to-digital interfacing, Sample-and-hold circuitry. Includes a discussion of static and dynamic errors.
Buses - Data Transfer (starting on page 433) Examination of operation and timing requirements
for synchronous, asynchronous, partially interlocked asynchronous, semi-synchronous, and split
cycle bus systems. This section of the notes deals exclusively with the transfer of data. Issues
associated with selecting the next bus master are presented elsewhere in the notes.
Buses - Arbitration (starting on page 476) Examination of operation and characteristics of daisy
chained and non-daisy chained bus arbitration techniques.
Direct Memory Access(DMA) (starting on page 545) Examination of DMA operation (software,
hardware and bus needs), DMA characteristics.
Grounding, Shielding and Transmission Line Issues (starting on page 601) Examination of some
of the real-world considerations at the wiring level for digital circuits.
-1
Examples (Signalling and Buses) (starting on page 674) Aspects of existing systems that demonstrate some of the course concepts.
-1
UNIVERSITY OF WATERLOO
Department of Electrical and Computer Engineering
Section I:
Course Introduction
f2014-1.0
Course Introduction
Course Introduction: Section Contents

This section of the notes contains the following subsections.
ECE224/MTE325 Course Goals (starting on page 7)
Overview (starting on page 12) Brief overview of the course theme.
Section Contents: Course Introduction
I - 0.1
Course Introduction
Introduction ECE 224/MTE 325

In ECE 224 / MTE 325, you will explore the design of microprocessor systems and computer
interfaces
You will develop insight into a few of the key questions that face modern computer interface
designers:
How do you transfer data from one type of device to another?
When should data be exchanged?
How should the exchange of data be arbitrated?
What conditions must be satisfied to reliably exchange data?
How should the data be organized?
Why do different computer interfaces exist?
Under what circumstances does one interface outperform another?
What are the advantages and disadvantages of different interfacing techniques?
ECE224/MTE325 Course Goals
I-1
Course Introduction
Computer Interfacing Analogy

In many ways, computer interfacing is analogous to the challenge of designing a way to
put a square peg in a round hole
Here is an example of a simple computer interfacing problem:
How do you design the hardware / software interface necessary to connect a computer
mouse to a USB port on a computer?
By the end of this course, you have a deeper understanding of design process required to
answer questions similar to the one posed above
I-2
Course Introduction
Course Syllabus
See the course syllabus for all information regarding deliverables, timing, marking, and due dates.
A copy of the course syllabus is available
on the uwaterloo Desire2Learn site https://learn.uwaterloo.ca.
I-3
Course Introduction
10
Course Resources: Summary from Syllabus

Part
of the contract
Announcements
Calendar: Labs, tutorial topics, and due dates are placed here as appropriate
Lectures: Lecture notes (1-up, 2-up, and 4-up versions)
Lab: Lab manual, files for download, marking sheets/rubrics
Course syllabus
Course responsibilities page
Information and discussion

Discussion board for your course monitored by instructor
Lab discussion board for all lab related questions/answers (a living FAQ)
Lecture summaries (by course)
Assignments (and solutions)
Previous exams (and solutions)
Other information provided during the term
I-4
Course Introduction
11
Textbooks
There is no recommended textbook for this course:
No suitable textbook exists
Most textbooks focus on a particular microcomputer system or computer interface
instead of examining the real design issues
Online lecture notes have been provided to assist you with your understanding of the course
material
Lecture attendance is strongly encouraged
Lecture Notes and Lab Manual: The lecture notes and the lab manual are available
online through D2L. The 2-up or 4-up versions of the lecture notes are the most suitable
for annotating in class. You should bring a printout of Appendix A of the lab manual to
the Lab Tools Tutorial.
I-5
Course Introduction
12
System Views
system1.pdf
Control Computer
Open Loop vs Closed Loop
(Other courses)
System to Control
(Other Courses)
Computer system
For performing some
(control) task
If IN1 > 0x1a07 then OUT = 0x40
System to Control
When the Temp is over 80 degrees shut the damper
View A: System-Centric View
Overview
View B: Computer-Centric View
I-6
Course Introduction
13
System Components
Consider a physical system with the widest possible set of parameters.
Possible System Components
Humans: Response times milliseconds to minutes (May be referred to as human-in-theloop.)
Machines with moving parts: Response times milliseconds to multiple hours
Machines without moving parts: Response times tens of nanoseconds and up
Chemical Reactions: Response times any
Overview
I-7
Course Introduction
14
Overview of Course Material

system2a
Computer
(Processor
Input
Output
plus
Interface Memory) Interface
Output
Signal
Conditioning
Input
Signal
Conditioning
Sensor
Overview
System to
be controlled
and/or
monitored
Actuator
I-8
Course Introduction
15
Note: Sensors and Actuators
Possible Sensors Sensors are used to determine information about the physical plant.
In our case all sensors will produce an electrical signal (analog or digital).
Electrical:Electrical voltmeter
Mechanical:Electrical switches, strain gauges
Chemical:Electrical pH meters
Optical:Electrical light meter
Thermal:Electrical temperature sensor
Magnetic:Electrical speedometer
Possible Actuators Possible actuators are used to affect the physical plant.
(Actuators in the broadest sense) Again: consider electrical inputs.
Electrical:Mechanical motors, speakers, solenoids
Electrical:Chemical electrodes for electroplating
Electrical:Optical electronic displays. fibre-optic drivers
Electrical:Thermal resistive heaters, Pelletier devices
Electrical:Magnetic electro-magnets (or magnetic coils)
Overview
I - 8.1
Course Introduction
16
Interface Issues
Interface computer to the outside world
Converts signals (analog or digital) to appropriate levels and timing to permit interaction
with the processor.
Issues
Synchronization Issues
Data Flow Issues
Signal Issues
Synchronization topics occur throughout the notes, however there is a more detailed discussion
of this material (Starting on page 50 OR Generalized synchronization)
Overview
I-9
Course Introduction
17
Signal Issues
Analog (values, offset)
Digital (number of bits, meaning of the bits)
Noise
Ground reference
Current/voltage
Overview
I - 10
Course Introduction
18
Data Flow Issues

What is the information transferred?
Is it the occurrence of an event?
Is it the data and the occurrence of an associated event?
Is it just the data, not associated with any event?
Unidirectional/bidirectional data flow
Source or destination responsible for control of data flow
Signalling for the data transfer (including how long is the data valid)
Overview
I - 11
Course Introduction
19
Synchronization Issues
Relationship between/among the entities.
Active Demand Oriented (Interrupt, service required)
Passive Request Oriented (Polling)
Consider the range of possibilities:
Non-maskable interrupt
Maskable interrupt
Tight polling loop
Periodic polling loop
Blind synchronization
What are the needs of the synchronization?
Source may provide data spontaneously
Source may provide data only when stimulated by the destination
Overview
I - 12
Section II:
Embedded Systems
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Embedded Systems
21
Embedded Systems: Section Contents

Introduction (starting on page 22) Importance and characteristics of general embedded systems. Introduces the ideas and significance
of embedded systems.
Terminology (starting on page 26) Compares and contrasts terms such as: microprocessor, microcontroller, System on a Chip,
Programmable System on a chip, Programmable logic devices.
Section Contents: Embedded Systems
II - 0.1
Embedded Systems
22
Introduction to Embedded Systems

embedded system: a special-purpose computer system designed to perform a task without the
users knowledge of its existence. The user may provide input to the embedded system via
controls and sensors but the user need not be aware of the presence of the embedded system.
Some applications of embedded systems are the following:
Consumer electronics
TVs, DVRs, CD players, etc.
Household appliances
washers, dryers, microwave ovens, etc.
Automotive
ABS systems, fuel injectors, transmissions, etc.
Telecommunications
handsets, cellular phones, pagers, etc.
Introduction
II - 1
Embedded Systems
23
Introduction to Embedded Systems Evolution
1960
2000
Mechanics
Electronics
Mechanics
Electronics
and Informatics
and Informatics
Car
90%
10%
50%
50%
Calculator
100%
0%
10%
90%
Camera
100%
0%
30%
70%
From: R. Siegwart, Grasping the Interdisciplinarity of Mechatronics, IEEE Robotics and Automation Magazine Vol. 8, No. 2, June 2001, p 27-34.
Introduction
II - 2
Embedded Systems
24
Embedded System Design

Embedded systems come in all shapes and sizes
Simple embedded systems are constructed out of electronics without the need for a processor and software, however there will be state.
Complex embedded systems incorporate one or more processors with sophisticated control
software
Often, the hardware components of a complex embedded system are designed prior to the
development of any software
Hardware/software codesign is the term given to the task of simultaneously designing
hardware and software components of a combined hardware/software system
Introduction
II - 3
Embedded Systems
25
What is embedded system design?

takes engineering judgment
challenging
multidisciplinary
pervasive
complex
fun
a hard-to-acquire skill
Introduction
II - 4
Embedded Systems
26
Terminology Issues
Hardware/Software:
From the Canadian Oxford Dictionary:
Hardware: 3. the mechanical or electronic components of a computer etc.
Software: 1. the programs or other operating information used by a computer. 2. storage media
such as video cassettes, audio tapes, etc. requiring playback on electronic equipment
What is a book?
is it the object?
is it the content?
Technology means that any model shifts with time.
Into this we bring a need for some terminology.
Terminology
II - 5
Embedded Systems
27
Microprocessors vs. Microcontrollers

Consider as implementations (rather than intellectual property).
Microprocessors: A microprocessor consists of a processor only (no main memory and no I/O
devices).
This term commonly refers to a general-purpose
Central Processing Unit (CPU).
Powerful, despite the name
Despite central may include more than one processing core
Suitable for all types of computations
Require additional hardware components to support
communications and storage
Examples: Intel Pentium series, AMD, Power-PC.
Terminology
II - 6
Embedded Systems
28
Microprocessors vs. Microcontrollers Cont.

Microcontroller : A complete computer including a processor, memory and some input/output
devices. These devices are usually specified in a fairly general manner to permit reuse of the
same microcontroller component in many applications.
This term commonly refers to a Central Processing Unit (CPU) that has been specialized to
control the operation of a mechanical or electronic system.
Small and cost-effective
Built-in memory
Specialized built-in interface support for some of the following:
high-speed communication
parallel devices
serial devices
analog devices
Designed to meet the needs of a wide range of applications.
Examples: Intel 8051, Motorola 68HC11, Microchip PIC, Cypress PSOC.
Terminology
II - 7
Embedded Systems
29
System-On-a-Chip (SOC)
System-On-a-Chip(SOC): A complete fully-functional system is implemented on a single integrated circuit. This may include processing, memory, input and output interfaces as well as any
other digital logic.
Typically, a System-On-a-Chip (SOC) incorporates the following hardware components (depending on the application):
functionality similar to the microprocessor or a microcontroller defined previously. The
implementation may be as either hardware or software.
Communication port(s)
Volatile storage (e.g., Random Access Memory RAM )
Non-volatile storage (e.g., Read-Only Memory ROM )
Other components could include: timers, parallel interfaces, Analog to digital converters
and Pulse width modulators.
A System-On-a-Chip (SOC) can be used to implement an embedded system or a portion of an
embedded system.
Terminology
II - 8
Embedded Systems
30
Programmable Logic Device (PLD)

Programmable Logic Device: A digital logic IC that permits configuration and interconnection
of internal logic blocks. Often this term refers to a computer chip that can be rewired to
implement a custom digital circuit using primitive building blocks.
Several types of PLD technologies exist:
SRAM (Static Random Access Memory)
EEPROM (Electronically-Erasable Programmable
Read-Only Memory)
Anti-fuse
Primitive building blocks include: Flip-flops, Multiplexers, Lookup tables, and Logic gates.
Not all PLDs are created equally:
In-system programmability vs. external
programming hardware
One-time programmable vs. reconfigurable
Terminology
II - 9
Embedded Systems
31
(SOPC) System-On-a-Programmable-Chip
System-On-a-Programmable-Chip (SOPC): An SOC implemented using a high-density, reconfigurable PLD it is considered to be a system on a programmable chip.
Advantages (with respect to SOC):
Flexible
Upgradable
Disadvantages (with respect to SOC):
Potentially slower
More expensive in large quantities
Terminology
II - 10
Embedded Systems
32
Note: Terms used in Embedded Systems

Terms:
embedded system (page 22)

Hardware (page 26)
Software (page 26)
Microprocessors (page 27)
Microcontroller (page 28)
System-On-a-Chip(SOC) (page 29)
Programmable Logic Device (page 30)
Terminology
II - 10.1
Section III:
Interfacing Software, Introduction to Synchronization, and Device
Drivers
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34
Interfacing Software, Introduction to Synchronization, and Device Drivers
General Synchronization Introduction: Section Contents

A comparison of the abstraction layers for software development. (starting on page 35)
Software Synchronization (starting on page 36) An examination of synchronization from the software perspective. Examines types
of synchronization, the coding for some examples, latency is introduced, interrupt processing software and sequencing is described.
Device Drivers (starting on page 48) Definition of device drivers and their needs.
Section Contents: Interfacing Software and an Introduction to Synchronization
III - 0.1
35
Software Development
A microprocessor system requires both hardware and software design.
Good software is written in a modular manner.
Main Program(s)
High degree of
abstraction
Functional Layer
Hardware
Abstraction Layer
Low degree of
abstraction
I/O Devices
Low
level functions interact directly with the systems hardware.

initialize device
read/write to the device
handle software synchronization through polling and/or interrupts
A comparison of the abstraction layers for software development.
III - 1
36
Software Synchronization
When a device completes its

task it must synchronize with
the processor.
Events may have a priority in
order to ensure minimum latency.
swsynch
time
device needs
service
service request
received
device latency
CPU latency
device service
initiated
device receives
service
CPU
device
CPU Latency and Device Latency : is the time between a service request and when the service
is initiated. Latency can involve both hardware and software delays.
Real-Time System: is one that guarantees a worst-case latency for critical events.
III - 2
37
Performance, Latency and Throughput

latthroug
Some unit that

processes requests and
produces results
Requests arrive at
times Tr1,Tr2, Tr3 ...
Results produced a
times Tp1, Tp2, Tp3...
Latency for the ith request is Tpi-Tri
Two terms that are used in discussing system performance are Latency and Throughput.
Latency : The delay between the arrival of the request and the completion of service. One
could also consider the average latency or the maximum latency by considering more results.
(Note: on the surface this appears to be slightly different than the definition of CPU Latency
defined earlier. However, this difference can be resolved by noting that the system is viewed as
completing the request once the ISR has started.)
Throughput: is a measure of how many items can be processed per unit of time. For example, a
system could have a very high latency (5 years for UW Engineering) but still have a throughput
of 900 graduates per year.
III - 3
38
Synchronization Mechanisms
Adapted from J.W. Valvano, Embedded Microcomputer Systems: Real Time Interfacing
Blind Cycle: software waits a fixed amount of time and then acts on the data whether or
not the device is ready
Periodic Polling : device status is checked after a pre-determined amount of time and this
repeats until the device is done. This is usually implemented with a timer interrupt.
Occasional Polling : device status is checked at the convenience of the designer.
Polling Loop (Gadfly or Busy Waiting): software continuously checks the I/O status,
waiting for the device to be done. Although this is often implemented as a very tight loop
(one status register test and then loop if not yet ready), it could be implemented as a
series of tests (say test 5 I/O status registers and service any that are requesting service).
III - 4
39
Synchronization Mechanisms Cont.

Interrupts
when device is done it generates a hardware interrupt
First 3 options are one-sided, as the synchronization is dependent primarily upon the CPU
timing
Polling loop and interrupts are more device oriented, the latency seen by the device is
minimized
III - 5
40
Polling Loop Synchronization Input
poll device and wait until data is available

while ( not data available ) loop //Tight polling loop
read data
clear data available flag (usually by hardware when data read)
process data
return
III - 6
41
Polling Loop Synchronization Output

poll before sending data
while ( not ready to output ) loop
clear ready to output flag (usually by hardware when data output)
output data
return
poll after sending data (this assumes that the interface is initially ready to output)
clear ready to output flag (usually by hardware when data output)
output data
while ( not ready to output ) loop
return
III - 7
42
Interrupt Synchronization
1. a device notifies the CPU of an interrupt request
2. CPU completes execution of the current instruction
3. execution of the main program is suspended
4. interrupts are disabled (processor specific)
5. some internal registers are saved (including the program counter)
6. device may be acknowledged
7. interrupt service routine is selected
8. interrupt service routine is executed (more on this later)
9. registers are restored, if required, including the program counter
10. interrupts are enabled (processor specific)
11. execution of the main program resumes
III - 8
43
CPU Notification
Interrupts must be handled from multiple sources
Single interrupt request line
CPU
IRQ
Device 1
Device 2
Multiple interrupt request lines

IRQ1
Device 1
CPU
IRQ2
Device 2
III - 9
44
Interrupt Service Routine (ISR) Selection

Non-vectored interrupts
devices are polled to determine source
priority must be determined (in software)
Handler for
Device
Device
interface
Device
interface
General Interrupt
Service Routine
Device
interface
Interrupt Request
Generated
Handler for
Device
Handler for
Device
Software Selects
Desired Code
Desired Code is
Executed
oneirq
III - 10
45
ISR Selection
Vectored Interrupts
requests are associated with an interrupt vector
fixed priority associated with the interrupt vector
interrupt service routine (ISR) at vector address is executed
Handler for
Device(s)
Device(s)
interfaces(s)
Handler for
Device(s)
Device(s)
interfaces(s)
Device(s)
interfaces(s)
Interrupt Request
Generated
Handler for
Device(s)
Hardware Assist
to Select ISR
Desired Code is
Executed
III - 11
46
Interrupt Service Routine (ISR)

should execute as fast as possible
1. any registers used by the function should be saved
2. device may be acknowledged
3. interrupts may be enabled to allow higher (and possibly same) priority interrupts (design
specific)
4. test for valid interrupt and/or determine the source of the interrupt
5. complete desired action
6. restore registers (interrupts may need to be disabled during this step)
7. return from interrupt
III - 12
47
Interrupt Initialization
The following steps need to be taken when initializing a system which uses interrupts.
1. disable all interrupts
2. enable device interface interrupts by setting appropriate device interface registers
3. set interrupt mask to allow interrupts from device
4. initialize interrupt vector with address of ISR
5. enable interrupts as required
III - 13
48
Device Drivers
A device driver is the software associated with a particular device. It will include:
Data Structures
variables needed to access the device interface registers
variables associated with the state of the device
data buffers
Initialization Functions
device initialization
synchronization initialization
initialization of driver variables
I/O Functions
functions to input and/or output to the device
interrupt service routine
The NIOS system provides the data structures and some of the driver functions for its devices as
part of the custom SDK associated with each design. This information can be found in nios.h
and nios peripherals.h.
Device Drivers
III - 14
49
Note: Terms used in Interfacing Software, Synchronization, Generalized IO, and

Device Drivers
Terms:
CPU Latency and Device Latency (page 36)

Real-Time System (page 36)
Latency (page 37)
Throughput (page 37)
Blind Cycle (page 38)
Periodic Polling (page 38)
Occasional Polling (page 38)
Polling Loop (Gadfly or Busy Waiting) (page 38)
Device Drivers
III - 14.1
Section IV:
Synchronization, Data Generation and Data Transfer
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51
Course Introduction: Synchronization and Data Transfer

Introduction (starting on page 52) Communicating finite state machines are introduced as a common thread for various parts of
the course. Peer-to-peer synchronization, types of synchronization and the elements (events and data) of data transfer are also
introduced. Persistent and transient events and data are compared.
Synchronous vs Asynchronous Systems (starting on page 67) Communication examples for synchronous and asynchronous systems
are described.
Generalized I/O Operations (starting on page 70) A view of IO in general terms. The software techniques described earlier are
considered. Three types of data sources (spontaneous, consumer responsive and consumer sensitive) are described. These models
permit a more complete discussion of latency.
Section Contents: Synchronization and Data Transfer
IV - 0.1
52
Finite State Machine Model of Interface Communication - Simplified

One key point in interfacing is time. The two sides of the communication (likely) operate with
different views of time.
FSMCommunication.
Introduction
IV - 1
53
One side of the interface

Data
Source
The other side of the interface

Time Zone 2
Time Zone 1
Await
new
data
Correct
Error
Await
Data
Read
Await
Cleanup
Prepare
for
new data
Signal
New
Data
Wait for
new
data valid
Data
Read
Other
Operations
Use/
operate on the
new data
Data
User
Introduction
IV - 1
54
Producer Consumer Model of Data Transfer

synchronization1
Producer
Consumer
Event
Data
Consider a producer/consumer system such as the one shown.

Producer : Either a software or a hardware component responsible for producing data (or
events) for the consumer.
Consumer : Either a software or a hardware component responsible for consuming data (or
using events) that have been produced by the producer.
Data: The value (or values) that are transferred from the producer to the consumer.
Event: represents the occurrence of some activity that is communicated to the consumer.
Introduction
IV - 2
55
Events and Data
Event Only: An event occurs (door

opens, shaft spins past some registered
point, a program initializes properly)
and this occurrence is transferred from
the producer to the consumer.
Data and Event: An event occurs
(key is pressed, message arrives, processor produces a value to print) and
the event and the data are transferred
to the consumer.
Data Only: Some data value is produced (or changed) but the consumer
is not directly notified of this change.
For example, a temperature of the engine block changes and can be read at
any time, but the change is not announced to the consumer.
Introduction
synchronization1
Producer
Consumer
Event
Data
IV - 3
56
Synchronization at several Levels - A Hierarchical Perspective

Synchronization must be considered at several levels. Consider the production of data from the
following levels.
I Data Generation: How is the data creation controlled (if it is controlled). How is it
started? stopped? Is this done by the Producer or the Consumer?
II Data Notification/Initiation of transfer : Once the producer has the data, how does
the producer notify the consumer that it is ready for the data to be consumed? Or,
alternatively how does the consumer request the data?
III Data Transfer : Once the producer has the data and the Consumer is ready for the
Data, how it the timing (synchronization) of the transfer handled?
Introduction
IV - 4
57
Synchronization at several Levels - A Hierarchical Perspective Continued

This structure can be considered as shown below.
peersynch2.
II
III
Introduction
I - Generation
of Information
II - Notification
/Initiation of transfer
III - Data Flow
II
III
Support for
Synchronizing peers
(Data Flow Issues)
IV - 5
58
Synchronization
Each level in the structure requires some form of synchronization.
Synchronization: For our purposes this refers to the interaction required to make two
entities (with different views of time) interact. For example, when do the two applications
interact?
Items included are listed below.
Active Synchronization: One of the entities is capable of forcing a change in the
operational characteristics of the other. For example, setting an interrupt signal can
force the processor to execute the interrupt service routine.
Passive Synchronization: One of the communicating entities signals a request for
service, however the entity receiving the request is not forced to respond.
Introduction
IV - 6
59
Synchronization
Relationship between/among the entities:
Number of communicating entities (two or more than two)
Is there a master/slave relationship?
Are the entities equals?
Level of service required
Active, demand oriented service. The event at one of the peers must be serviced.
This could be implemented as an interrupt.
Passive, request oriented service. The event at one of the peers may be serviced.
One side keeps testing the other to see if an event has occurred.
Introduction
IV - 7
60
Examples of Synchronization Configuration Scenarios

producerconsumer2.
Producer
Consumer
Consumer
Data
Produced
Poll
Data
Produced/
Event
Occurs
Producer
Poll
Poll
Poll
Read
Data
Write
Data
Producer
Data
Produced/
Event
Occurs
Consumer
Ready for
Data (event)
Consumer
Demand
Service
Response
Time
Optionally
Verify
Request
Read
Data
Ti m e
Consumer
Passive Notification/
Initiation and
Consumer Transfer
Introduction
Producer
Passive Notification/
Initiation and
Producer Transfer
Producer
Active Notification/
Initiation and
Consumer Transfer
IV - 8
61
Note: Examples of Synchronization Terms
Consider two situations: a printer (consumer) attached to a computer (producer) and a keyboard (producer) attached to a
computer (consumer).
The data is the value of the character to be printed or the key pressed. From the keyboards perspective the user provides
spontaneous input. On a higher level, the user is simply responding to a request from the application program.
The events would be the preparation of a character (or string) for printing and the typing of a key on the keyboard.
Synchronization, in the case of the keyboard could be by polling or by interrupt, in either case, the signal indicating new
data (the event) to be consumed would be from the producer to the consumer.
Synchronization, in the case of the printer, the event may provide an indication that a new character may be printed. (I.e.,
from the consumer to the producer.)
Missing from the figure is any form of flow control. This is considered later this term.
Introduction
IV - 8.1
62
I Generation
The Generation of the data requires action by the producer, however the cause of the creation
of the data can be at either the producer or the consumer.
Spontaneous Sources: Data is produced in the device independent of the actions of the
consumer accepting the data.
Consumer Sensitive Sources: Data is produced by the device only after the previous data
has been consumed by the consumer. (more implicit.)
Consumer Responsive Sources: Data is produced by the device only after requested by the
consumer. (more explicit.)
Introduction
IV - 9
63
Consumer Responsive, Consumer Sensitive and Spontaneous

spont consumer
Data
Data
Consumed
Introduction
Event
Data
Available
Producer
Consumer
Producer
Data
Consumer Responsive
Data
Available
Data
Producer
Event
Data
Available
Consumer
Event
Consumer Sensitive
Consumer
Spontaneous
Data
Request
IV - 10
64
II Notification or Initiation of Transfer

Notification of transfer (or initiation of transfer) may be initiated by either the producer or the
consumer.
Consumer initiated: The consumer requests data, then the data either becomes ready
(or already is ready) and then the request is completed.
(passive synchronization) Polling for a key to be pressed, once it is pressed the data
is consumed.
(active synchronization) An interrupt from a printer to indicate that it is ready for
the next item to be printed.
Producer initiated: The data is available, (eventually) the data is accepted by the
consumer and then the transfer is complete.
(passive synchronization) Polling for a printer to become ready for the next character,
once it is ready the data is transferred and consumed.
(active synchronization) An interrupt from a keyboard to indicate that it has the next
character ready to be consumed.
Introduction
IV - 11
65
III - Data Transfer

Data Transfer : Refers to all aspects of a transfer between two entities that have (potentially) different views of time. For example, how do the two systems interact.
Data
transfer includes: data persistence, clocking, and control signalling. Items included are
listed below.
Data Persistence: How long data is valid for transfer between the communicating
entities.
Time Synchronization and Clocking : How signals, representing any data, are specified
and enabled to make the transfer happen.
Control Signalling : How any control information is exchanged between the communicating entities.
Introduction
IV - 12
66
III - Data Persistence Duration

Persistent: Information remains valid until consumer signals that the data has been collected (processed).
Transient: Information is made available to the consumer and remains valid for a period
of time and then may change. In most cases the minimum period of time is known by the
designer.
Introduction
IV - 13
67
Need for Synchronization
Consider blind synchronization.

In the timing example, the consumer just reads
the data with no
regard for the
changes at the
producer.
Some
errors
could
occur
if the data
changed
too
close to the
sample time.
synch1
System 2
System 1
Data
producerconsumertimenotime
Producer
Clock
Producer
Data
Data 1
Data 2
Data 3
Producer Time: Data changes only on falling edge of local clock
Consumer
Clock
Sample
Every (local)
Falling Edge
Data Only Transfers, Not attempt to synchronize with data changes
Synchronous vs Asynchronous Systems
IV - 14
68
Synchronous Common View of Time

synch2.
Synchronous Transfer
(Common View of Time)
Data
System 1
System 2
producerconsumertimecommon
Global
Clock
Producer
Data
Sample
Every
Rising Edge
Data 1
Data 2
Data 3
Producer Time: Data changes only on falling edge of global clock
Since the data is known correct at the rising edge, sample then
IV - 15
69
Asynchronous Different Views of Time

synch3.
Asynchronous -- must share

view of time to transfer
data
System 1
Time
System 2
Data
producerconsumertimesharetime
Producer
Clock
Producer
Data
Data 1
Data 2
Data 3
Producer Time: Data changes only on falling edge of local clock
Sample
When time
signal received Transfer (read) data only when told to by producer (correct time provided)
IV - 16
70
Generalized I/O Overview

The steps necessary to perform an Input/Output (I/O) transfer are:
Global Initialization: setting processor and I/O interface parameters necessary for the
overall operation on the system. (Eg., set interrupt tables, specify unchanging bidirectional
ports to input/output) Executed once.
Transfer Initialization: setting processor and I/O interface to facilitate a specific process.
(Eg., set the memory location to accept (provide) the data for the transfer, set the block
and track number for a disk transfer.) Executed once per transfer. Later in these notes,
in the specific case of multiple transfers this step is referred to as Block Initialization
Transfer the Data: including synchronization.
Generalized I/O Operations
IV - 17
71
III - Data Transfer - Example Continued

The explanation below assumes that data is to be transferred from an interface to the processor
(I.e., a read operation.)
Recall the three components of synchronized data transfer
I Generation: Source Characteristics (Spontaneous, Consumer Sensitive and Consumer
Responsive).
II Notification/Initiation of Transfer (to detect when data can be transferred) and
III Data transfer (to actually perform the transfer)
IV - 18
72
Note: Transfer Assumptions

In this generalized description, we have attempted to look at I/O with as few restrictions as possible. As a result we use the
terms: unit and data unit to describe individual bus transactions and the term block to describe sets of data units that require
synchronization.
For example the data transferred in 1 bus transaction is 1 data unit, where the size of the unit is the size of the data bus.
Synchronization is associated with one or more units of data, constituting a block. For example, synchronization can occur for each
sector of a disk, for each block transmitted using a synchronous communication channel, or for a single byte written to an I/O device.
Normally synchronization occurs before the data is transferred.
IV - 18.1
73
I - Impact of Generation
progcontrol0
Device and
Interface
Time
Consumer
Sensitive
Spontaneous
Consumer
Responsive
tinterdata
Data Available
The figure shows the

data transfer phase of
a READ I/O operation. It shows the
three different source
characteristics. Note,
Each transfer contains
1 unit of data.
ttransfer d
repeat if
multiple
transfers
required
READ Operation
Device Centric
IV - 19
74
Overview Data Transfer - Terminology

ttransf er producer : is the time for the device and interface combination to transfer one
data unit. This determines the maximum rate at which data could be available to the
processor.
ttransf er
consumer :
the time the processor needs to transfer one data unit. This may be
longer or shorter than ttransf er d but
the actual transfer time will be Maximum(ttransf er
(The figures assume ttransf er
> ttransf er
consumer
prod
producer ).
tsynch: is the execution time of the processor to synchronize with the availability of the
data. (I.e., the time that the processor is not available for other activity.)
Note:
tsynchpoll : Polling synchronization uses processor time until just after the data is
ready.
tsynchintr : Interrupt synchronization only starts to use CPU time after the data has
become available.
tinterdata: is the time between consecutive data blocks. Although this time could vary
between blocks, for these purposes it has been assumed to be a constant.
IV - 20
75
II Impact of Notification/Initiation - Read Data Transfer - 1 Unit
progcontrol1
CPU Activity (Consumer)

Interrupt
(n = 1)
Polling
(n = 1)
tinterdata
tsynch-poll
ttransfer producer ttransfer consumer
repeat if
multiple transfers
required
Periodic
Polling
Other CPU Activity
Producer
Device and
Time
Interface
(Polling synch
time shown)
Data Available
The figure shows the data

transfer phase of a READ I/O
operation. It assumes a Consumer Sensitive data source,
and that each block contains
only 1 data unit.
ttransf er d < ttransf er p therefore the actual transfer time =
ttransf er p
Occasional
Polling
White space
Other CPU
Activity
tsynch-intr
Note: if
IRQ used,
a diffferent
device
timing is
needed
Read Operation,
Consumer
Sensitive
I/O Device
One Transfer per
Synchronization
IV - 21
76
Read Data Transfer - 2 Units
progcontrol3
CPU Activity
Interrupt
(n = 2)
Polling
(n = 2)
tinterdata
tsynch-poll
Other CPU Activity
Device and
Time
Interface
(Polling synch
time shown)
Data Available
The figure shows the data

transfer phase of a READ I/O
operation. It assumes a Consumer Sensitive data source,
and that each block contains 2
data units.
ttransf er d < ttransf er p therefore the actual transfer time =
ttransf er p
tsynch-intr
ttransfer producer
ttransfer consumer
Note: if
IRQ used,
a diffferent
device
timing is
needed
repeat if
Read Operation,
multiple transfers
Consumer
required
Sensitive
I/O Device
Two Transfers per
Synchronization
IV - 22
77
Overview Data Transfer - Transfer Time Estimate

The table below summarizes the time to transfer 256 data units. In the table, n is the number
of data units that are in one block (and thus synchronized in one step). Eg. n = 1 indicates
that each data unit is synchronized and n = 256 indicates 256 data units are synchronized at
once.
The table assumes the following:
ttransf er = Maximum(ttransf er
producer , ttransf er consumer ).
tsynch refers to the time for the appropriate synchronization technique (polling (tsynchpoll ) or
interrupts (tsynchinter )).
and
twait =
tsynchpoll
polling busy wait-loop
tsynchintr + tinterdata interrupt
IV - 23
78
Overview Data Transfer - Transfer Time Estimate
Items per
synch.
1
n
256
Consumer Sensitive Device.

CPU time required
(minimum) total time
for transfer
256 (tsynch + ttransf er )
256 (twait + ttransf er )
256
d 256
e
t
+
256
t
d
synch
transf
er
n
n e twait + 256 ttransf er
tsynch + 256 ttransf er
twait + 256 ttransf er
Note that the assumption that tinterdata is fixed regardless of the size of the block is unusual.
IV - 24
79
Note: Terms used in Synchronization and Data Transfer

Terms:
Producer (page 54)

Consumer (page 54)
Data (page 54)
Event (page 54)
Data Generation (page 56)
Data Notification/Initiation of transfer (page 56)
Data Transfer (page 56)
Synchronization (page 58)
Active Synchronization (page 58)
Passive Synchronization (page 58)
Spontaneous Sources (page 62)
Consumer Sensitive Sources (page 62)
Consumer Responsive Sources (page 62)
Data Transfer (page 65)
Data Persistence (page 65)
Time Synchronization and Clocking (page 65)
Control Signalling (page 65)
Persistent (page 66)
Transient (page 66)
Global Initialization (page 70)
Transfer Initialization (page 70)
ttransf er producer (page 74)
ttransf er consumer (page 74)
tsynch (page 74)
tsynchpoll (page 74)
IV - 24.1
Section V:
Computer Structure
f2014-1.0
Computer Structure
81
Computer Structure: Section Contents

CPU-Memory Interface (CPU Version) (starting on page 91) The single bus CPU model is used to motivate the needs for the system
bus from the CPUs perspective.
CPU-Memory Interface (Memory Version) (starting on page 95) The needs for communication from the memorys perspective are
described. This includes the potential for synchronous and asynchronous communication alternatives.
Multiple Drivers (starting on page 101) How to attach more than one device that can drive a value onto a line. This discussion
centers around the electrical alternatives for these connections. Tri-state, passive pull-up and passive pull-down alternatives are
described and compared.
Device Selection (starting on page 121) Explicit and passive selection techniques are examined.
Overview of Device Selection with Synchronous Bus (starting on page 124) Requirements for attaching to a basic synchronous bus
described. Both read and write operations are shown.
Reality Check (starting on page 130) Although most previous courses have assumed that the timing of signals was appropriate.
Metastability may occur if the setup or hold time is violated.
Synchronous Bus Introduction (starting on page 131) Definitions of the terms and times used in this section of the notes including
skew time, propagation delay, select time and access time. There is also a discussion of the features common to all bus structures.
This material is covered in more detail later in the course.
Synchronous Bus Transfer (starting on page 141) The synchronous bus is used as the basis for the discussion of bus data transfer
structures. The timing and interconnections required to support a basic synchronous bus are described here with the more complex
discussions left for detailed coverage later in the term.
Questions (starting on page 148)
Section Contents: Computer Structure
V - 0.1
Computer Structure
82
Computer Organization
ECE 224 ECE 222

and ECE 150
ROM
RAM
Interface
Device
Interface
Device
gene121
CPU
RAM
Clock
Typical (no frills) Computer

Structure
Background
V-1
Computer Structure
83
System Bus Introduction

A key element of the system.
Why a bus? A flexible interconnection scheme
What is a bus? A shared communication scheme.
What are the components of a bus?
A technique to select the two (or more) communicating entities. Often, but not
always an address of one of the communicating entities.
A set of lines/signals to transfer the data item
Control signals for the bus.
Background
V-2
Computer Structure
84
System Bus Structures

Memory Mapped I/O
I/O devices are connected to the system in a manner similar to memory.
CPU
I/O Interface
Device
Register
Memory
Separate I/O Bus

I/O devices are connected to the system using a separate bus (I.e., using a bus separate
from the one used to communicate with memory.
The bus can be physically or logically separate.
I/O Inteface
Memory
Background
CPU
Register
Device
V-3
Computer Structure
85
Memory
Stores instructions or data (indistinguishable except by context of read/write).
Stored memory values are accessed using their address
Memory is connected to CPU using one (or more) buses.
ROM (Read Only Memory): usually contains the sequence of instructions necessary to
place the processor in a known start-up state. This may be the final state (if a monitor
is used as in the lab) or this state may be just the starting point for a more functional
operating system.
RAM (Random Access Memory) used to store values and programs that may change.
There is no distinction between ROM and RAM addresses (other than they tend to be in
groups).
Background
V-4
Computer Structure
86
CPU
Central Processing Unit composed of:
Arithmetic and Logic Unit(s): to perform operations required by the instruction
sequence
Registers:
Data Registers: to provide internal storage for intermediate results. (Also referred
to as General Purpose Registers.)
Special Purpose Registers (contents listed):
Program Counter (PC): address of the next instruction to be read.
Instruction Register (IR): current instruction (NOT its address)
Program Status Register (PSW): Current status of execution (flags etc.)
Stack Pointer (SP): In CPUs that support stack-oriented operations (push,
pull, jump to subroutine, return from subroutine ... ) the SP points to the
top of the stack.
Memory Address Register (MAR) and Memory Data Register (MDR). Although not accessible to a programmer, these are the registers used to send
and receive data over the system bus.
Memory Address Register (MAR) and Memory Data Register (MDR): registers
used to permit access to memory.
Background
V-5
Computer Structure
87
Control Unit: to read instructions from memory to generate a sequence of operations.
Background
V-5
Computer Structure
88
Control Signals
Many operations are triggered by a control signal.
An active high control signal indicates a certain condition when it has a value of 1.
An active low control signal indicates a certain condition when it has a value of 0.
A rising-edge occurs when a signal changes from a low voltage to a higher voltage.
A falling-edge occurs when a signal changes from a high voltage to a lower voltage
signals.
Rising Edge
Falling Edge
Active High RD Signal
RD
/RD
Active Low RD Signal
Inactive
Background
RD Active
Inactive
V-6
Computer Structure
89
Clock
In general terms a clock provides synchronization among two or more units.
In general terms a clock may be implemented as an active edge (rising and/or falling) on
a given signal. A clock may have any duty cycle, and may even be specified by multiple
signals.
In the case of a processor, such as those discussed this term, the (processor) clock signal
is a source of regular, periodic rising and falling edges.
The processor clock can also be used as a measure of the time required to execute a given
instruction.
Changes in output signals occur in a predictable relationship with the system clock.
Input signals are sampled at a predictable time with respect to the system clock.
Background
V-7
Computer Structure
90
Clock (cont.)
clocks.
(a) Single Phase Clock: 2 edges
(b) Two Phase Clock 4 edges
(c) 2 phase clock 4 edges
Background
V-8
Computer Structure
91
CPU-Memory Interface (CPU Version)
File:222rev.
Read Write
IR
Control
Rn
MFC
Processor
Control
Unit
R1
...
From Computer Organization, Hamacher, Vranesic and

Zaky 5th Ed. Chapter 7, Section 7.1-7.2, and 7.4
Consider the one-bus 32-bit
CPU structure shown below.
PC MAR MDR
To Memory
M UX
Internal CPU BUS
Const 4
ALU
Select
V-9
Computer Structure
92

Sample Instruction execution Sequence (Figure 7.6 (HVZ))
* R1 R1 + [R3]
Step
1
2
3
4
5
6
7
Action
PCout, MARin,READ, Select Const 4, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
R3out,MARin, READ
R1out, Yin, WMFC
MDRout, Select Y, Add, Zin
Zout, R1in, END
V - 10
Computer Structure
93

Review Internal Operation
Note the Memory Interface operations
MDRin, MDRout, MARin, READ, WRITE, WMFC
What does READ/WRITE do/mean?
What about WMFC?
V - 11
Computer Structure
94
CPU-Memory Interface (CPU Version) cont.

MDRdetail.
Mux
READ/MDRin
Clock:
MDRIn or
MFC
To/From
External
(system)
Bus
To/From
CPU Internal
Bus
Write
MDROut
Abstracted view of MDR Structure
V - 12
Computer Structure
95
CPU-Memory Interface (Memory Version)
Where are:
MAR?
MDR?
READ?
WMFC?
File:222read1.
Address
Control
MDR
CPU
Clock Rate: 100MHz
Period: 10 ns
MAR
Memory Read Operation
Memory
Access Time:
50 ns
(+/- 5 nsec)
Data
How can the clocks be synchronized?

How is the MFC signal used?
When does the value come back from memory?
V - 13
Computer Structure
96
CPU - Memory Timing Interactions

CPU and Memory may differ by a significant difference in performance (factor of 5 in the
example). Assume that the memory has the following performance.
File:222read3.
Read Operation
Address
Data
Address 1
?
Data 1
Address 2
?
Data 2
V - 14
Computer Structure
97
CPU - Memory Timing Interactions - Synchronous Option
CPU could specify that it will

only transfer data one out of
5 cycles. (One example is
shown below)
The memory uses the Sync
Pulse to indicate when the
memory address is correct.
Note all CPU transfers are
at the same rate in this case
(data must be correct by the
end of the 5th pulse following
the sync. pulse (i.e., the fifth
falling edge)).
File:222read4.
CPU CLK
Sync Pulse
Address
Valid Address
Data
Valid Data
1 Memory Cycle
V - 15
Computer Structure
98
CPU - Memory Timing Interactions - Asynchronous Option

CPU and memory could exchange timing signals.
CPU CLK
(Not used by
1
Memory)
Processor
Sync Pulse
Address
Memory Sync
Signal
(From Processor View)
Valid Address
(From Memory View)
Data
Valid Data
File:222read5.
Processor now waits until the memory has produced the requested value.
V - 16
Computer Structure
99
CPU - Memory Signals

What happens if there are two (different) memories involved?
Memory Read Operation
Memory
10 ns
(+/-1 ns)
CPU
Clock Rate
100 MHz
(10 ns)
Address
Data
Memory
50 ns
(+/- 5 ns)
File:222read2.
V - 17
Computer Structure
100
Multiple Driver Issues

The following questions must be considered.
How are multiple drivers for the same line handled (ECE 124 and ME 262)?
How is one device selected from a set?
V - 18
Computer Structure
101
Multiple Drivers
Consider the simplified case shown below.
File:223a.
How do the AND gates

safely drive (in the sense of relibility for the devices) and
reliably interpret
the shared line?
When does Memory 1 or Memory 2 drive the line?
Multiple Drivers
V - 19
Computer Structure
102
Multiple Drivers
At the transistor level (For our purposes consider the following transistor model ... See ECE 231
and 332 for more precise models)
VCC
Cuttoff
VBE < 0.4 V
Gnd
File:223d.
Multiple Drivers
V - 20
Computer Structure
103
Note: Signal Levels

This term we will be using a variety of specific signally levels. The figure below illustrates some of the terminology that we will be
using this term.
Low
(for 224/325 a 0)
1.5 V
Multiple Drivers
Noise Margin
signallevels
High
(for 224/235 a 1)
2.5 V
Voltage
V - 20.1
Computer Structure
104
Multiple Drivers
Consider a standard AND Gate (With a totem-pole output driver)
+VCC
1
0
VCC-0.1V
{Or digital value 1}
0.1V
{Or digital value 0}
0
1
Gnd
File:223c.
Multiple Drivers
V - 21
Computer Structure
105
Note: Source and Sink Current

sourcing.
Output 0
(Low impedence
to low voltage)
Input: High impedence,

however with no input the
input will float to some level.
Sinking current
(to lower voltage at load(s)
current is flowing to ground level)
Output a 1
Sourcing current
(to raise voltage at load(s))
Multiple Drivers
V - 21.1
Computer Structure
106
Note: Source and Load Currents

ilinearSourceLoad.
+5 V (or 0V)
1k
Assume Linear Source and Load

to get equivalent cct.
1k
1k
1k
I
+
1k
Multiple Drivers
V
-
Develop IV Characteristics
+
V
-
1k
V - 21.2
Computer Structure
107

linearSourceLoad2.
Develop IV Characteristics
+
V
I (ma)
1k
3
2
1
V (Volts)
Multiple Drivers
V - 21.3
Computer Structure
108

sourceload.
Output = 0\0
I
V
Output = 1
Multiple Drivers
Input Impedance
V - 21.4
Computer Structure
109
Note: Source and Load Currents Merged

sourceloadmerged.
Interpret as
a 0 (low)
Interpret as
a 1 (high)
I
V
Output = 1
V
Output = 0
Input Impedance
Multiple Drivers
V - 21.5
Computer Structure
110
A More Complete View

Now connect two of these drivers together (This cannot work if the memory values are different!)
VCC
Memory 2
(From AND gate)
Memory 1
(From AND gate)
Bus Line
(shared)
MDR
Gnd
File:223b.
Multiple Drivers
V - 22
Computer Structure
111
A More Complete View with current flow
VCC
0
V2
V1
0
Based on Q3 and Q4
V1 would be (VCC - 0.1 V)
Based on Q1 and Q2
V1 would be 0.1 V
Gnd
File:223bcur.
Multiple Drivers
V - 23
Computer Structure
112
Alternatives
Must prevent two (opposite direction) transistors from being active at the same time.
Eliminate two of the transistors
Permanently passive pull-up or pull-down, (e.g., open-collector (BJT) or opendrain (MOS/CMOS) are passive pull-up and open-emitter (BJT) or open-source
(MOS/CMOS) are passive pull-down)
Temporarily (Tri-State)
Multiple Drivers
V - 24
Computer Structure
113
Alternatives - Passive Pull-Up (Open-Collector)

Eliminate the two transistors that could pull the bus line to supply voltage.
Must replace with a passive component (resistors)
VCC
To MDR and others
VCC
Gnd
VCC
I= ((VCC-0.1)/R) A
I=0A
0.1 V
ON
OFF
(no Current
Flow)
File:223e.
Multiple Drivers
V - 25
Computer Structure
114
Passive Pull-Up (Open-Collector) Example
VCC
VCC
ON, VCE=0.1 V
OFF
M1
ON, VCE=0.1 V
M2
M2=1, M1=0
VBUS=0.1V
ON, VCE=0.1
M1
M2
N1
Gnd
N2
M2=M1=0
VBUS=0.1V
Gnd
File:223f.
Multiple Drivers
V - 26
Computer Structure
115
Note: Terminology
In different situations the terms Wired-And and Wired-Or are used to describe behaviours associated with passive pull-up and
pull-down structures.
In the previous figure, a passive pull-up structure, B may be considered as a function of M1 and M2 or as a function of N1 and N2.
Input
Output
Input
M1
M2
N1
N2
In this case, the bus line is an AND of the two memory lines, and a NOR of the intermediate signals N1 and N2.
Multiple Drivers
V - 26.1
Computer Structure
116
Alternatives - Active Pull-Up and Pull-Down (Tri-State)

It is also possible to add gating so that at any given time only one pair of drivers can be
enabled.
File:223g
Enable
Signal Value
Q1
Tri-state
Output
Signal Enable Output

Value
0
0
Z
1
0
Z
0
1
0
1
1
1
Q2
Enable
Signal Value
Output
Multiple Drivers
V - 27
Computer Structure
117
Active Pull-Up and Pull-Down (Tri-State) Example

Or in a bus situation
Address Lines
address and timing decoder (ATD)

Enable 1
M1
signal
value
Synchronization
signals
Enable 2
MDR
M2
Q3
Q1
Q4
Q2
Tri-State
Output
Add high-impedance R to provide

a value if no driver is enabled.
File:223h
Multiple Drivers
V - 28
Computer Structure
118
Differences - Timing
Consider the following:
Enable
Transistor
on resistance = r
r << R
Signal Value
Q1
Q1
C
Q2
Tri-state
Output
223eg.
Multiple Drivers
V - 29
Computer Structure
119
Differences - Timing
Passive pull-up means that the parasitic capacitance (C) of the bus wire is charged through
the resistor R.
If R is too small, then very large (slow) transistors are needed
If R is too large, then capacitor charges very slowly
t=RC
t=rC
t=rC
t=rC
File:223i.
Multiple Drivers
V - 30
Computer Structure
120
Differences - Errors
Impact of Multiple Drivers (with different values) enabled on the same signal line.
Impact at the Receiver (Reliability - of the transfer)
Passive pull-up: the value read will be low in all cases. (I,e., if one is pulling down
the value is down.)
Active pull-up and pull-down (I.e. totem-pole). The value read will be indeterminate.
If you have a passive pull-down then since one will be pulling up the value read will
correspond to a high value.
Impact at the Drivers (Reliability - of the device(s))
Passive pull-up drivers, or passive pull-down drivers could tolerate multiple active
drivers.
Active pull-up and pull-down systems may have short or long term problems with
conflicting values.
As a result, in most cases, one must select or enable at most one driver per line
at a time.
Multiple Drivers
V - 31
Computer Structure
121
Device Selection
In the event that one or more signal lines has more than one possible driver, there must be
some technique to select the current driver (or it must be possible to have more than one driver
enabled at one time.)
Explicit Selection
Passive Selection
Bus signals:
may permit multiple drivers on at
Data transfer signals includthe same time.
ing
decision not based on an explicit
address, therefore based on other
Address signals
criteria.
Data lines
Direction control
time (Eg. every 10 ms a dif Timing control
ferent device starts to drive
Bus arbitration signals (later)
the shared line.)
Special purpose signals.
external events (IRQ lines)
tends to be used in special applications, examples presented as
needed in the term.
Device Selection
V - 32
Computer Structure
122
Simplified Explicit Device Selection Using a Passive pull-up structure

223n
Memory 2
Memory 1
Bus Line
(shared)
Decoded Address
=0 except when
Address of M1
is detected
Q2
Enable 1
Decoded Address
=0 except when
address of M2 is
detected
Q4
Enable 2
Address and Timing Decoder (ATD)

Address Lines
Device Selection
V - 33
Computer Structure
123
Simplified Explicit Device Selection Using a Tri-state structure

223h
Address Lines
address and timing decoder (ATD)

Enable 1
M1
signal
value
Enable 2
MDR
M2
Q1
Q3
Q4
Q2
Tri-State
Output
Device Selection
Synchronization
signals
Add high-impedance R to provide

a value if no driver is enabled.
V - 34
Computer Structure
124
Sample Bus Structure

For
now, just consider a basic set of data transfer control signals.

Address lines (named Addr0 ... Addr15)
Data lines (named Data0 ... Data15)
A Read/Write signal
Overview of Device Selection with Synchronous Bus
V - 35
Computer Structure
125
Read Timing Example
Consider the read operation shown below

Clock (Ck)
Addr
(CPU)
Valid Address
R/W
Reading a value from a device attached to a bus requires the following:

the correct address and
the correct timing.
Read
Data
(Mem)
Valid
Data
A
B C
File:223j.
Time A the CPU (the bus master ) drives the address value and the R/W signal onto the
appropriate bus lines.
Time B, the bus slave assumes that the bus signals are correct
Time C (at some time later) the bus slave drives the data lines with the requested value.
V - 36
Computer Structure
126
Address Decoding - Read

What could the circuit look like to perform the bus slave actions?
Assumptions Required
Bus Master has allowed for the amount of time required to decode the address
before the active part of /Read occurs.
Option 1. ... No Aliasing
Option 2. ... Aliasing Permitted
V - 37
Computer Structure
127
Address Decoding - General Structure

addressdecode1.
Address
and
Timing
Decoder
(Centralized ATD)
A0-Ae-1
R/W
(Chip) Select
or
Device Enable
Am-1
A4 A3 A2 A1 A0
Register
Select
Decentralized
ATD
Register
Select
Ae-Ae+m-1
Address
Lines
CPU/Bus Master
Address bits
Device
Interface
Device
Clock
Data Lines
V - 38
Computer Structure
128
Aliasing vs No Aliasing
No aliasing - the address decoder deals with Aliasing - the address decoder deals with only
all of the address lines except those allocated a subset of the address lines except those alto Register/Internal decode.
located to Register/Internal decode.
A15
A15
A11
A11
Select:
1000 xx00 0010 xxxx
let e=4 and m=12
A9
A8
Select 0x842X;
let e=4 and m=12
A8
A4
A4
Time Information
(more later)
Time information
(more later)
noalias.
alias.
V - 39
Computer Structure
129
Write Timing Example

Consider the following write operation
Clock
Addr
(CPU)
R/W
Data
A
File:223k.
At time A the bus master drives the address, R/W and data lines
At time B the bus slave assumes that the bus signals are correct
At time C the data is clocked into (stored) the appropriate device interface register. (This
is a bis of a simplification that we will address later in the term.)
V - 40
Computer Structure
130
Metastability
Unfortunately, reality is seldom as simple as we would like
Consider the following scenarios.
Ck
D
hold
setup
File:meta1.
Ck
Ck
Q
Valid timing
new value stored
Violates Setup
Time
Ck
Ck
Possible Metastable
signals
Valid Timing
old value kept
Reality Check
Violates Hold
Time
V - 41
Computer Structure
131
Synchronous Bus Introduction

The Buses - Data Transfer (starting on page 433) section of these notes examines different
types of buses in more detail. In this section of the notes one specific bus version, based on
a purely synchronous transfer, is examined. In addition a number of terms are defined, all of
the terms required for all of the buses examined are also defined in the Buses - Data Transfer
(starting on page 433) section of the notes.
V - 42
Computer Structure
132
What are the needs of the interconnection network?

provide a flexible, bidirectional path among a number
of digital components.
provide a mechanism for addressing the various components.
provide a defined mechanism
for controlling the timing of
transfers between the various
components.
Why a bus?
to limit the number of interconnection signals and the
complexity of the wiring structure, need to share and re-use
interconnection signals.
to keep reasonable performance, need to pass a reasonable number of data and/or
address bits at one time.
whyabus.
Processor
Disk
Interface
Serial
Interface
Interconnection Mechanism
Memory
Analog
Interface
V - 42
Computer Structure
133
Connections Alternatives
File:busringstar.
Daisy Chain
Wiring structures play a role
in the bus arbitration scheme
alternatives
Star
Bus
V - 43
Computer Structure
134
What are the characteristics of a synchronous bus?
a common view of time (often

a clock) is available to all of
the attached devices.
there is a control line to indicate if the operation is a read
or a write.
all operations are assumed to
require the same amount of
time to complete.
there is no feedback from the
consumer to the producer to
alter the rate of transfer or
to alter the duration that the
data is valid.
synchronous0.
I/F Clock
Processor Clock
Processor
(Master
only 1 in this
case)
Bus
Clock
Source
Interface1
Memory 2
Memory1
Address
Decode
Address
Decode
Address
Decode
Data
Address
Clock
R/W
V - 44
Computer Structure
135
Signal Conventions
Single Signal Representations

Abstract signal, instantaneous change
Rising edge, some allowance for delay in
transition
Rising edge, imprecision in start time and
some allowance for transition delay
Signal of unknown value at start, but has
known value after transition.
Multiple Signal Representation (E.g., Address lines)

Tri-stated line takes on value
Tri-stated Signal, imprecision on start time
Change of value (unknown value) or listed

as shown as A and B.
File:glossary.
V - 45
Computer Structure
136
Bus Transfer Terminology

Address propagation delay (tP A): The time for the address to propagate from the bus
master to all of the potential slaves.
Data propagation delay (tP D ): The time for the data to propagate from the data source
to all of the potential data receivers.
Bus Propagation delay : The maximum of the separate (Data and Address) propagation
delays.
tp = Maximum propagation delay for all signals
= Max(tP A, tP D )
Setup Time (tSetup): The minimum time that a signal has to be available at the input to
the buffer before the active clock signal (edge) arrives. (At the slave for a write and at
the master for a read.)
Hold Time (tHold): The minimum time that data has to be held stable after the clock
edge that triggers the transfer. (At the slave during a write and at the master during a
read.)
Bus Terminology
V - 46
Computer Structure
137
Bus Transfer Terminology (Cont.)

Select Time (tS or tSelect): The time required for a device (or interface) attached to
a shared communication media (a bus) to detect that the current transfer involves the
device (or interface). This time does not include any of the time required by the device
(or interface) to perform any internal address decoding.
tselect.
tselectw.
(Chip) Select
m address
lines
n address
lines
Address Valid
Chip Select
tSelect
tAccess
Data Valid
Device Interface
With 2n addressable
locations
READ
Data
Address (at least m+n address lines)
Note: No timing signals shown

(so just address decoder, no timing
decoder)
Bus Terminology
Address
Decoder
Address
Decoder
Address Valid
Chip Select
(Chip) Select
m address
lines
n address
lines
Device Interface
With 2n addressable
locations
Data
Address (at least m+n address lines)
Data Valid
tSelect
tStore
(Any change
in data after
the end of
tStore will not
affect the stored

values)
WRITE
Note: No timing signals shown
(so just address decoder, no timing
decoder)
V - 47
Computer Structure
138
Bus Transfer Terminology (Cont.)

Access Time (tAccess): The time required for the interface to access the information for
the bus after the device or interface has been selected and the address is correct. The
exact order that the select is correct and the address is correct may vary depending on
implementation details. The access time is the time following the last of these two events.
Store Time (tStore): The time required for the interface to enable the correct location and
to write the appropriate value into that location after the device (or interface) has been
selected and the address is correct.
Skew Time (tSkew ) (partial): For our purposes here the skew time is the difference (largest
or worst case) in signal propagation times. Although various sets of signals could have
different values of skew time (E.g., the address lines or the data lines), one value, the
largest, is used in this presentation. A more general definition would be the magnitude of
the difference between two events that ideally would occur simultaneously. (This definition
was taken from the JEDEC dictionary.) Of course this definition does allow for skew on a
single signal (discuss this with your instructor.)
Margin Time: In the figures in this section tM 1 (or tmargin1) and tM 2 (or tmargin2) are the
times where there may be some design flexibility. More generally, the margin time is the
overdesign that a designer includes for safety to assure successful operation.
Bus Terminology
V - 48
Computer Structure
139
Note: A second look at tAccess

tAccess Expanded.
A:
Focus of
224/325
Select
tAccess
sufficiently
long that
address does not
impact output
Address
Lines
Valid Address
Select
Data
Out
Valid Data
tAccessAddress
Address
Lines
Select
Data
Out
Bus Terminology
Valid Address
sufficiently
long that
select does not
impact output
Valid Data
V - 48.1
Computer Structure
140
Skew
Wires are not infinitely fast

nor are they all created equal.
Sources of skew:
differences in propagation delays due to differences in wire lengths
(minor)
logic
gate
(i.e.
transceivers)
delay
differences
(much
larger),
rise and fall times due to
capacitive effects (very
variable)
Bus Terminology
skew.
Skew
At Source
At Destination 1
(fastest)
At Destination 2
(slowest)
Delay
(tp)
V - 49
Computer Structure
141
Synchronous Bus Transfer - Block Diagram (Read)
Address
and
Timing
Decoder
(Centralized ATD)
A0-Ae-1
(Chip) Select
or
Device Enable
Decentralized
ATD
Register
Select
Ae-Ae+m-1
Address
Lines
CPU/Bus Master
synchreadblock.
Device
Interface
R/W
Device
Clock
Data Lines
Internal Signals
for bus
Enable
Output
Data
Bus
Synchronous Bus Transfer
V - 50
Computer Structure
142
Synchronous Read (Single Clock) - Ladder Diagram

synch3 ladder
Time at
Master
CK1
Synchronous Bus Read

Single Clock
Time at
Slave
Address and
t +t
Control (Clk, R/W) PA Skew
Master Edge
tmargin1
Decode address on bus and select slave
Time to access the requested data
tmargin2
tSetup
tHold
Slave Edge
tSelect
t Access
tPD+ tSkew
Slave removes data
Note: Next cycle must be delayed by

tHold.
Time at
Master
Time at
Slave
V - 51
Computer Structure
143
Synchronous Read (Single Clock) - Timing Diagram
Synchronous Read Bus Transfer (Master and Slave Timing the same at the edges)
Phase 1
tPA tSkew
Valid Read Address
Address
R/W
tSelect
Address
Decoded
>0
Enable
Output
tPD+tSkew+tAccess
Valid Read Data
Design Margin
tM1
tM2
tHold
Minimum
Phase 1
Data
Master Edge
Phase 2
tSetup
Clock
Slave Edge
tSelect+tAccess+tSkew+tPD+tSetup+tM2
One Bus Cycle
synch3.
V - 52
Computer Structure
144
Address
and
Timing
Decoder
(Centralized ATD)
(Chip) Select
or
Device Enable
Decentralized
ATD
Register
Select
Ae-Ae+m-1
Address
Lines
CPU/Bus Master
Synchronous Bus Transfer - Block Diagram (Write)
A0-Ae-1
Device
Device
Interface
R/W
Clock
Data Lines
Data in
Register
Q
Reg
Clock
n-bit (D) Register

Data
Bus
synchwriteblock.
V - 53
Computer Structure
145
Synchronous Write (Single Clock) - Ladder Diagram
Address, data
and control
CK1
Synchronous Bus Write

Single Clock
tp+ tSkew
tmargin1
Time to decode address on bus
Time to store the data
tSelect
t Store
tmargin2
New address and control
tSetup
tHold
Note: the next cycle can start sooner

than in the case of a Read.
synch4 ladder
V - 54
Computer Structure
146
Synchronous Timing - Write (Single Clock) - Timing Diagram
Write Bus Transfer

Phase 1
Clock
Slave Edge
Phase 2
Master Edge
t
tPA Skew
Valid Write Address
Address
tSelect
R/W
Address
Decoded
tStore+
tMargin2
TSetup
tHold
Data
tPD+tSkew
Reg Clock
synch4.
Note: RegClock = (R/W Clock AddressDecoded)

V - 55
Computer Structure
147

In the figure below:
Clock1 = (R/W Clock AddressDecoded)
Clock2 = RegClock = (R/W Clock AddressDecoded)
Address Decoded
R/W
Clock
Clock 1
Clock 2
clockderived.
V - 56
Computer Structure
148
Questions of Interest:
1.
Consider the two signalling scheme shown below: the one on the left is as shown in the previous notes, the one on the right
could be used. Compare and contrast the characteristics of the two schemes.
rwvsrw.
Read Cycle
Write Cycle
R/W
Option 1
Clock
/RD
/WT
Option 2
Questions
V - 56.1
Computer Structure
149
Note: Terms used in Computer Structure

Terms:
Address propagation delay (tP A ) (page 136)

Data propagation delay (tP D ) (page 136)
Bus Propagation delay (page 136)
Setup Time (tSetup ) (page 136)
Hold Time (tHold ) (page 136)
Select Time (tS or tSelect ) (page 137)
Access Time (tAccess ) (page 138)
Store Time (tStore ) (page 138)
Skew Time (tSkew ) (partial) (page 138)
Margin Time (page 138)
Questions
V - 56.1
Section VI:
Parallel Interfacing
f2014-1.0
151
Parallel Interfacing: Section Contents

Function of Parallel Interfaces (starting on page 152) The main function of the parallel interface is to provide a method to permit
the processor, or other bus master, to read (or write) data from(to) the interface in the time scale of the bus. The interface may
also provide signal conditioning and other features described in later in this section of the notes.
System Bus Side (starting on page 158) Introduces basic synchronous bus communication structure to motivate how to attach a
parallel interface to a processor.
Device-Side Alternatives (starting on page 160) Considers both unidirectional and bidirectional port alternatives however, focuses
on bidirectional issues including: control (implicit and explicit direction control), drivers (tri-state, passive pull-up (open collector),
and pseudo bidirectional), and the differences between static and dynamic applications of bidirectional ports.
Data Characteristics (starting on page 171) Characteristics of parallel data examined include: in-band and out-of-band signalling,
transient and persistent data, signalling alternatives to indicate that data is present, and de-bouncing data. Several examples of
parallel ports to support these characteristics are provided.
Event Characteristics (starting on page 179) Characteristics of events in parallel data examined include: transient vs persistent
events, how events can be stored and cleared
Questions - Short Answer (starting on page 191)
Section Contents: Parallel Interfacing
VI - 0.1
152
Function of Parallel Interfaces

(Vranesic and Zaky Sections 5.4 and 5.5)
(Hamacher Vranesic and Zaky (ECE 222) Section 4.6.1 (5th Edition))
Buffer
Time
(Synchronization)
Level
General structure
Data
Parallel
I/O
Port
R/W(Read Not Write)

CS (Chip Select)
Other Control Lines
(Eg., Address)
I/O Lines
Control/Sync Lines
System Bus Side
Device Side
File:basic.
VI - 1
153
(Optional)
Memory
Interface
Memory
Processor
Partial Address
Decoding
Electro/Mechanical
Device
Processing Domain
Device Domain
File:structure2.
VI - 2
154
Ae-Ae+m-1
(Chip) Select
or
Device Enable
Address
and
Timing
Decoder
(Centralized ATD)
Decentralized
ATD
Register
Select
Address
Lines
CPU/Bus Master
A0-Ae-1
Device
Device
Interface
R/W
Clock
Data Lines
Device Interface
Register
Data Available
in Device Interface
Q
Q
Enable
Output
Reg
Clock
Data
Bus
n-bit (D) Register

Data
Bus
synchreadwriteblock.
VI - 3
155
Structure of Parallel Interfaces
STD
Data Lines
Control
Register
STI
SFD
Status
(Register)
SFI
Data Out
Register
Subset of
Address Signals
SFD
Device Side
System Bus Side
STD
Data In
(Register?)
Register
Select
(may or may not
include
Address decode)
Bus Timing Signals
(SFD) Signals From Device

(STD) Signals To Device
(SFI) Signals From Interface
(STI) Signals To Interface
Timing
Decode
Address Decode
Not Shown and
Intended for general
Discussion only
parellelStructure.
VI - 4
156
Property
Signal Levels
Timing
Signals
Delays
System Bus Side

Processor Standards
Memory-like
RD and WR or R/W and CK
Fixed, Known
Device Side
Device Standards
Any
Any
Device Dependent
VI - 5
157

Or from a system view
File:para-a.pdf
Bus Lines
Address,
Data, and
Control
Signal Lines
Device/Interface
Device
CPU
Parallel
Interface
Synchronous or
Asynchronous
Bus Signals
Persistent Data
(until Taken)
or
Transient Data
(Limited Time)
VI - 6
158
System Bus Side

Later this term we will examine buses in detail.
General signal groups within a bus:
Data bi-directional between the processor and memory and devices.
Selection some technique is required to select which memory location or which I/O
device (address)
Control the transfers must be synchronized.
Data transfer synchronization signals (i.e. R/W, Clock, ...),
Bus control signals (I.e. Bus Request, Bus Grant ... ) and often
Processor arbitration signals (I.e. IRQ ...)
For our purposes, at this point in the course, we only need to consider the following
situation.
Assume a memory mapped I/O device (as opposed to a 2-bus structure)
Assume that the interface has more than 1 register memory mapped (assume 4)
Assume that the bus is a synchronous bus (global clock)
Assume that the timing is similar to that specified in the following figure.
System Bus Side
VI - 7
159
Sample Processor Bus

File:bus1.
Read
Write
Clock
R/W
Address
Valid Address
Valid Address
ChipSelect
Data
Invalid
Device Data
Processor Data
Interface Clocks Data Into Register

Processor clocks data from data lines
System Bus Side
VI - 8
160
Device-Side (Data) Alternatives

Unidirectional Cost/Complexity
Bi-directional Versatility
Control
Explicit (Data Direction Register)
Implicit (no Data Direction Register)
Implementation Alternatives
Passive pull-up (often implemented as Open Collector) implicit or explicit
Tri-State explicit only
Pseudo Bi-directional implicit only
Importance of changing directions.
Static: In some cases, a bi-directional port is configured infrequently (often only
during initialization) and then operates as a unidirectional port.
Dynamic: In other cases, a bi-directional port is re-configured frequently as part
of its operation.
Device-Side Alternatives
VI - 9
161
Driver Alternatives
One (Generic) Driver
Control Input
(if required)
Control Input
(if required)
Pull-Up
Switch
Pull-Down
Switch
Shared Signal Line

(multiple other drivers possible)
Higher Supply Voltage
Lower Supply Voltage
File:drivers.
Totem-Pole Driver : Both switches are active. A logic-1 is applied to the shared signal line by
closing the pull-up switch and opening the pull-up switch. In this driver one of the two switches
is always closed and as a result it is not useful on a shared signal line.
Passive Pull-up Driver : (often implemented and called open collector) Replaces the pull-up
switch with a resistor (a passive component with no control input). In this way the line can be
pulled low (for a logic-0) but a logic-1 results if no driver pulls it low.
Passive Pull-down Driver : The passive pull-down driver (open emitter) is the dual to the passive
pull-down where the Pull-down switch is replaced with a resistor.
Tri-state Driver : Both switches are active, however the logic driving the control inputs has been
modified to permit both switches to be off at the same time. When both are off the output
floats and this driver is in the hi-impedance state (sometimes called Hi-Z).
VI - 10
162
Control Signals
Address Bus
D0 D1
Unidirection (Input)
Tri-State Drivers
Tri-State Enable =
F(A15, A14, ... A1,
A0, RD/W, Ck)
Device Signals
Device Side Alternatives (Data - no synchronization shown) - Unidirectional

(Data Only) Input
Ck
Address
R/W
Address
and
timing
decoder
(ATD)
Enable
Data
File:para-uni.
File:para-uic.
Enable = Ck AddressCorrect R/W
VI - 11
163
Control Signals
Address Bus
Unidirectional (Input)
D0 D1
(Registered)
Tri-State
Discuss
Clock Source
Drivers
Tri-State Enable =
F(A15, A14, ... A1,
A0, RD/W, Ck)
Device Signals
Device Side Alternatives (Data - transient data) - Unidirectional (Data and

Event) Input
Ck
Address
R/W
Enable
Data
Data Transfer Phase
Address
and
timing
decoder
(ATD)
File:para-uni-reg.
Data
From
Device
One
version
of Event
( possible
Data
Clock)
Data Creation Phase. Event is used to indicate new data is valid
File:para-uic-reg.
VI - 12
164
Device Side Alternatives (Data - no synchronization shown) - Unidirectional

Output
Ck
D0 D1
Q
Clock
Control Signals
Address Bus
Device Signals
Unidirection (Output)
Clock = F(A15, ..
A0, R/W, Ck)
Address
and
timing
decoder
(ATD)
Address
Data
R/W
Clock 1
Clock 2
Clock Data into
I/F Register
File:para-uno. and para-uoc.
VI - 13
165
Device Side Alternatives (Data) - Explicit Bidirectional
D0 D1
Data Direction Register
D
D
Write DDR = FDDR(A15, ..

A0, R/W, Ck)
D
Tri-State Drivers
Address Bus
Control Signals
Write Data = FOUT(A15, ..

A0, R/W, Ck)
Tri-State Drivers
Device Signals
Read Data = FIN(A15, A14, ... A1,

A0, R/W, Ck)
Address
and
timing
decoder
(ATD)
File:para-exp.
VI - 14
166
Device Side Alternatives (Data transient data) - Explicit Bidirectional
D0 D1
D
Add Transient
Data

A0, R/W, Ck)
D
Tri-State Drivers
Address Bus
Control Signals

A0, R/W, Ck)
D
Tri-State Drivers
Device Signals
Data
Available
A0, R/W, Ck)
Address
and
timing
decoder
(ATD)
File:para-exp-transient.
VI - 15
167
Device Side Alternatives (Data) - Explicit Bidirectional
D0 D1
D
D

A0, R/W, Ck)
D
Tri-State Drivers
Address Bus
Control Signals

A0, R/W, Ck)
Tri-State Drivers
Device Signals

A0, R/W, Ck)
Address
and
timing
decoder
(ATD)
File:para-exp.
VI - 16
168
Device Side Alternatives (Data transient data) - Implicit Bidirectional
D0 D1
Passive
Pull-up
Drivers
Address Bus
Control Signals

A0, R/W, Ck)
Tri-State Drivers
Device Signals

A0, R/W, Ck)
Address
and
timing
decoder
(ATD)
File:para-implicit.
VI - 17
169
Passive Pull-up (Explicit Direction Control using Passive Pull-up)
File:opencoll.
One Bit of Passive Pull-up Bidirectional I/O Port

DDR
X
Data
D0
Output
Input
DDR -- Data Direction Register
Write DDR
(FDDR )
Device
I/O line
Write Data
(FOUT)
DDR = 1 X = Data, and

I/O may float and as a result
the value read may = Data
written,
DDR = 0 X = 0 and I/O
floats.
Note the value read
Power-up DDR = 0 (Only safe
state)
The signals labelled from the processor (p)

are the signals derived in previous figures.
Read Data
(FIN)
A0
A1
Register Select (part of ATD)
CS
(note: that only part

of the address is decoded)
R/W
Clock
VI - 18
170
Implicit Directional Control (Also known as pseudo bi-directional)
(NO DDR)
One Bit of
Data Bus
Write Data Register

(from mP)
File:pseudob1.
D
DOWN
/DATA
IO line
Read Data Port

(from mP)
The signals labelled from the processor (mp)

are the signals derived in previous figures.
DOW N = DAT A ... if DAT A =

0 then the I/O line is driven low.
Note: DATA refers to the value
stored in the D flip-flop.
If DAT A = 1 then the I/O line
floats high.
To read a value from a device attached to the I/O line, DAT A must
be set to 1 previously.
Note: No DDR
Note: Similar to passive pull-up
(open collector).
VI - 19
171
Data Characteristics
Whenever two systems communicate there is a question as to how data can be passed from one
domain to the other. This transfer may include:
Signal Translation (light electrical, or 5 V 3 V, or 5 V 10 mA)
Synchronization. When is the data to be read or written?
Consider the following dimensions to the problem.
Data may be
Persistent I.e. it will remain/must remain valid until the customer explicitly accepts
the data. As described in the synchronization section of these notes. (starting on
page 66)
Transient: I.e. the data will vanish if not read at the appropriate time.
The source of the data may either inform or not inform the receiver that the data is
present.
The receiver may (or may not) request new data when it is ready for the data.
VI - 20
172
Control Signalling
There are two general techniques to pass control information between two entities.
In-Band : Some (or all) of the control information is passed in the same way that
the data is transferred. For example, a control-C in a text string looks like data,
but in some cases may be interpreted as a control character with a special operation
characteristic.
Out-of-Band : The control signalling is done using techniques that cannot be confused
with data. For example, there may be signals at a frequency not found in the data,
or there may be values on the data lines that cannot ever be data, or there may be
extra signal lines to indicate some control information.
VI - 21
173
Signalling of Data Changes

In this particular case the control information to be considered is to detect/signal that
there is a new data value to be read from the parallel port. For example, how to tell the
difference between two values of 0x76 and one value of 0x76 that has not yet changed.
Using the In-Band approach. The only indication that there has been a change is
the fact that the value on the data lines is different than it was previously (Eg., a
different key has been pushed). This would require very special operating specifications. One alternative, from among many, would be to insert a special value between
all consecutive values.
Using the Out-of-Band approach, the most straightforward alternative would be to
use an extra signal line to indicate that new data is available.
VI - 22
174
Persistence of Data
Consider the persistence from the perspective of the receiver of the data.
Persistent data may be accepted at the convenience of the receiver. Once the change has
been detected, then after the data has been accepted the source is informed that the value
is no longer needed.
Transient data must be accepted within a time specified by the source after its presence
is signalled. This could be done with a latch at the receiver.
Time
Persistent data
Transient Data
Valid Data
Valid Data
Known
(specified)
time
File:datatype.
VI - 23
175
Persistence of Data (cont.)

How might you handle persistent data? (fully interlocked, out-of-band signalling)
File:persist.
Valid
Accept
CR
SR
Accept
Parallel Interface
(CPU as the
Customer)
Valid
Timer
Data
Counter
Data
//One way to get this signalling

LOOP:
TST SR
BEQ LOOP
MOVE DATA, R0
MOVE #1, CR
LOOP1: TST SR
BNE LOOP1
MOVE #0 CR
Device Registers
VI - 24
176

How might you handle transient data? (out-of-band signalling shown below.)
File:para-tra.
Control
Data
Edge
Detect
Register
Data
Available
Data
VI - 25
177
It may also
be
noisy
(bounce)
The SPDT
solution
assumes
that
the
switch will
not bounce
from one
throw
to
the other.
It bounces
on
and
off of one
throw at a
time.
File:switchdebounce.
SPST (Single Pole Single Throw) SPDT (Single Pole Double Throw)
Q
B
Milliseconds
A
B
C
Switch Starts to change state
Q
VI - 26
178
De-bounce Options
Software: unknown duration of bounce (assume limit, act After stable)
Hardware: counter or shift register (clock to sample etc.) or more expensive switch and
RS latch.
VI - 27
179
Synchronization Control Line Issues

NOTE: There are additional notes on this material available on the uWaterloo
Desire2Learn site for the course in the lecture section. Please review those notes.
Input Synchronization:
How to inform CPU
Interrupt
Polling
Function:
Inform CPU only
Clock Data
Active Edge
When to reset Status bit.
Output Synchronization
When to set bit/signal
CPU only
As a side effect of some external event
When to reset bit/signal (as above).
Event Characteristics
VI - 28
180
When/How to inform CPU.
VI - 28
181
Events and Parallel Interfaces

EventTypes.
Transient Events
Persistent Events
E3
E1
E3Ack
E2
Event
Occurs
Event
Used/Consumed
The signal from the event producer

may resemble either E1 or E2
Event
Occurs
Event
Used/
Consumed
E3 signals even happens and E3Ack indicates
Event has been consumed.
Transient Event Persistent Event

Transient Data
Persistent Data
VI - 29
182
Transient Event Implementation

Transientevent.
Event
Ck
Occured
(rising edge) Asynchronous
Clear
Stable value
indicating that
the event has
happened
Event
Consumed
To Event Consumer
From Event Producer
Transient Event Processing
VI - 30
183
Events and Control Register Values

a processor can set and clear bits in a control register explicitly.
these bits could be interpreted as an event from the processor to some device.
VI - 31
184
Events and Status Bits

Transientevent.
Event
Ck
Occured
(rising edge) Asynchronous
Clear
Explicit Clear
Stable value
indicating that
the event has
happened
Event
Consumed
To Event Consumer
From Event Producer
Transient Event Processing
Implicit Clear
VI - 32
185
Note: Data Only Transfers

Data Only Input Transfer (SPST Switches)
SW0
dataonlyinput.
Enable when DataRegister's

Address detected and correct
Read Time
no time constraints, no events.

possible concern regarding switch debouncing
MOVE DATA, R0
Processor
I/O Bus
SW7
Data Only Transfer (Input)

(No Storage at Interface)
VI - 32.1
186
Note: Data Only Transfers

Data Only Output Transfer (LEDs)
dataonlyoutput.

Write Time
(Regclock FIN)
Q0
again, no time, no events, no notification of

changes
MOVE R0, DATA
LED Display
Q
Processor
I/O Bus
Q1
Data Only Transfer (Output)
(Storage at Interface)
VI - 32.2
187
Note: Event Only Transfers -Explicitly clear status bit

Event Only, CPU Explicit Reset
eventonlycpu.
Control Register's
Address Detected and
Write Time
once the program detects the event it will then

write a 1 into one bit into the control register
and then write a 0 in to the same control bit.
Note: The CPU (and other

device interfaces drive the data lines)
One bit of Control

Register
Asynchronous
Reset
1
D
Event Occurs
Clock
Status Register's
Address Detected and
Read Time
Processor
newEVENT
Data Bus
One bit of Status Register
Event Only Transfer, explicit

CPU Reset.
VI - 32.3
188
Note: Data and Event Transfers, Transient Data, implicit status bit clearing
Data and event, transient data, capture most recent

data dataeventinputtransient.
Register holds transient
Read Time
input data in this case
the data changes every clock pulse
(on the rising edge)
Data from sensor
dataeventinputtransientTimingDiagram.
Data
Data 1
Data 2
Event
Event
(Data Available)
In this case the figure illustrates implicit clearing of the status bit when the data is read. This
could also be implemented as an explicit clearing.
NewData
Processor
I/O Bus
OverRun
Reset Implicitly
(automatically) when
datais read
Asynchronous
Reset
1
D
Q
Clock
Status bit
indicating fresh
data is available
(could be used
for polling or
interrupt)
VI - 32.4
189
Note: Data and Event, Transient Data Transfers

Data and event, transient data, capture first data
dataeventinputtransientfirst.
Read Time
D a ta from s e ns or
Register holds transient

the data changes on the first clock pulse
after the previous event has been serviced
Event
(Data Available)
In this case there is consideration for what happens when a second event occurs before the first
event (data) has been processed.
There are various options available to the designer such as:
always keep the first event (as shown) or
always keep the newest event (not
shown)
Processor
I/O Bus
Once the first value is loaded,
later clock pulses are ignored
until the status bit is cleared
Reset either by CPU or
Automatically when
Asynchronous
data is read
Reset
READ
1
Status
D
Q
Clock
Clock
NewData status
bit indicating fresh
data is available
(could be used for
polling or IRQ)
READ
Status
Q
OverRun status
bit indicating that
new event occured
while previous event not
consumed
VI - 32.5
190
Note: Data and Event Transfers, Persistent Signals

Data and event, persistent data, capture most recent
data. In this case there is a register (not always needed
for persistent data, but in this case it is the persistent
hand-shake signals that are the focus.
dataeventinputpersistent.
Data from sensor

Register holds persistent
Read Time
the data changes every clock pulse
Processor
I/O Bus
Reset either by CPU or

Automatically when data
is read
Asynchronous
Reset
Event
(Data Available)
D
Q
Clock
Data Accepted
Status bit
indicating fresh
data is available
(could be used
for polling or
interrupt)
VI - 32.6
191
Questions of Interest: Short Answer

Possible short answer question prototypes. These prototypes do not have any of the exam sugar coating. They simply raise some
issues to give you suggestions on areas of interest.
1.
Terms that have been defined (not an exhaustive list) include: buffering time and level, implicit data direction control, explicit
data direction control, static and dynamic bidirectional port operation, data direction register, persistent and transient data,
in-band and out-of-band signalling, and input and output synchronization. You may be asked to define or explain these terms
or compare and contrast similar (or dis-similar) terms.
2.
For the switches shown in the figure below, show how to interface each of them to a parallel port and how you would read
SPST
the switch (pseudo code). Consider how to handle bounces in the hardware and the software in each case.
3.
SPDT
For the LED shown below, indicate how to attach it to an implicit (passive pull-up) parallel port. (Again, show code, including
5V
R
initialization.)
Questions - Short Answer
VI - 32.1
192
Questions of Interest: Engineering

One popular style of question is the engineering question. This question specifies a choice and asks you to explain when each side of
the choice would be relevant. Examples follow (with structures of answers)
1.
Consider the choice between implicit and explicit data direction control. (when would each be appropriate?) Your answer
should include the following issues.
A quick summary of each alternative (from the design perspective)
A summary of how a user would use this in a hardware sense. You should be able to provide sample drawings of
various attached devices.
A summary of how a user would use this in a software sense. You should be able to provide sample pseudo-code to
operate various attached devices.
One (preferably more) insightful comments, supported by your previous answers and example applications.
2.
Consider the choice between an implementation with persistent or transient data. (Same points should be in your answer.)
3.
Consider the choice between in-band and out-of-band signalling. (Similar points,)
VI - 32.2
193
Questions of Interest: Detailed

For the 4-by-4 switch shown below, use an implicit eight-bit bidirectional passive pull-up parallel port to attach to the switch. Write
the pseudo code necessary to interface to this unit. (Show all the components required to attach the switch. Note: there are no
pull-up resistors in the parallel port.) Assume that the goal is to determine which switch (numbered from 0 to 0xF), if any, is pressed.
VI - 32.3
194
Questions of Interest: Less Structured

Consider the device shown in the figure below. It could be used as either an input or as an output device. Assume that 10 mA are
required to light the LED and that an implicit bidirectional parallel port is to be used to attach to the device. Show how to attach
(and use) this device so that the led can be on or off at the control of the program if the switch is open. The processor is also
expected to respond within 1 ms of the button being pressed. Show the circuit and the pseudo code to accomplish this task.
5V
R
VI - 32.4
195
Note: Terms used in Parallel Interfacing

Terms:
Totem-Pole Driver (page 161)

Passive Pull-up Driver (page 161)
Passive Pull-down Driver (page 161)
Tri-state Driver (page 161)
In-Band (page 172)
Out-of-Band (page 172)
VI - 32.7
Section VII:
Error Detection and Correction
f2014-1.0
197
Error Detection and Correction: Section Contents

Error Handling Introduction (starting on page 199) The error environment, the general methods for dealing with some errors
(detection and/or correction), the limitations to error handling new, and an introduction to data words and code words.
Parity (starting on page 206) The most basic (and common) of the error detection techniques parity sends one additional bit per
data word to permit single bit errors to be detected.
EC, ED and Distance (starting on page 208) The relationship between error detection (ED) and error correction (EC) is examined.
The distance between words is defined and used as a measure to compare error correction and detection needs.
Hamming Code (starting on page 210) One of the standard single bit error correction techniques, Hamming code, is introduced
through a small example. The constraints and costs associated with Hamming code is examined and the effects on efficiency when
longer code words are used is also considered.
Hamming Code Implementation (starting on page 220) The issues associated with implementation for larger words is also examined.
Section Contents: Error Detection and Correction
VII - 0.1
198
Error Handling Resources

John F. Wakerly, Digital Design, Principles and Practices, Prentice Hall, 1994, pp 53 67. (On
reserve in Davis Centre library.) Go to this page and select Course Reserves and then search for
ECE 224 or MTE 325 for a list or search for your instructor.
The most likely resource need will be for the material on error correcting codes. (Hamming code
in these notes). There are many sources available on the internet.
Resources
VII - 1
199
Transfer Errors in Digital Systems

Errors (may) occur in any environment where data is transferred from one unit to another.
Buses
Memory
Serial/Parallel Channels
CPU to Memory and back to CPU, an error may have occurred during the actual bus
transaction, or at the storage location.
Types of errors
Hard Errors: permanent error (Eg. a memory bit stuck at some value)
Soft Errors: transient errors (Eg. the 4th bit of a transmission failed ... the error
may not repeat)
Error Handling Introduction
VII - 2
200
Communication Structure
channel.
Data
Source
Data Transfer
(with noise?)
Data
Destination
Goals of Error Detection and Error Correction

Error Detection(ED): Given information to be transferred, sufficient (redundant) information is added (at the data source) to make it possible to determine (at the data
destination) that the received data is not the same as the original information.
Error Correction(EC): Given information to be transferred, sufficient (redundant)
information is added (at the data source) to make it possible to recover (at the data
destination) the original information.
The received may be: correct; incorrect, but correctable; incorrect but detectably received
in error; or incorrect but not able to detect or correct the error(s).
VII - 3
201
Issues and More Terminology

Error rates and the overhead to detect the error are two issues to be considered.
Error Rate: The rate of errors on the channel. This may be specified as a probability.
For example, 106 indicates that, on average, one bit in a million is in error. The
errors may (or may not) be correlated. (I.e., the occurrence of an error may increase
the likelihood that the next bit will be in error.)
Overhead : For our purposes we define overhead as the number of non-data bits
divided by the total number of bits transferred.
Block recovery vs Byte/Word recovery.
If recovery is at the smallest unit level (Eg., byte level), the system may be very
responsive the fewest bits to re-transmit, but there may be many extra bits to
transmit.
If recovery is done on a large group of bits a re-transmission requires the entire
group to be resent, but the number of bits transmitted in the initial transmission is
smaller.
In this context, a block of information may be treated as a group of bits for error
handling.
VII - 4
202
Data Words and Code Words

Let B be the number of bits of data and C be the number of check bits required to handle
the errors (correction or detection at the required level).
Data Word: The information bits that are to be transferred over a channel. In this case
the data word has B bits of data. The data word is the smallest unit for error correction
or detection.
Code Word: The combination of the B bits of data and the C bits of error handling bits.
Thus the number of bits actually transmitted is B + C bits. As a result the overhead is
OV ERHEAD =
C
B+C
In the event of an uncorrectable error all B + C bits must be retransmitted.
VII - 5
203
Communication Structure
Consider a system with B bits of data and C check bits for correction.
Correct
Data word
(B Bits)
Data
Channel
CRec
Det/Cor
Channel
Data
Out
B Bits
CCalc
Compare
Data In (B Bits)
Code word
(B+C Bits)
Error
Detected
C Check Bits
F is the function to calculate the C check bits.
general.
VII - 6
204
Communication Structure Interpretation

If F (Bin) == F (BOut) there has been no error (or at least no detectable error)
If F (Bin) 6= F (BOut) then
F may detect only (ED) or
F may provide sufficient information to correct some errors (EC) or
F may provide sufficient information to correct some errors and detect others (ECED).
VII - 7
205
Limitations of Error Detection and Correction

Some errors can be neither detected nor corrected.
Errors could convert a valid code word into a different code word and thus the (erroneous)
received data would be indistinguishable from an error-free reception of the other code
word. This could result if the correction/detection design was built on an assumption of
a single bit error but there were multiple bits in error.
An error could convert an valid code word into an erroneous code word that would then
be corrected into an invalid code word. As above this could be as a result of more bits in
error than permitted in the design.
There could be timing or signalling errors that prevent recovery of sufficient information
to recover from an error event.
VII - 8
206
Parity
The most common first level of defense. (C = 1)
Add 1 bit per B bits so that the B + 1 bits always have
an even number of bits set to a 1 value (even parity)
an odd number of bits set to a 1 value (odd parity).
Detects single bit errors.
The minimum distance between valid code words is 2.
Distance: The minimum number of bits that must change to go from one code word
to another code word
.
Note: to detect single bit errors requires a distance of at least 2.
Parity
VII - 9
207
Parity
Consider a 3-bit data word (plus 1 bit of parity) (bbbc){Assume Even Parity in this case}
Word Valid? Word Valid?

0000
1000
0001
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
1110
0111
1111
Parity
0001
0000
0100
1001
1000
1011
1010
1110
1111
0011
0010
0110
0111
1100
0101
1101
distance2.
VII - 10
208
Distance and EC vs ED
distance3.
Correct Code
Word
Word with
Error
Effect of 1 bit
error (distance 1)
EC, ED and Distance
VII - 11
209
Distance and EC vs ED
distance3a.
EC-ED
ED Only
0-1 1
1-1
1-2
2-2
Correct Code Word

Word with Error
Effect of 1 bit error
(distance 1)
EC, ED and Distance
VII - 12
210
Hamming Code
(See Wakerly)
Consider the case of B = 4.
Consider the example on the next two pages.
There are 3 sets (P, Q, and R).
Each set includes 1 check bit (thus there are 3 check bits for 4 bits of data in this case)
Each check bit is set so that the combination of the data and check bits in the set has an
even number of 1s (i.e. each set has even parity).
For any received/read value each set could have either Even or Odd parity.
Thus there are 23 1 code words that indicate a single bit error and
Only 1 correct code word. (P, Q, and R all have even parity at the receiver).
Hamming Code
VII - 13
211
Hamming Code
Calculate the Check

Bit for each set.
Set Q
Set P
Set P (4 bits on)
Set Q (2 bits
1
1 1 0
Data Word = 1110
Set R
Set R (2 bits on)

Data Word = 1110
Each of the sets has even parity

Data = 1110
Check = 100
venn1.
Hamming Code
VII - 14
212
Note: Bit Placement in Previous Example

In the previous example the data and check bits have been included in a very specific combination of locations. Later in this set of
notes (See Hamming Code Implementation (starting on page 220) ) an algorithmic method of placement is described. For now, note
the following placement characteristics:
Each bit is located in a unique combination of sets.
each check bit is in exactly one set. (C0 is in set R C1 is in set Q and C2 is in set P)
the data bits are in two or three sets. ( D0 is in sets Q and R, D1 is in sets P and Q, D2 is in sets P and R, and D3
is in sets P and Q and R)
Hamming Code
VII - 14.1
213
Possible Error Conditions
Set Q
Set P
Assume that the Data bits

and check/parity bits are
arranged as shown in the
figure. Note: the bit layout is arbitrary in this discussion.
CP
Data Word = 1110
1
D1
1
D
1 3 0
D2
D0
CQ
CR
Set R
venn0.
If the 7 bits shown in the figure above were to be transmitted, and we assume that there
is (at most) 1 bit with an erroneous value, the table on the next page lists the parity for
the 3 sets of values at the receiver.
Hamming Code
VII - 15
214
Possible Error Conditions
Received Parity
Bit In Error Set P Set Q Set R
CP
Odd
Even
Even
CQ
Even
Odd
Even
CR
Even
Even
Odd
D0
Even
Odd
Odd
D1
Odd
Odd
Even
D2
Odd
Even
Odd
D3
Odd
Odd
Odd
None
Even
Even
Even
Hamming Code
VII - 16
215
Note: Possible Error Conditions Interpretation

If we assume that we have a circuit that will generate
a 0 if there is no error and a 1 if there is an error.
Noting that the previous table used even parity so that
a received odd parity is an error the table becomes the
following.
Received Parity
Bit In Error
Set P
Set Q
Set R
CP
CQ
CR
D0
In other words, the number formed by these 0s and 1s

is a number which can be interpreted to indicate which
of the bits is in error. If we transmit the data in the
correct order, then this can also be the number of bit
received that is incorrect. (As shown in the reordered
table below.)
Received Parity
Bit In Error
Set P
Set Q
Set R
None
CR
CQ
D1
D0
D2
CP
D3
D2
None
D1
D3
Hamming Code
VII - 16.1
216
Example: An Error in D2
As Received
As Corrected
Set Q
Set P
1
1
Odd
0
Data Word = 1110
0
Even
Even
Error in 1 Data bit
0
Odd
Set Q
Set P
Set R
Parity errors in
Set P and R
(only 1 bit in common)
--- Correct it
venn2received.
Hamming Code
Data Word = 1110

Even
Even
0
Set R
Data = 1110
Check = 100
venn2corrected.
VII - 17
217
Code Word Size

What is the minimum length of the code word for B bits of data?
Given C bits of check information, there are 2C 1 error representations (in the C bits)
and 1 correct representation.
Thus to correct 1 incorrect bit out of B + C bits of information, requires that
2C 1 B + C
Hamming Code
VII - 18
218
Maximum Word Length vs Number of Check Bits

checkbitschart.
Check Bits vs (Max) Data Bits

2500
Maximum Number of Data Bits
2036
2000
1500
1013
1000
502
500
11
26
57
120
247
10
11
Number of Check Bits and Max Number Data Bits
Hamming Code
VII - 19
219
Code Word Size Typical Values

The table shows the value of C that is required to correct single bit errors for some common B
values.
C
3
4
5
6
7
C + B 2C 1
3 + B 23 1
4 + B 15
5 + B 31
6 + B 63
7 + B 127
Hamming Code
B
4
8
16
32
64
Overhead for B
43 % (3/7)
33 % (4/12)
24 % (5/21)
16 % (6/38)
10 % (7/71)
VII - 20
220
Hamming Code Implementation

Although the set explanation may be intuitive, one must consider a systematic implementation
Which bits should be associated with which parity bits to simplify coding and decoding?
Assume that the bits are numbered 1 i B + C
NOTE the 1.
C bits generated based on the data
CCalc
B data bits
C bits read from channel
CRec
ceiling(log2(B+C+1))
bits indicating the
location of the error
syndrom1.
VII - 21
221

Syndrome: Combine the values of C Calc and C Rec to indicate the presence of and the location
of an error in a received code word
The ith bit of the syndrome (Si) is
CiRec
CiCalc
Si =
for 1 i C
If S = 0 (i.e., the syndrome has zero 1s)
then the code is correct (CiRec = CiCalci)
If S has only one 1 then the error is in a
check bit
If S has more than one 1 then the number
represented is the bit in error.
One way to accomplish this is the following:
place the check bits at positions:
20, 21, 22, ...2C1
and data bits everywhere else.
then associate
Check Code Bits

Bit
(in
global
posit.)
20
1, 3, 5, 7, ...
21
22
23
2j
Remark
All the bits
with
20 = 1 in numerical rep.
2, 3, 6, 7..
21 = 1 in numerical rep.
4, 5, 6, 7, 12.. 22 = 1 in numerical rep.
8..15, 24..31, ... 23 = 1 in numerical rep.
See
Ques- 2j = 1 in nutions (start- merical rep.
ing on page
227)
VII - 22
222
Return to Example and Syndrome Calculation
CPT ransmitted
CPT ransmitted
CQT ransmitted
CQT ransmitted
CRT ransmitted
CRT ransmitted
=
=
=
=
=
=
D1 D2 D3
111=1
D0 D1 D3
011=0
D0 D2 D3
011=0
Set Q
Set P
CP
Data Word = 1110
1
D1
1
D
1 3 0
D2
D0
CQ
CR
Set R
venn0.
VII - 23
223
Return to Example and Syndrome Calculation

Assume that D2 is received in error.
CPRec
CPRec
CQRec
CPRec
CRRec
CPRec
=
=
=
=
=
=
CPT ransmitted
1
CQT ransmitted
0
CRT ransmitted
0
CPCalc
CPCalc
CQCalc
CQCalc
CRCalc
CRCalc
=
=
=
=
=
=
D1 D2 D3
101=0
D0 D1 D3
011=0
D0 D2 D3
001=1
Syndrome = C Rec C Calc

= 100 001
= 101
If the fifth bit were D2 then the syndrome would indicate which bit to change.
VII - 24
224

Consider the specific case when B = 8 and C = 4.
Overall Bit (Binary)
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
10
1010
11
1011
12
1100
Data Check
C0
C1
D0
C2
D1
D2
D3
C3
D4
D5
D6
D7
C0
C1
C2
C3
=
=
=
=
D0 D1 D3 D4 D6
D0 D2 D3 D5 D6
D1 D2 D3 D7
D4 D5 D6 D7
VII - 25
225
Example
Data in (D7...D0) = 0 0 1 1 1 0 0 1
Check Bits (C3,C2,C1,C0) = 0 1 1 1
Bit
D7
D6
D5
D4
Data Out
Check Out
C3
D3
D2
D1
C2
D0
C1
C0
1
1
Sent
Received
VII - 26
226
Example of an SEC (Single Error Correcting Code)

S0 =
=
=
=
S1 =
=
=
=
S2 =
=
=
=
S3 =
=
=
=
C0Rec C0Calc
1 D0 D1 D3 D4 D6
110110
0
C1Rec C1Calc
1 D0 D2 D3 D5 D6
111110
1
C2Rec C2Calc
1 D1 D2 D3 D7
10110
1
C3Rec C3Calc
0 D4 D5 D6 D7
01100
0
Syndrome = S3S2S1S0 = 0110 = 6, therefore bit 6 (D2) is wrong!
VII - 27
227
Questions of Interest: Error Correction
Terms used in this section: Hard Failures, Soft Failures, Overhead, Error Detection, Error Correction, Data Word, Code
Word, Distance and Syndrome.
Specific examples of Hamming coding would be worth considering. Possible examples include:
Given a number of bits in a data word, how many check bits would be needed?
For a given data word and coding scheme what are the values for the check bits?
For a given received pattern if there is an error, which bits are in error?
For the entry in the table for the code bit positions (starting on page 221) for the check bits, derive an expression
for code bits to be included in the calculations for Check bit C j .
Engineering Questions (See questions at the end of the parallel port section for the types of points to include in your
consideration.)
When are additional check bits justified? Eg., given x data bits when is it reasonable to add check bits? When is it
unreasonable?
How might you determine how many blocks to split x bits into for transmission. (Use material from your probability
course.)
VII - 27.1
228
Note: Terms in Error Detection and Correction Section

Terms:
Hard Errors (page 199)

Soft Errors (page 199)
Error Detection(ED) (page 200)
Error Correction(EC) (page 200)
Error Rate (page 201)
Overhead (page 201)
Data Word (page 202)
Code Word (page 202)
Distance (page 206)
Syndrome (page 221)
VII - 27.1
Section VIII:
Serial Interfacing
f2014-1.0
Serial Interfacing
230
Serial Interfacing: Section Contents

Serial Interfacing Introduction (starting on page 231) The issues associated with serial interfacing such as the types of synchronization, are introduced.
Terminology (starting on page 234) Link types (simplex, half-duplex and full duplex), types of synchronization (bit, byte and clock)
are described, bit-rate and baud-rate, and types of coding schemes.
Character-Oriented Serial Interfaces (starting on page 242) Examines the structure of character-oriented serial interfaces. The
material focuses on: the transmit and receive register structure, the interface with the system bus, The issues associated with
clocking (for example when to clock the data into the shift register), and the register structure in the interface.
Protocols and Standards (starting on page 252) The scope of a protocol and a communication standard are examined. There is also
a brief summary of the types of standards.
Asynchronous Protocols (starting on page 255) Asynchronous character-oriented serial communication is described in detail. Topic
emphasized: clocking issues, phase detection, clocking errors, other errors (framing, parity, overrun) and special characters such as
a break
Synchronous Protocols (starting on page 270) Introduces synchronous, block-oriented, protocol structures.
Synchronous Serial Communication (starting on page 273) Describes synchronous, block-oriented, serial port structures. Examines
two synchronous communication protocols (HDLC and BISYNC).
Universal Serial Bus (USB) (starting on page 295) The USB (Universal Serial Bus) structure is examined. Signalling issues such as
bit-stuffing, NRZI signalling, and packet-oriented transfers are also discussed.
Using RS 232 Communications Standard (starting on page 309) The RS-232 standard connections are introduced and the need (and
functionality) of a null-modem is examined.
Section Contents: Serial Interfacing
VIII - 0.1
Serial Interfacing
231
Serial Interfacing Resources

Vranesic and Zaky, Microcomputer Structures, Chapter 5 (5.0 5.3), Chapter 11.4 (VZ)
Hamacher, Vranesic and Zaky, Computer Organization, McGraw-Hill, 5th Ed. (RS-232)
Chapter 10.3 (HVZ)
Stone, Microcomputer Interfacing, Addison-Wesley, Chapter 5
Wakerly (John Wakerly, Digital Design, Principles and Practices, Prentice-Hall, 1994, pp
53-67)
J.W. Valvano, Embedded Microcomputer Systems: Real Time Interfacing, Chapter 7 and
Section 14.5
Tanenbaum, Andrew S., Computer Networks N.J., Prentice Hall PTR, 1996. (HDLC in
particular)
Serial Interfacing Introduction
VIII - 1
Serial Interfacing
232
Serial Interfacing Motivation

Topic Map
serialrange.
Computer
Computer
Channel
I/F
I/F
Range of Serial Topics

Why Serial?
least complex electrical interface between digital devices
use a single wire (plus ground) to carry information one symbol (one bit in the simplest
case) at a time.
VIII - 2
Serial Interfacing
233
Communication Context
context
Context
Information (Variable size: perhaps a file)
Which is composed of many

Packets
Data and Header
Data and Header
Frames Frame (formatted for communication)
Frame (formatted for communication)
Which is composed of many

Byte
Block Synchronization Required

Byte
Byte Synchronization Required

Bits
Bit Synchronization Required
Logic Values on wires
Analog Signals
VIII - 3
Serial Interfacing
234
Channels
Simplex: unidirectional as shown below
Half Duplex: bidirectional, one-way at a time, as shown below
Full Duplex: simultaneous bidirectional, as shown below
duplexing.
Tx
(Transmitter)
Rx
(Receiver)
Channel
(implementation
unspecified)
Simplex
Terminology
Tx
Rx
Distributed
Direction
Control
Channel
(implementation
unspecified)
Half Duplex
Rx
Tx
Tx
Rx
Rx
Channel
(implementation
Tx
unspecified)
Full Duplex
VIII - 4
Serial Interfacing
235
Classes of Synchronization
Bit Synchronization: How long is each bit? and Where do bits start (or stop)?
These two components may be considered separately.
Bit Rate Synchronization: The time that elapses between the start of one bit and
the start of the next bit.
Phase Synchronization: Given that the rate is known, how is the mid-point (or start)
of each (or any) bit found. This amounts to determining the phase relationship
between the local clock and the clock used to transmit the data originally.
Byte Synchronization: Where do bytes start and stop?
Block Synchronization: Where do blocks start and stop?
Terminology
VIII - 5
Serial Interfacing
236
Bit Synchronization
Given an input signal as shown below:
Time
synch1.
How many bits are represented? Unknown

What are their values? Unknown
What do they mean? Unknown
Terminology
VIII - 6
Serial Interfacing
237
Bit Synchronization (Cont.)

Given an input signal and a clock as shown below: (The clock provides one way to get the bit
timing. In this case, one edge of each clock period is used to sample the data line.)
Clock
Data
synch2.
How many bits are represented? 8

What are their values? Unknown (Phase Synchronization required.)
rising edge? 01101110
falling edge? 11111100
select edge to sample at the most correct time (if possible).
Terminology
VIII - 7
Serial Interfacing
238
Bit Synchronization (Cont.)

Given an input signal and a clock as shown below: The clock provides one way to get the bit
timing, if we assume rising edge then bit synchronization has been attained and the bits can be
reliably interpreted. 16, 0110111001101010
Clock
Data
synch3.

where does a byte start?
if one byte is read the following values are read depending one where the first bit is
assumed to be located Bit 1 Hex(6e), Bit 2 Hex(dc), Bit 3 Hex(b9) Bit 4 Hex(73)
etc.
need a convention to find the start of a byte.
Terminology
VIII - 8
Serial Interfacing
239
Byte Synchronization
Given an input signal and a clock as shown below: The clock provides one way to get the
bit timing, if we assume rising edge then bit synchronization has been attained and the bits
can be reliably interpreted. 16, 0110111001101010 Further assume that by convention
synchronization information permits bytes to be detected 0xB9, 0xA9
16-bits of interest
Byte
Clock
Bit
Clock
Data
1011 1001 1010 1001

synch4.
What do the bytes mean? Unknown

what do they mean: ASCII (American Standard Code for Information Interchange)?
Part of a block? ...
Terminology
VIII - 9
Serial Interfacing
240
Terminology
Bit per second (Bit Rate) vs Baud (or Baud Rate).
Bit Rate: The number of bits that can be transferred per second over a channel.
Baud Rate: The maximum number of symbols that can be transferred per second over a channel.
Consider the following figure
Clock
Bit
Data
Bit
Read
4 Value
Data
Value
Read
bitbaud
Terminology
VIII - 10
Serial Interfacing
241
Implementation Issues - Data Representation as Electrical Signals
serial13.
1
On/Off
NRZ
Bipolar
RZ (Return to Zero)
(Split Phase) Manchester
Min. 1 edge per bit (middle)
Clock Recovery easy
Differential Encoding
Edge means 0
No edge means 1
Data can be interpreted
even if it is inverted
Note: Coding schemes that

do not have a zero rest point
are referred to as an NRZ
(Non-Return-to-Zero) code.
One could characterize on parameters such as: Ease of design, the presence of a DC
component, use of bandwidth
and synchronization possibilities.
(Also in Wakerly)
NRZI (Inverted or Interval)

Edge means 1,
No Edge means 0
Terminology
VIII - 11
Serial Interfacing
242
CS
Address
Decoder (ATD)
A0, A1
Address Lines
One-Byte Serial Interface Transmit
Address and
Synchronization
Signals
R/W
CS Chip Select
RCV Receive Register
XMIT Transmit Register
SR Shift Register
Int Req Interrupt Request
System Bus
Data Bus
Int REQ
Interface
Register
Selection
8
8
e.g.,
TXReady
STATUS
CONTROL
RCV
XMIT
SRin
SRout
Local
Osc.
May Jumper to
one or both
clocks
Serial Data in
Rx Clock
Serial Data Out
Tx Clock
Virtually the same as

a parallel port with
one input and one
output 8-bit port.
serial1.
Shift registers are used to convert between serial and parallel data streams.
Character-Oriented Serial Interfaces
VIII - 12
Serial Interfacing
243
Note: One-Byte Serial Interface Transmit Comments

Data is loaded into XMIT (Transmit) register (in parallel) from the system bus.
When SRout (I.e. the Output Shift Register) is idle, data is transferred from XMIT to SRout (in parallel)
Data is shifted out serially by the Tx (Transmit) clock.
In the figures below, two alternatives for the transmit clock are shown.
CS
Synchronous
serial1ta.
serial1tb.
R/W
A0, A1
Address Lines
Address and
Synchronization
Signals
System Bus
Data Bus
Int REQ
CS
Interface
Register
Selection
RCV
System Bus
Data Bus
XMIT
SRin
SRout
Int REQ
Interface
Local
Osc.
Address and
Synchronization
Signals
R/W
Register
Selection
CONTROL
STATUS
Address
Decoder (ATD)
Asynchronous
Address
Decoder (ATD)
A0, A1
Address Lines
Serial Data in
Rx Clock
Serial Data Out
Tx Clock
Tx Clock from free-running local oscillator
8
8
STATUS
Local
Osc.
CONTROL
RCV
XMIT
Serial Data in
Rx Clock
SRin
Serial Data Out
SRout
Tx Clock
Tx Clock Received from the Data Destination or other

External Source
VIII - 12.1
Serial Interfacing
244
CS
Address
Decoder (ATD)
A0, A1
Address Lines
One-Byte Serial Interface Receive
Address and
Synchronization
Signals
R/W
CS Chip Select
RCV Receive Register
XMIT Transmit Register
SR Shift Register
Int Req Interrupt Request
System Bus
Data Bus
Int REQ
Interface
Register
Selection
8
8
e.g.,
TXReady
STATUS
CONTROL
RCV
XMIT
SRin
SRout
Local
Osc.
May Jumper to
one or both
clocks
Serial Data in
Rx Clock
Serial Data Out
Tx Clock
Virtually the same as

a parallel port with
one input and one
output 8-bit port.
serial1.
VIII - 13
Serial Interfacing
245
Note: One-Byte Serial Interface Receive Comments

Data is shifted into SRin (Input Shift Register) serially by the Rx (Receiver) Clock.
when SRin is full data is transferred into the RCV (Receive) register (in parallel)
Data is transferred (in parallel) to the system bus.
In the figures below, two alternatives for the receive clock are shown.
CS
Synchronous
serial1ra.
serial1rb.
R/W
A0, A1
Address Lines
Address and
Synchronization
Signals
System Bus
Data Bus
Int REQ
CS
8
8
STATUS
XMIT
R/W
System Bus
Data Bus
Register
Selection
Local
Osc.
CONTROL
RCV
Address and
Synchronization
Signals
Int REQ
Interface
Interface
Register
Selection
Address
Decoder (ATD)
Asynchronous
Address
Decoder (ATD)
A0, A1
Address Lines
SRin
SRout
Serial Data in
Rx Clock
Serial Data Out
Tx Clock
Rx Clock from free-running local oscillator
STATUS
Local
Osc.
CONTROL
RCV
XMIT
Serial Data in
Rx Clock
SRin
Serial Data Out
SRout
Tx Clock
Rx Clock Received from the Data Source or other

External Source
VIII - 13.1
Serial Interfacing
246
Processor Side of One-Byte Serial Interface

serial1busa.
Address Lines
(A1 and A0)
Address Lines
(A15..A2)
System Bus
Data Lines
on interface
R/W
Address
Decoder (ATD)
Chip Select
Bus Clock
Enable
Register
Selection
(Address
Decoder
for the
lower bits)
Transmit Register
Address and Write
Timing Information
the Communication
part of the
serial interface
Control
Register
Decoded Control
Serial Out
Register
Interrupt Enable
Address and
Write Timing
information
Serial Interface
(example)
Transmit
Register
Decoded Receive
Register
Address and
Read Timing
Receive Information
Register
Serial Data
Serial In
Out Ready
Interrupt Enable
Note: there is no clock

for the status register, why?
Decoded Status
Register
Address and
Read Timing
Information
Status
Register
Serial Data
In Ready
Open Collector
Gates
VCC
/IRQ
VIII - 14
Serial Interfacing
247
Reality Checks
There are a number of issues to resolve.
Time:
How does the receiver really recognize bits, bytes (or later blocks)?
Given a clock how do you send/receive the data (next)?
How do you get the clock (later)?
In the case of serial communication, slightly different meanings of Synchronous and
Asynchronous:
Synchronous: Both Rx and Tx use the same clock (frequency and phase).
Asynchronous: Rx and Tx have independent clocks that have the same (or similar)
frequencies.
Errors:
Corrupted data received due to noise on the channel.
Erroneous data caused by timing problems (e.g., slow reading, clocking differences)
VIII - 15
Serial Interfacing
248
Clocks/Time
Internal Clock for TransmitterB
Internal Clock for Receiver

B
Internal Clock for TransmitterA
Internal Clock for ReceiverA
There are many clocks in this system.
Nominal Data RateRight
System A
System B
Nominal Data RateLeft
The Transmit and Receive

clocks on a given interface do
not have to be at the same
data rate. (They usually are
at the same rate.)
The serial interface figures
leave the clock as external to
the interface.
In some cases a local oscillator is used for the transmit
clock and may be used for
the receive clock e.g., asynchronous.
The next figure shows the incoming
data and 4 ways to interpret it.
clocks.
VIII - 16
Serial Interfacing
249
Time and Data at the Transmitter and Receiver
Serial Data In
Rx Clock
Sample On Rising Edge (0011111000)

0
Sample On Falling Edge (0011110000)
Rx Clock
Sample On Rising Edge (01100)
Sample On Falling Edge (01100)
serclock.
VIII - 17
Serial Interfacing
250
Time and Data at the Transmitter and Receiver

Why are there two registers in each direction?
Receive: Processor may not pick up the data fast enough (Overrun)
Transmit: Processor may not respond fast enough to keep serial data stream uninterrupted.
VIII - 18
Serial Interfacing
251
Bit
Time
Bit
Time
Byte Time
RCV Register
8-bits to
CPU
Shift register
1-bit at a time
bitbyte
VIII - 18
Serial Interfacing
252
Before Communication Begins

How do two systems that need to exchange information agree on a common language.
The two ends must agree on the following issues:
timing,
control,
format,
data representation and
signal voltages, currents, connector pin-outs.
Communication Protocol : A set of rules for making connections and transferring information.
Protocols and Standards
VIII - 19
Serial Interfacing
253
Standards Who is in Charge?

The protocols associated with communication structures are often developed in a sequence
similar to the one listed below.
Industry specification: some company (or consortium of organizations) defines the specification for use with their products.
A national level organization (Eg., ANSI) may sanction this standard (or a slightly modified
version of the standard). The country organization may opt for input from a technical
organization (Eg., IEEE).
Eventually there may be need for an international standard. International standards are
often sanctioned by the International Standards Organization (ISO).
Finally, once the standard has reached true acceptance it will be sanctioned by CCITT
(Comite Consultatif International Telephonique et Telegraphique) the international organization representing the telephone companies.
VIII - 20
Serial Interfacing
254
Address
Decoder (ATD)
A0, A1
Address Lines
Serial Protocols
Clock Connection:
Synchronous?
Asynchronous?
Address and
Synchronization
Signals
System Bus
R/W
Data Bus
CS
Register
Selection
Int REQ
Local
Osc.
STATUS
8
CONTROL
8
SRin
RCV
8
XMIT
May Jumper to
one or both
clocks
Data Connected
SRout
Serial Data in
Channel
Interface
Rx Clock
Serial Data Out
Tx Clock
synchasynch.
VIII - 21
Serial Interfacing
255
CS
Address
Decoder (ATD)
A0, A1
Address Lines
Asynchronous Protocols
Clock Connection:
Asynchronous Clocks Passed By Convention
Address and
Synchronization
Signals
R/W
System Bus
Data Bus
Channel
Int REQ
Interface
Register
Selection
8
8
STATUS
Local
Osc.
CONTROL
RCV
XMIT
May Jumper to
one or both
clocks
Data Connected
Serial Data in
8
SRin
SRout
Rx Clock
Serial Data Out
Tx Clock
asynchclock.
Assume both ends of the channel know the correct (nominal) data rate.
(Standard) Baud Rates: 110, 134.5, 150, 300, 600, 1200, 2400, 4800, 9600, 19.2K
... .
Must convey the phase of the tx clock to the receiver.
This is an asynchronous data frame
showing one byte of data.
serial2a.
LSB
b0 b1
Idle
Start
Bit
Early
MSB
b7
Data Bits
Time
Late
VIII - 22
Serial Interfacing
256
Bit Synchronization
Issues
The data cannot be clocked into the receiver using the same clock as used for
transmission. That is, there is no wire connecting the clocks.
The designer (and user) of the receiver has only a nominal transmission frequency
specification.
There is no (direct) phase synchronization between the transmit and receive clocks.
The clock generators in the source and destinations do not necessarily have the same
drift coefficients. (Time or Temperature)
Design principle: The structure is designed assuming that the receiver has a reasonable
estimate of where the bit should start (phase synchronization), and the goal is to sample
the bit in the middle. Why?
To sample in the middle of the bit the following design characteristics are required.
A reasonably accurate specification for the nominal frequency (eg. (10000 5%) Hz.)
used to find the next bit given the current bit.
A way to extract the phase of the clock. (described later)
VIII - 23
Serial Interfacing
257
Bit Synchronization
Detailed clock design example
The figure assumes correct frequencies but Rx1, Rx2 and Rx3 differ in phase synchronization with the transmitter.
If we have multiples of the transmitter frequency available at the receiver, then we
can more accurately estimate the middle of the bit. (16 or 32 are multiples often
used)
VIII - 24
Serial Interfacing
258
Bit Synchronization
For this figure, ignore the

propagation delay from the
transmitter to the receiver.
Assume that data is transmitted by the falling edge of the
transmit clock.
Assume that you can construct several (three in the
figure) versions of the transmitter clock (an exact multiple of the actual transmitter
frequency, but with different
phases).
In the figure, the points
marked with the circle are the
rising edge closest to the center of the data bit. (The rising
edge of the transmit clock.)
sixteen.
One Bit Tx
Transmit Clock (At Rx)
Rx1
Rx2
Rx3
One Times Tx Clock
2*Rx1
2*Rx2
2*Rx3
Two Times Tx Clock
4*Rx1
4*Rx2
4*Rx3
Four Times Tx Clock

Probable Sample Edge
Worst case edge
VIII - 25
Serial Interfacing
259
Example of an Asynchronous Frame
Idle
LSB
b0 b1
Start
Bit
MSB
b7
Data Bits
Early
Start bit
for next
frame
1
Time
Late
serial2.
Bit -1 (Start Bit). Must have a value of 0 and indicates that a data byte is to start.
Bit 0-7 Data bit values
Bit 7 may also be a parity bit (Space (Parity Bit = 0), Mark (Parity Bit = 1), Even,
or Odd)
Bit 8 (and perhaps 9) Stop bit:
Must have a value 1 to indicate end of data
Value of 1 assures that start bit will have a falling edge at the start of it.
Between characters. The protocol leaves the line as a 1 when there is no data to transmit.
VIII - 26
Serial Interfacing
260
Bit Sampling
Possible to implement an asynchronous protocol at the receiver with a free-running local
oscillator n times the data rate. (Assume n=16, 8-bits of data, and no parity for this
example.)
Step
1
2
3
4
5
6
8
9
10
11
Counter
0x0
0..7
8
0x9..0x18
0xi9..0x(i + 1)8
0x79..0x88
0x89..0x98
0x98
0x99..0xA8
(If reqd)
0x0
Operation
Wait for start of start bit (falling edge)
Wait for 0.5 bit times (8 clock periods)
Verify that serial data line is still 0.
Wait 16 clock times (1 bit time) and sample the first bit
Wait 16 clock times (1 bit time) and sample the ith bit
Wait 16 clock times (1 bit time) and sample the last bit (bit
b7)
Wait 16 clock times (1 bit time)
If data = 0 then framing error (stop bit has wrong value).
If there are to be 2 stop bits repeat steps 8 and 9 one more
time.
Indicate that the byte has been received go to step 1.
VIII - 27
Serial Interfacing
261
S1
S2 S3 S4
Idle
b0
LSB
0x98
S0
0x88
88
0x78
0x58
72
0x68
0x48
40 56
0x28
24
0x18
0x08
Sample in the middle of each

bit.
Note: since the start bit
time and the bit structure is
known, Byte synchronization
is inherent.
Note: in this case 1 stop bit
is tested by considering the
lines value at clock 0x98. If
there were 2 stop bits, there
would be an additional test at
0xA8. If there were 1.5 stop
bits the additional test would
be at clock step 0xA0.
0x38
Bit Sampling
16 times clock
(HEX Notation)
104
120
136
152
16 times clock
S5 S6
S7
S8 S9
Sample Points
b1
b7
MSB
1
Start Bit
serial3.
VIII - 28
Serial Interfacing
262
Impact of Clock Errors

If the clock rate drift causes the sample point to change by more than 0.5 bits in 10 (1
start, 8 data and 1 stop bit), the information detected will be corrupted.
Therefore the frequencies of the derived clocks at the receiver and the transmitter
must differ by no more than 5% (if there is a 10-bit frame)
Note impact on the required clock precision if the number of data bits is increased.
Start
Bit
Data Bits
Stop
Bit
Correct Clock
Clock too slow
Line-up in
the middle of
start bit
Clock too fast
slowclocks.
VIII - 29
Serial Interfacing
263
Clock Shift
Let fT x and fRx be the actual clock rates for the transmitter and the receiver respectively. Also
assume that the number of bits to be transferred without error is B (B includes the start and
stop bits).
1/fTx
Tx Clock
DT
Rx Clock

Tx
1
1
fRx f
If B T > 12 f 1 then the shift at
Tx
the end of B bits is larger than 0.5 bits.
T =
1/fRx
clockshift.
VIII - 30
Serial Interfacing
264
One Eight-Bit Implementation - Overhead
Idle
LSB
b0 b1
Start
Bit
MSB
b7
Data Bits
Early
Start bit
for next
frame
1
Time
Late
serial2.
Overhead : (to be consistent with the previous definition) is
N umber of non data bits in a f rame

T otal number bits in a f rame
There is the following overhead (per byte of data).

Worst case: 7 data bits, 1 parity bit, 1 start bit and 2 stop bits, or 4 non-data bits for
every 7 bits of data. (4/11 or 36%)
Best case: 8 bits of data, 1 start bit, and 1 stop bit or 2 non-data bits for every 8 bits
of data. (2/10 or 20%)
VIII - 31
Serial Interfacing
265
Some Errors
Framing Error : An incorrect frame has been detected. In the case of one-byte asynchronous transfers, the indication of a framing problem is that the stop bit is incorrect
(possible baud rate error)
.
Overrun Error : In a serial communication system, the data at the transmitter and receiver
is transferred at a time convenient to the controlling processor. As a result it may be that
the serial data will arrive too quickly for the receiver to process the data. It is also possible
that the transmitter will be sending data faster than the serial channel can transfer the
data. In either case, some data may be overrun by the data following it in the channel.
This is an overrun error.
There are two special cases.
Receive Overrun Error : At the receiver, incoming data has overwritten data in SRin
or RCV register.
Transmit Overrun Error : Resulting from the CPU or the device writing to the transmit
buffer before the current content of the transmit buffer has been transmitted.
Parity Error : The parity of the received data and the value of the parity bit do not match
Start Bit Error : when the line is sampled one half of a bit time after the edge of the start
bit is detected, the value is not zero. This probably indicates that a false start bit has
been detected, alternatively there may be some error in the assumed bit rate.
VIII - 32
Serial Interfacing
266
Impact of Parity Selection

The selection of Even or Odd parity for a given application may depend on the character
set usage. For example:
Some noise appears as short duration pulses. These pulses may imitate some of the
timing of one or more bits.
Consider the cases shown in the figure below.
Parity Bit
Stop Bit
delete.
Start Bit
Bit 0
Delete 0x7F In the even parity

version in the presence of short noise
pulses: 8 bits (7 plus parity) a single
start bit followed by all 1s looks like
a correct even-parity character. However, it would be quite unlikely that the
signal pattern for the odd parity version
of Delete would occur in the same environment.
0x7E In this case, the even parity
version is less likely an error than the
odd parity version. Thus there is no
ideal parity.
Even Parity DELETE

Odd Parity DELETE
Even Parity ~
Odd Parity ~
VIII - 33
Serial Interfacing
267
Special Character
Break (and long break) ... Forces a framing error.
A normal break is usually a fixed duration in a given system. In some cases (with
slow data rates) this break may appear to be some form of data that starts with a
number of zeros. A long break often stays asserted as long as the user presses the
break key, this assures that it will be a framing error.
An example of out-of-band signalling.
Stop
Start
break.
Break
VIII - 34
Serial Interfacing
268
Note: Impact of Stop Bit Mismatch

Consider the situation where the transmitter and the receiver use different assumptions about the number of stop bits. (Since all
systems use 1 start bit there can be no confusion on this part of the protocol).
simplex1a.
Tx
(Transmitter)
Source
Assume
SBTx stop bits
Rx
(Receiver)
Channel
(implementation
unspecified)
Sink
Assume
SBRx stop bits
If SBT x = SBRx There is not problem

If SBT x > SBRx There may be a bit of extra
idle time between consecutive bytes, but communication will not be a problem.
If SBT x < SBRx There is a problem. If the
transmitter ever sends consecutive bytes as close
together as possible (SBT x bit times separation)
then the receiver will be looking for a stop bit
(a 1) where there is a start bit (a 0) and should
indicate a framing error.
Note: If the channel is bidirectional, then in most cases
the number of stop bits used for the transmit and receive timing will be the same on one end of the channel.
Hence if there is a discrepancy, one direction of communication will have the SBT x < SBRx relationship.
VIII - 34.1
Serial Interfacing
269
Asynchronous Serial Communication Synchronization Summary
Synchronization
Technique
Comments
Bit Synchronization:
Bit Rate by agreement May also be done by software detection.
Bit Synchronization:
Phase start/stop bits The receiver detects falling edge to determine
where the first bit starts.
Byte Synchronization start/stop bits Since only 1 byte per frame, once bit 0 has
been detected, the byte is also known.
Block Synchronization
N/A
Some of the techniques described in later sections could be used to provide Block Synchronization.
VIII - 35
Serial Interfacing
270
Synchronous Protocols
Require a common clock at source and destination.
this is the only difference between synchronous and asynchronous.
separate lines for clock and data. (limited distances and data rates.)
or
encode clock and data on same signal line (typically done with a signalling structure
similar to Manchester encoding).
Advantages:
reduced overhead no Start/Stop bits
higher speeds possible (no need to worry about relative accuracies of the two clocks).
asynchronous RS-232 max. 19,200 bps; Synchronous can be used beyond 10Mbps.
VIII - 36
Serial Interfacing
271
Clocking of Synchronous Serial Communication

genericsync.
To CPU
To Output Device
May provide a feedback loop

8-bit shift register
Data
in
8-bit shift register
Data
out 8-bit shift register
Clock in
From CPU
Global
Clock
From Input Device
Note:
Clock and wire length. If the distances are too large, then the clock may not arrive at
each input at the correct time. (Discussed in detail later in the term.)
VIII - 37
Serial Interfacing
272
Synchronous Serial Communication Connections
Address
Decoder (ATD)
A0, A1
Address Lines
synchclock.
R/W
System Bus
Channel
Int REQ
Data Bus
CS
Clock Connection:
Synchronous
Address and
Synchronization
Signals
Interface
Register
Selection
STATUS
Data Connected
Local
Osc.
CONTROL
8
8
SRin
XMIT
Serial Data in
RCV
Rx Clock
SRout
Serial Data Out
Tx Clock
CS
Address
Decoder (ATD)
A0, A1
Address Lines
synchclock2.
Clock Connection:
Synchronous encoded
data and clock on one signal
Address and
Synchronization
Signals
R/W
System Bus
Data Bus
Int REQ
Interface
Register
Selection
8
8
STATUS
CONTROL
RCV
XMIT
Encode Data and

Clock signal on a
single Line (Eg.,
Manchester Ecoding)
Tx Clock
Local
Osc.
Serial Data in
8
SRin
Rx Clock
Channel
Data Connected
8
8
Serial Data Out

8
SRout
Decode signal
to extract clock
and data.
VIII - 38
Serial Interfacing
273
Block Oriented Synchronous Port Structure
Address
Decoder (ATD)
CS
R/W
Register
Select
In Sync
(Status Bit)
Int REQ
Data Bus
Clock
Extraction
STATUS
CONTROL
Serial Data in
Sync Detect
RCV
QUEUE
SRin
XMIT
SRout
QUEUE
Serial Data Out

Tx Clock
serial14.
Synchronous Serial Communication
VIII - 39
Serial Interfacing
274
Typical Synchronous Port Structure

Of Note:
The receive clock is extracted from the input signal. The edges on the data line are used
to adjust the frequency and phase of a local oscillator.
no internal clock for the receiver. Although, there be an oscillator for use in clock
recover.
Since there are no start/stop bits, extra hardware is required for synchronization.
Since higher speeds are possible, FIFO queues may be required. (Gaps or flow-control may
be difficult or not possible at this level).
VIII - 40
Serial Interfacing
275
Bit Synchronization in Synchronous Systems
Serial Data
transmit Clock
Serial Transmit Data

0
0
1
Possible Receive Clock 1 (Wrong Edge Assumption)

1
Error
Possible Receive Clock 2 (Correct Edge Assumption)
manchester1.
VIII - 41
Serial Interfacing
276
How to Add Synchronization

Why is it needed?
Where/When is it needed?
BISYNC Protocol : Modify the sequence of characters using hardware or software to provide block synchronization. (Byte synchronization is used to derive block synchronization.)
HDLC Protocol : Modify the sequence of bits so that synchronization can be maintained.
(Bit synchronization is used to derived block synchronization.)
VIII - 42
Serial Interfacing
277
BISYNC Protocol
Based on special ASCII characters: SYNC (0x16), SOH, STX, ETX, ETB, and DLE.
(SYNC - Synchronize, SOH Start of Header, STX Start of Text, ETX End of Text, ETB
End of Transmission Block, DLE Date Link Escape) A complete listing of the ASCII table
is available in most texts or on the Internet (at www.asciitable.com).
A long string of SYNC characters can eventually be recognized and are used to establish
synchronization during initialization.
SYNC characters are ignored (except for their synchronization characteristic).
VIII - 43
Serial Interfacing
278
BISYNC Protocol (Cont.)
Check Bits 2 Bytes
ETX 1 Byte
Data < 256 Bytes
STX 1 Byte
Header 3 Bytes
SOH 1 Byte
seria15a.
SYNC >= 1 Byte
Header: may contain

source and destination
addresses,
and/or a sequence
number
BISYNC Frame
Data: contains data being transferred (but not STX or ETX characters).
send these characters (and all special characters) with a Data Link Escape (DLE). A
DLE character indicates that the next character is to be interpreted as a normal (not
special) character.
For example:
DLE | STX would be used to send an STX in the data stream and
DLE | DLE would be used to send a DLE in the data stream
When the source buffer empties, SYNCs are inserted by the source and ignored by the
destination, as long as the character prior to the first SYNC is not a DLE.
VIII - 44
Serial Interfacing
279
HDLC (High-Level Data Link Control) Protocol

HDLC is based on modifying the sequence of bits so that synchronization can be achieved.
HDLC will never transmit a string of six 1s over the link, except as a special message to
the receiver called a flag.
if the user data requires five 1s (in one byte or in two consecutive bytes) the hardware
sends five 1s, then a 0 and then the sixth bit of data.
0x7E (0111 1110) is transmitted as {9 bits} 0111 11010, where the extra 0 has
been stuffed into the data.
0x3E (0011 1110) is transmitted as {9 bits} 0011 11100, where the extra 0 has
been stuffed into the data.
when a receiver receives five 1s in a row, it discards the next bit (if it is a 0) and
treats it as a flag (if it is a1).
this referred to as bit-stuffing.
VIII - 45
Serial Interfacing
280
Flag
Check
Data
Control (1-2)
Addr
Flag
HDLC Protocol (cont.)
seria15b.
Note: No idle periods are allowed. Thus:

if the source FIFO ever empties, the transmission must be aborted. (An abort is eight
1s in a row.)
VIII - 46
Serial Interfacing
281
HDLC Frame Structure

serial16.
01111110 Address
Flag
Minimum Frame 3 Fields
-- Address (8)
-- Control (8)
-- Checksum (16)
>= 0
Control
Data
16
Checksum 01111110
Flag
Frame Types
Control Field
i) Information
0 Seq
ii) Supervisory
1 0 type next
iii) Unnumbered
1 1 type mod
next
p/f
VIII - 47
Serial Interfacing
282
HDLC - Information Frames

serial16a.
Frame Types
Control Field
i) Information
p
/
f
0 Seq
next
Seq: Frame sequence number

Each frame is assigned a number (0 ... 7)
Used for re-transmission control
Permits several messages to be sent before any ACK received.
Next: Piggy backed acknowledgment
All messages up to Next-1 (mod 8) have been received without error.
P/F: Poll/Final. Can be used to poll (P) a unit for data or to indicate that this is the
final (F) packet. It can also be used to force (F) an acknowledgment from the other end.
VIII - 48
Serial Interfacing
283
HDLC - Supervisory Frames

serial16b.
Frame Types
Control Frame
ii) Supervisory
1 0 type next
Type 0: Used as an Acknowledgment (ACK) only. Useful when there is no reverse traffic
on which to carry the acknowledgments.
Type 1: Negative Acknowledgment (NACK). The Next field indicates the number of the
first frame that must be retransmitted.
Type 2: Similar to type 0. ACK all messages up to Next-1 but causes the sender to stop
transmission. When ready Next will be either ACKed or NACKed.
Type 3: Selective Reject. Resend just the named frame.
VIII - 49
Serial Interfacing
284
HDLC - Un-Numbered Frames

serial16c.
Frame Types
iii) Unnumbered
Control Frame
1 1 type mod
Various Control functions

DISConnect Machine going down.
SNRM (Set Normal Response Mode) Reset sequence numbers to 0
FRMR (Frame Reject) A frame was received with a valid checksum, but it made no
sense.
UA (Un-numbered Acknowledge) Acknowledge for a control frame (control frames are
not numbered, but only one can be outstanding at a time.)
VIII - 50
Serial Interfacing
285
Various Acknowledgement Structures

1. No sequence number. One outstanding at a time.
seria17a.
Time
Sender
Receiver
2. Sequence numbers (no errors)

seria17b.
1
0
3
1
4
2
5
3
Numbers all relative to Sender Numbers
VIII - 51
Serial Interfacing
286

3. Sequence numbers (with errors(E) and time-outs). Note: D indicates a discarded frame.
Timeout
seria17c.
4. Sequence numbers using NACKs for errors

0
4
NACK
D D D D
E Error no packet received
D Discard
E
seria17d.
Stop course content on HDLC at this point

VIII - 52
Serial Interfacing
287

5. Two Directional Traffic Flow.
B->A
A->B
1
1
4
1
2
5
6
2
4
0
Acked
B
B->A
A->B
2
1
1
3
2
4
3
5
7
Acked
6
0
seria18a.
Note: Only n 1 can be outstanding at one time.
VIII - 53
Serial Interfacing
288
3/0
3/1
3/2
3/3
3/4
Assume all are delivered
3/5
3/6
3/7
4/0
4/0
4/1
4/2
4/3
4/4
4/5
4/6
4/7
Assume all are lost
5/0
Now the right side has been told that the 2nd
0 packet has been received.
seria18c.
VIII - 54
Serial Interfacing
289
3/0
3/1
3/2
3/3
3/4
3/5
3/6
4/7
4/7
4/0
4/1
Assume all are lost
4/2
4/3
4/4
4/5
5/7
Now the next field of 7 has 1 meaning to both sides
seria18d.
VIII - 55
Serial Interfacing
290

6. Could Accept frames out of order.
0
0
ACK 6
NACK 2
seria18b.
Note for out of order to work the protocol must

have a receiver that has a window that it will accept data in.
the receiver window must be no more than n2 where n is the range of the message
numbers.
VIII - 56
Serial Interfacing
291

For Example
3/0
3/1
Timeout
3/2
3/3
3/4
3/5
3/6
4/7
Lost
Old
3/0
3/1
3/2
Window 7, 0-5
(Assumed to be) New
3/3
3/4
3/5
3/6
Now forward 7, old 0- old5 to host
serial19.
Thus the new window and the old window cannot overlap ... max window size is n2 .
VIII - 57
Serial Interfacing
292
Synchronous Serial Communication Synchronization Summary

Sync
Level
Bit Rate
Bit Phase
Byte
Block
Global
Single Line
Clock
for Data and Clock
Technique
Technique
Comments
Dedicated clock signal Hardware detection
May require agreement to
an approximate rate
Dedicated clock signal Derived from serial Although often part of
data stream
clock extraction, the phase
can be detected by observing the edges and shifting
edges until mid bit always
found. (Assuming Manchester encoding.)
Flag, bit, bit-pattern Flag or bit pattern
or global reset
Byte synchronization Bit or byte synchronization
VIII - 58
Serial Interfacing
293
Asynchronous vs Synchronous Serial Communication

Issue
Transmission
Rate
Complexity
Bit and Byte
Synchronization
Block
Synchronization
Asynchronous
Often slower
Synchronous
May be high if block-oriented Even higher (dependent on

transfers are implemented
H/W S/W choices)
Higher overhead (up to 20%)
Byte-oriented only
(e.g., BISYNC)
Alternatives available
(e.g., BISYNC and HDLC)
VIII - 59
Serial Interfacing
294
Final Signal Comments

Electrical Properties: it should be noted that the actual drivers and receivers used to
transfer (synchronous or asynchronous) serial signals can be of any type.
The considerations that may come into the driver and receiver selection include the following.
Distance: as the distance increases, there will be a need for more specialized drivers
and receivers.
Noise: as the noise increases, there will be a need for more specialized drivers and
receivers.
Data Rates: as the data rate increases, there will be a need for more specialized
drivers and receivers.
Standards: if the driver and receiver will be provided by different subsystem manufacturers,
then a standard would be required.
VIII - 60
Serial Interfacing
295
USB Resource
The most complete source is the USB specification, available from the USB web site
http://www.usb.org/developers/docs/
There are also a number of good reference books on the subject available including:
Anderson and Dzatko, Universal Serial Bus System Architecture, Mindshare Inc, NJ, 2001.
Universal Serial Bus (USB)
VIII - 61
Serial Interfacing
296
USB Introduction - Goals

General Goal: to bring sanity to the mixture of standards and cables used in the PC market.
Interpreted from the following motivations.
connection of the PC to the telephone (cheap ubiquitous connectivity)
ease-of-use (a.k.a. plug-and-play)
port expansion (bidirectional, low-cost, low-to-mid speed peripheral bus that expands)
Specific Goals:
common connector (tree based, expandable) This goal failed in that there is more
than 1 connector used.
hot plug-in support, including automatic detection and configuration.
support new and legacy peripherals
higher performance than the systems it replaced
low-power implementation
direct power distribution for low-power devices
VIII - 62
Serial Interfacing
297
Introduction - Structure
Links transferring only

LS information
1.x Host Controller and

Root Hub
Links transferring
LS and FS information
Device
Device
Device
Device
Hub (1.x)
Hub (1.x)
Hub (1.x)
Device
Device
Low Speed Device (LS)

(1.5 Mbps)
Full Speed Device (FS)
(12 Mbps)
Hub
Version 2.0 also supports High Speed (HS)

(480 Mbps)
Version 3.0 supports Super Speed (4.8 GBits per second)
- requires double cabling.
usb1.
VIII - 63
Serial Interfacing
298
Introduction - Topics of Interest

Signalling
Data transfers
Synchronization
Control structure
These notes discuss Low Speed (1.5 Mbps) and Full Speed (12 Mbps) modes for connection to
1.x compliant devices. There is very limited discussion of the High Speed (480 Mbps) mode for
connection to 2.x compliant devices.
VIII - 64
Serial Interfacing
299
Low Speed and Full Speed Signalling

At the signal level.
Four wires, power, ground, D+ (Data Positive) and D- (Data Negative)
D+ and D- are half duplex (unidirectional at any given time)
Differential drivers and receivers,
Cable Z0 = 90 15%
RSource = 45 for high-speed operations. A value between 28 and 44 is specified
for full-speed operation.
not source matched.
Slew rate limited (4 ns to 20 ns from 10% to 90% voltage levels into a 50 pf load).
VOH 2.8 V ; VOL 0.3 V .
Maximum cable skew between D+ and D is 100 ps.
VIII - 65
Serial Interfacing
300
USB Signalling
usbsignal1
Only one of these resistors per device

Upstream Port
(hub)
Differential
Receiver
Differential
Transmitter
Xmit Data
SE0
OE
D+
Single Ended Receivers
(Primarily for line
status information)
D-
Low Speed
Devices
(only)
Full Speed
Devices
(only)
Downstream Port
(device or hub)
D+
D90 Cable
15 k
SE0: Single-ended 0
VIII - 66
Serial Interfacing
301
Low-Level Synchronization
Data rate is specified by the presence of one of the resistors pulling up either D- (Low
Speed) or D+ (Full Speed). This is detected when the device is plugged into the hub
Non-Return-to-Zero-Inverted (NRZI) signal encoding. (Zeros cause transitions and ones
do not cause transitions)
Bit stuffing is used to maintain enough clock edges to keep the clock synchronized. (Stuff
after 6 consecutive ones in this case.)
(Block Synchronization 1) Start of Packet is transmitted as 00000001 to synchronize
clock (lots of edges with the 0s for bit/clock synchronization and then one 1 for byte
synchronization.) Of note, line goes idle between packets and clock re-synchronization is
required for each packet.
(Block Synchronization 2) Out-of-band signalling for end of packet. (Both D+ and Dare held at 0 for 2 bit times using the SE0 signal to force a violation of differential output
values.)
VIII - 67
Serial Interfacing
302
NRZI Signalling
usbsignals
D+
DSynchronization Pattern
start of the
packet
VIII - 68
Serial Interfacing
303
USB Data Transfers

Asymmetric connection, only the root hub can initiate transfers
Each transaction is (usually) composed of 3 packets.
USB Token Packet: Selects the slave for the communication. The slave includes:
T arget device (7-bits), endpoint number (the I/O register in the device (4-bits)),
and the direction of transfer (in or out).
USB Data Packet: Payload information for the transfer up to 1023 bytes in
isochronous case, and 64 bytes for other (full-speed) transfers.
USB Handshake Packet: When required, this is used to confirm to the data source
that the data has been received (and accepted) by the data destination. This is not
required for isochronous transfers.
VIII - 69
Serial Interfacing
304
USB Packet Format
Packet ID
(PID)
8-bits
Packet Specific Information
CRC
EOP
Synchronization
Sequence
usbpackets1
0000001
USB PID: There are 16 PID values. Each value is specified as 4-bits followed by the same
four bits, complemented. For example: ID 0101 (Start of Frame) is a PID of A5.
Other values are: Setup (0xD, or 0x2D), Input (0x1 or 0x1E) and Output (0x9 or 0x96).
VIII - 70
Serial Interfacing
305
USB Token Packets

USB SOF Token Packet: In USB, a frame is used to provide some synchronization and to
facilitate data transfer. In most cases, the SOF packet will be sent once per millisecond
to indicate a new cycle has started. The SOF token packet provides a number to indicate
that this is the start of the nth frame. Please note, the concept of frame used in USB (a
sequence of activities that repeat every 1 ms) is quite different from the concept used in
the serial communication section of the notes.
USB IN Token Packet: The IN packet can be used for Interrupt, Bulk, Control and
Isosynchronous transfers (more later). The IN packet provides the address of the device
and the I/O register (endpoint) to provide the data for the IN transfer.
USB OUT Token Packet: The same as IN except the communication channel being
established is in the opposite direction.
USB SETUP Token Packet: Used to setup the remote device or hub.
VIII - 71
Serial Interfacing
306
USB Handshake Packets

USB ACK Packet: Error free receipt of data packet.
USB NACK Packet: Unable to accept or return data. Also used during polling to indicate
that no new data is available.
USB STALL Packet: T arget unable to complete transfer and software intervention is
required.
VIII - 72
Serial Interfacing
307
USB Types of Transfers

USB Interrupt Transfer : Traditional small volume transfers. There is no interrupt facility
on the USB, so each device must be polled at a regular interval to see if a new value has
been entered for action. During the interval between polling, a device could lose data, but
every piece of data must be delivered, therefore there is a time critical component.
USB Bulk Transfer : Used by block transfer devices. Once the transfer has been started,
there is no particular time constraint. Every piece of data must be delivered.
USB Isochronous Transfer : Typically real-time data. The data must be read/written with
a given rate. If one item is missed it can be ignored and processing continues. Every piece
of data need not be delivered.
USB Control Transfer : Used to setup devices.
VIII - 73
Serial Interfacing
308
USB Setup
usbsoftware
User Application
requests 1024 byte
bulk transfer (Out)
User
Request
Audio
1 sample per ms
Other
System S/W
Other
System S/W
I/O Request Packet (IRP)

64-Byte
Requests
Host
Driver
USB
Driver
16
Add to
Each Frame
Frame 1
VIII - 74
Serial Interfacing
309
Using Serial Communication in the Real World

Considered thus far:
channels,
synchronization,
clocking, and
block and byte transfer techniques.
Left to cover:
how to use typical interconnections (RS-232)
signalling details (later in the notes)
Using RS 232 Communications Standard
VIII - 75
Serial Interfacing
310
RS-232 Electrical Interface

Originally specified to attach data terminal equipment (DTE) to a modem or data communication equipment (DCE)
Now used to connect computers to: terminals, modems, (some) printers, almost any
(relatively) slow peripheral
serial6.
DCE (Modem or other Communication Equipment)

{Data Communication Equipment}
DTE (Terminal or Computer)

{Data Terminal Equipment}
Ring Indicator (RI)

Data Terminal Ready (DTR)
Carrier Detect (CD)
Data Set Ready (DSR)
Clear To Send (CTS)
Request To Send (RTS)
Receive
Transmit
22
20
8
7
6
5
4
3
Ring Indicator
Data Terminal Ready
Carrier Detect
signal gnd
Data Set Ready

Clear To Send
Request To Send
Receive
Transmit
1
shield ground
VIII - 76
Serial Interfacing
311

Note:
Shield Ground is attached to the chassis (if it is safe to do so)
Signal Grounds must be connected which may lead to ground loop problems
According to the standard each device may have 50 feet of cable (100 ft. total)
A standard D connector is used
Many more signalling details later in the course.
VIII - 77
Serial Interfacing
312
DTE
RS-232
DCE
Comm. Line
serial7.
Note: Connections are

asymmetric there is
a DTE connector and a
DCE connector and the
direction of information
flow is not the same.
Signal
Function
TRANSMIT
Data from DTE to DCE
RECEIVE
Data from DCE to DTE
RTS (Request to Used by the DTE to indicate that
Send)
it has a character to send (Half duplex)
CTS (Clear to Used by the DCE to indicate that
Send)
the character (indicated by RTS)
may now be sent
DSR (Data Set Used to inform DTE and DCE that
Ready) and DTR the other is operational (Power on
(Data Terminal etc.)
Ready)
CD (Carrier De- The communications line is now actect)
tive
RI (Ring Indica- There is a request from the commutor)
nications line (and hence the DCE)
to contact the DTE
VIII - 78
Serial Interfacing
313

If connecting two DTEs (Eg. a computer and a printer), then must translate connections
between lines, using a null modem.
serial6b.
RS-232 Links
Communications
System
Printer
Processor
Connection as envisioned by standard writers
RS-232 Links
A Null Communications
system
(usually referred to as
a Null Modem
Processor
Connection used by
computer users
Printer
VIII - 79
Serial Interfacing
314
General Null Modem

serial8.
DTE
RI
DTR
CD
Signal GND
DSR
CTS
RTS
RECEIVE
TRANSMIT
Shield GND
DTE
What connections
go in here to
make it work
RI
DTR
CD
Signal GND
DSR
CTS
RTS
RECEIVE
TRANSMIT
Shield GND
Null Modem
VIII - 80
Serial Interfacing
315
3/4-Wire Null Modem

serial8 3.
DTE
DTE
RI
DTR
CD
Signal GND
DSR
CTS
RTS
RECEIVE
TRANSMIT
Shield GND
RI
DTR
CD
Signal GND
DSR
CTS
RTS
RECEIVE
TRANSMIT
Shield GND
3 (or 4) Wire Null-modem
Note change in operation at the software level.

Note shield ground is not always included (as discussed much later in the course).
VIII - 81
Serial Interfacing
316
5/6-Wire Null Modem

serial8 5.
DTE
DTE
RI
DTR
CD
Signal GND
DSR
CTS
RTS
RECEIVE
TRANSMIT
Shield GND
RI
DTR
CD
Signal GND
DSR
CTS
RTS
RECEIVE
TRANSMIT
Shield GND
5 (or 6) Wire Null-modem
To be continued
VIII - 82
Serial Interfacing
317
Questions of Interest: Serial
Terms discussed in this section of the notes: Simplex, Half-Duplex, Full-Duplex, Bit Synchronization, Bit Rate Synchronization, Phase Synchronization, Byte Synchronization, Block Synchronization, Bit Rate, Baud Rate and Overhead.
Various specific bit patterns and overheads for the different types of communication alternatives
Given 1024 bits to transmit. Compare the overhead bits required to send the data as:
asynchronous frame, with 2 stop bits, 8 bits of data and no parity
asynchronous frame, with 2 stop bits, 8 bits of data and 1 parity bit
asynchronous frame, with 2 stop bits, 8 bits of data, and sufficient check bits (using Hamming coding) to correct
single bit errors.
as synchronous frame, 256 byte blocks, sufficient checking for single error bit corrections (no other control information)
the minimum number of BISYNC frames
the minimum number of HDLC frames
comment on the relative merits of each technique and when it would be reasonable to use that technique.
VIII - 82.1
Serial Interfacing
318
Questions of Interest: Serial (Cont.)
A group of 224 students entered their radio-shack/source store to by a cable that implemented a null-modem (as well as
connecting two DTEs). However on closer examination, they determined that there were actually 8-wires. Using their
knowledge from class, they knew what the first six wires were ... what two additional wires could have been cross-connected?
Why do you think this? One enterprising student borrowed a connectivity meter and determined that this particular cable
connected CTS on one end to RTS on the other end. This leads to the following questions.
What extra functionality would be available with this added connectivity?
How would the interfacing software change with the addition of CTS and RTS? (Your answer should consider both
options: could their be no change? and what changes would be required to use any extra functionality provided by
this connection?)
Provide an application where this functionality may be important?
Engineering Questions
trade-off when to use character vs block oriented communication
BISYNC vs HDLC (in-band/out-of-band signalling)
since a 3 wire null-modem requires fewer signals than a 5-wire null modem, it should be used.
VIII - 82.2
Serial Interfacing
319
Note: Terms used in Serial Interfacing Section
VIII - 82.1
Serial Interfacing
320
Terms:
Simplex (page 234)

Half Duplex (page 234)
Full Duplex (page 234)
Bit Synchronization (page 235)
Bit Rate Synchronization (page 235)
Phase Synchronization (page 235)
Byte Synchronization (page 235)
Block Synchronization (page 235)
Bit Rate (page 240)
Baud Rate (page 240)
Communication Protocol (page 252)
Overhead (page 264)
Framing Error (page 265)
Overrun Error (page 265)
Receive Overrun Error (page 265)
Transmit Overrun Error (page 265)
Parity Error (page 265)
Start Bit Error (page 265)
BISYNC Protocol (page 276)
HDLC Protocol (page 276)
USB Token Packet (page 303)
USB Data Packet (page 303)
USB Handshake Packet (page 303)
USB PID (page 304)
USB SOF Token Packet (page 305)
USB IN Token Packet (page 305)
USB OUT Token Packet (page 305)
USB SETUP Token Packet (page 305)
USB ACK Packet (page 306)
USB NACK Packet (page 306)
USB STALL Packet (page 306)
USB Interrupt Transfer (page 307)
USB Bulk Transfer (page 307)
USB Isochronous Transfer (page 307)
USB Control Transfer (page 307)
VIII - 82.1
Section IX:
Analog Interfaces
f2014-1.0
Analog Interfaces
322
Analog Interfacing: Section Contents

Op-Amp Review (starting on page 325) Review of the aspects of Op-Amp operation required for the analog section of the notes.
Analog Signal Conversion Issues (starting on page 338) Issues associated with conversion between discrete and continuous systems
and representation of analog values in various binary number representations.
Digital-to-Analog Converters (starting on page 342) Operation characteristics associated with digital-to-analog converters; binary
weighted ladder and R-2R ladder used as examples; commercial examples; and errors and performance issues are considered.
Analog-to-Digital Converters (starting on page 374) Operation characteristics associated with analog-to-digital converters; hardware and software (assisted) implementations for binary ramp and successive approximation converters as well as hardware only
implementations for flash, single-slope and dual slope converters used as examples; and commercial examples are considered.
A/D Converter Specifications and Errors (starting on page 412) Linear and Non-linear errors as well as performance limitations are
examined.
Time Varying Signals (starting on page 413) The earlier discussions of errors assumed that the signals applied to the analog-to-digital
converter were constant with respect to time. The limitations imposed by time varying signals are examined.
Sample and Hold Circuits (starting on page 421) Examines the operational characteristics and limitations of sample and hold circuits
as an alternative to manage time-varying signals.
Section Contents: Analog Interfacing
IX - 0.1
Analog Interfaces
323
Resources
Texas Instruments Data Sheets:
Current Feedback Amplifiers: Review, Stability Analysis and Applications provides background
material on the introductory section of these notes.
Current Feedback Amplifiers ...
http://www-s.ti.com/sc/psheets/sboa081/sboa081.pdf
Understanding Data Converters. This document provides good coverage of the error in Analogto-Digital and Digital-to-Analog converters. It also material in excess of our coverage in sampling
topics.
TI Application Note: Understanding Data Converters
http://www-s.ti.com/sc/psheets/slaa013/slaa013.pdf
The following application note may be of interest to those wishing to pursue material beyond the
scope of this course. It focuses on some of the material we cover, but also examines performance
issues in more detail.
Principles of Data Acquisition and Conversion
http://www-s.ti.com/sc/psheets/sbaa051/sbaa051.pdf
Resources
IX - 1
Analog Interfaces
324
Analog Introduction
Digital-to-Analog
Conversion and Interface
(1)
User System
Possible Feedback Path
Processing system
Analog-to-Digital
Conversion and Interface
(2)
Sample and Hold

(3)
Signals Treated as Discrete

Values
Signals treated as
Continuous Values
analogOverview
Resources
IX - 2
Analog Interfaces
325
Op-Amp Review
VVin= (V+-V-)
V+
Vin
AVol
Vout
opamp1.
Properties of an ideal Op-Amp:

Infinite input impedance (Zin = and the input current is zero)
Zero output impedance (Zout = 0)
Infinite open-loop gain (AVol = ; VVout
= AVol )
in
(ol open loop)
Input/output relationship Vout = (V+ V) AVol = Vin AVol
Zero internal noise generation
Infinite bandwidth
Op-Amp Review
IX - 3
Analog Interfaces
326
Non-Ideal Op-Amps
ideal, but finite gain
rails.
Vout
Vout = (V+ V) AVol = Vin AVol

Vout
= V+ V
AVol
Vs
V-
Vs
Vout
V+
Vs-
Very steep slope
Vin= 0
Vin
Vs-
Op-Amp Review
IX - 4
Analog Interfaces
327
Use of an Op-Amp
two modes:
Comparator : An op-amp connected without feedback can be configured to be a
comparator. In this case the output values are close to either VS or V+S
With feedback
Negative feedback
Positive feedback (not this term)
Op-Amp Review
IX - 5
Analog Interfaces
328
Op-Amp (without feedback) as a Comparator

Often required for interface between the analog and digital domains.
Note: if there is no feedback component(s), then the output switches to either Vs or Vs.
VVin= V+-VV+
Two input voltages:

VC, and VRef
Vs
Vout
+
VsOp-Amp View
V
VV+
Vout
+
V
s-
Logic Output (1 or 0)
Open Loop Comparator
User's View
compare1a.
Op-Amp Review
IX - 6
Analog Interfaces
329
Op-Amp (without feedback) as a Comparator Output Characteristics

Vs
V-= VRef
V+=VC
Vs
Vout
+
VsVs
V-=VC
V+=VRef
Positive-Logic Comparator
Implements VC>VRef
Vs-
VRef
Negative-Logic Comparator
Vout
Vout
Vs
VC
Vout
Implements VC<VRef
VsVs-
Op-Amp Review
VRef
VC
compare1b.
IX - 7
Analog Interfaces
330
Basic Inverting Amplifier
dac1.
Rf
V-
Rin
Vin
V+
Vout
Rin
+ Vin
V = ( Vout Vin)
(Rin + Rf )
(1)
Vout = (V+ V) AVol
But
V+ = 0
Therefore
Vout = VAVol
Vout
V =
AVol
(2)
Inverting Amplifier : An op-amp configured with a resistor feedback element such that an increase
in the input voltage results in a decrease in the output voltage
Op-Amp Review
IX - 8
Analog Interfaces
331
Note: Basic Inverting Amplifier
Vout-Vin
Rf
Vin
VRin + Vin
( Vout Vin )
But
V+ = 0
Vout
V+
Rin
+ Vin
(Rin + Rf )
Vout = (V+ V ) AVol
V-
Rin
Therefore
dac1a.
Op-Amp Review
Vout
V AVol
Vout
AVol
IX - 8.1
Analog Interfaces
332
Basic Inverting Amplifier

Equating (1) and (2) results in:
Vout
AV
ol
= (Vout Vin) (RinR+inR ) + Vin

f
=Vout( (RinR+inR ) + A1 ) = Vin( (Rin+f R ) )

f
Vol
Therefore, if AVol then

Rf
Vout
=
Vin
Rin
Vout =
Rf
Vin
Rin
(3)
(Typical values for AVol are between 105 and 106.

Op-Amp Review
IX - 9
Analog Interfaces
333
Note: Basic Inverting Amplifier
Note: (Substitute (3) into (1))

V = (
= (
Op-Amp Review
Rf
Rin
Vin Vin )
+ Vin
Rin
(Rin + Rf )
Rin + Rf
Rin
)(
)Vin + Vin = 0
Rin
(Rin + Rf )
IX - 9.1
Analog Interfaces
334
Simplified Op-Amp Analysis
I1 + I2 = 0; I1 = I2
Vout
Vin
; and I2 =
Rin
Rf
Therefore
I1 =
I2
I1
Rin
Vout
Vin
=
Rin
Rf
Vout
Rf
=
Vin
Rin
Assume AV = infinity
ol
Rf
Rin
VV+
Vin
I1
Note: 0V drop is a virtual short!
Rf
0V
I2
Vout
if AVol :
virtual short
0 = V+V = Vin
V+ = V
dac2.
Op-Amp Review
IX - 10
Analog Interfaces
335
Current Summer/Inverting Adder/Weighted Summer
I1
V1
R1
If =
0v
Rf
If
I2
V2
Rf
R2
VIn
Vn
Vout
Vout
V+
current in the ith leg is Ii = RVii ,

the current in the feedback is If =
From KCL
P
P
i Ii + If = 0 and If = Ii
Therefore
If Rf = Vout
Vout
Rf
Rf
Rf
Rf
= ( V1 +
V2 + ... +
Vn )
R1
R2
Rn
If (R1 = R2 = ... = R) then
Rn
dacsumm.
Vo
Op-Amp Review
Rf X
= ( Vi )
R i
IX - 11
Analog Interfaces
336
Basic Non-Inverting Amplifier
I2
I1
Rin
I1 = I2
Rf
V+
Vout
I1 =
I2 =
Vin
Vin
Rin
Vout Vin
Rf
Vin
Rin
Vout Vin
Rf
Vout
Vin
Rf +Rin
Rin
dac3.
Non-Inverting Amplifier : An op-amp configured with a resistor feedback element such that an
increase in the input voltage results in an increase in the output voltage
Op-Amp Review
IX - 12
Analog Interfaces
337
Non-Inverting Buffer
Non-Inverting Buffer : A special case non-inverting amplifier Rf = 0; Rin =
Vout = Vin
High impedance input
Low impedance output
Rf = 0
VVout
Vin
dacbuff.
Op-Amp Review
IX - 13
Analog Interfaces
338
Dynamic Characteristics of Analog Signals
Expected Output
Actual Output
Vin
+/- 10%
of final
value
X
10%
Delay
Slew
Ring
Settling Time
step response when viewed at an analog level (i.e., this is true for all signals)
delay
slew
ring
dynamic1
The Step response is characterized by

settling time: the time for the output to settle within a specified range of the final value
for a given input.
slew rate: the rate at which signals change from one value to another.
Analog Signal Conversion Issues
IX - 14
Analog Interfaces
339
Analog Interfacing Some Conversion Issues

Quantization: When an analog signal is reduced from a continuous signal to a set of digital
values, a range of analog signals must be assigned a single digital value (quantity). The act of
this transformation is quantization.
LSB: On the analog side, one LSB is the change in the analog signal that corresponds to a
change of one digital LSB (one bit). A more mathematical specification is that 1LSB =
F SAR
2n 1 ,
where F SAR is the full-scale analog range and n is the number of bits used by the digital
representation.
Analog Digital
continuous discrete
real integers
In 224 and 325 LSB in reference to the analog

material refers to the analog LSB. (Voltage
or Current)
LSB (voltage or current) LSB (bit)
IX - 15
Analog Interfaces
340
Scaling and Number Systems
Positive
Voltage
scaling1s.
Unipolar (0 to VMax)
Negative
Voltage
Assume the same VMax in the +ve Voltage
Sign-Magnitude
2's Complement
0 1 2 3 4 5 6 7 8 9 A B C D E F
Digital Value
Consider a 4-bit value:

b3 b2 b1 b0
Unipolar: Values represented zero (0) to fifteen (15).
Sign Magnitude: A b3
value of 0 means b2b1b0
is one of 7 positive values and a b3 value of 1
means b2b1b0 is one of 7
negative values. (Note
increment from a digital value of 7 (0111)
to a digital value of 8
(1000).)
Twos Complement: b3
has same impact as in
sign magnitude. Note
the impact of incrementing from 0111 to
1000.
IX - 16
Analog Interfaces
341
Note: Scaling and Numbers

Issues to note on the previous slide.
Given 4 bits (16 values) there has been an assumption that the goal for all three converters shown, is to convert (either to
or from analog) the same maximum positive value. Of course other assumptions would have lead to different figures.
Using sign-magnitude, there are 2 zeros (recall from earlier course).
In the case of twos-complement arithmetic, to change from 0 to -1, requires that ALL bits change (from 0000 to 1111).
note the impact of not allowing for this in your software. If you accidentally send a -ve 1 (1111) to a D/A converter expecting
unipolar values wide voltage swings may result. If you read a value and assume the wrong type of converter your control
algorithm will behave very oddly.
Although not related to the number system in use, it is worth noting the impact of switching from 3-bits to 4-bits to represent
the positive values.
IX - 16.1
Analog Interfaces
342
Digital-to-Analog Converters
D/A Converters (DACs)

Output voltage (or current) Proportional to:
Analog ref. voltage
(VRef ) and
n-bit binary input
x = k Vref B (x is the
output, k a proportionality constant, Vref the
ref. voltage, and B the
binary word).
It will be shown that:
full-scale:
VM ax = kVref (2n 1)
Often |k| 21n and thus
|VM ax| |Vref |
System Bus
CS
D/A Interface
Not all signals to

Parallel port shown
j-Bit Register
Address Decoder
Reference In
Vref
i bits (j >= i )
n bits
Connection to D/A
may (or may not) be
a fully parallel connection
Analog Out
D/A Converter
x = kVrefB
dacover.
IX - 17
Analog Interfaces
343
Analog Output (x)
Ideal Relationship
Analog Output(x)
Volts
LSB
3.75
2.50
n=2, and k = 1/2n
1.25
x = 0.25 * 5 * B
0.0
For example,
Let Vref=5 Volts,
No Error Points
00
000
001
010
011
01
10
11
Digital Input (B)
Digital Input(B)
dacrange2.
dacrange.
Two DAC examples:

I Binary weighted resistor ladder
II R-2R ladder.
IX - 18
Analog Interfaces
344
I Binary Weighted Resistor Ladder

Assume that switch i is switched (connected) when a 1 is applied to bit Bi.
Switch
Vref
If
B3
B2
0.5R
1R
B1
2R
B0
4R
8R
Vout
Basic Binary Weighted Resistor Ladder
weighted.
If =
Vout
0.5R
2Vout
R
ref
= ( 8R
B0 +
Vref
4R B1
Vref
2R B2
Vref
R B3 )
IX - 19
Analog Interfaces
345
I Binary Weighted Resistor Ladder
If =
2Vout =
2Vout =
Vout =
Vout =
M ax
Vout
=
Vout
0.5R
2Vout
R
ref
= ( 8R
B0 +
Vref
4R B1
B0 B1 B2 B3
+
+ ) Vref
( +
8
4
2
1
Vref
(8B3 + 4B2 {z+ 2B1 + B0)}
8 |
3
Vref X
Bi2i
16 i=0
Vref n1
X
n
Bi2i
2 i=0
2n 1
Vref n = F SAR
2
Vref
2R B2
Vref
R B3 )
Reminder: These derivations are all

based on the assumption that the
feedback resistor is of size 0.5R. A
different value of the feedback resistor will lead to different results and
a different value of k.
Recall:
FSAR
1 LSB = n
2 1
n
Vref 2 21
n
=
2n 1
VRef
=
2n
IX - 20
Analog Interfaces
346
I Binary Weighted Resistor Ladder - Varying Input Impedance

Note Input Impedance (w.r.t. Vref ) varies as n-bits vary.
Consider the current demands on Vref if all of the B values are 1, then compare that
to the situation when all of the B values are 0.
It is easier to make a constant voltage source if you have a constant current load.
Vref
R
2R
4R
8R
B3 0
1
B2 0
1
B1 0
1
0
B0
1
0.5R
Vout
Constant Input Impedence 8R || 4R || 2R || R = 8/15 R
weighta.
Constant current load from the Vref source. However, this current load is now the same
as the maximum current load in the previous version.
IX - 21
Analog Interfaces
347
Note: How do I attach one of these to my processor?

7
6
Data register
Load data register serial or parallel

Design assumes transient data
5
4
3
Vref
R
2
1
0
B3
0
1
2R B2 0
1
4R B1 0
1
8R B0 0
1
0.5R
Vout
weighta1.
The register could either be the one associated with the parallel port, or could be the register from some form of serial interface (I.e.
SPI).
IX - 21.1
Analog Interfaces
348
I Binary Weighted Resistor Ladder - Resistor Values
Nominal Case 1
Bit
Resistor Resistor
7
20 R 10 k
6
21 R 20 k
0
2n1 R 1.28 M
Op-Amp Characteristics
Parameter
Case 1
Vref
10 V
IB7
1mA
IB0
4 A
Case 2
Resistor
100
200
12.8 k
Case 2
10 V
100 mA
400 A
For large n very

large resistors are
needed.
Consider
the two cases shown
to the left.
100 mA is too large
for most/all normal
op-amps. (Case 2)
4A is down in the
noise level of most
op-amps. (Case 1)
Large range of resistors is very hard to
fabricate precisely.
IX - 22
Analog Interfaces
349
II R 2R Ladders
Vref
I
R
I1
2R
R
I2
2R
R
I3
2R
I4
2R
2R
r2ra.
Input Impedance is fixed at Zin = R. (Start from the right)

I=
Vref
R
I1 =
I
2
I2 =
I1
2
I
4
etc.
IX - 23
Analog Interfaces
350
Note: How do R - 2R Ladders Work?

Consider the modified version of the figure shown below.
At the blue points the circuit to the right always looks like two 2R
resistors in parallel (when looking to the right).
The two parallel 2R resistors split any current in half
The two parallel resistors (effective resistance 1R) are in series
with a resistor with a resistance of R.
Vref
I
R
I1
2R
R
I2
2R
R
I3
2R
I4
2R
2R
r2ra2.
IX - 23.1
Analog Interfaces
351
II R 2R Ladders
r2r1.
Vref
Vo = IT R = RIT
2R
B3 1
2R
B2 1
R 2R
B1 1
R 2R
2R
B0 1
IT
I
= R(B0 16
+ B1 I8 + B2 I4 + B3 I2 )
Vo
ref
ref
ref
ref
= R(B0 16R
+ B1 8R
+ B2 4R
+ B3 2R
)
Vref
16 (B0
V
ref
Vo = 16
1
k = 16
P3
+ 2B1 + 4B2 + 8B3)
i=0 Bi 2
or, (x = kVref B)
There is additional material starting on page 342 OR

DAC Equation
IX - 24
Analog Interfaces
352
R 2R Characteristics
Easy to fabricate 2 resistors of fixed ratios.
Exact value not critical.
Consider an n-bit D/A Vo =
Vref
2n
Pn1
i=0
Bi2i
Full scale output Bi = 1, i, 0 i n 1

Vref
Vo = n
2
Thus, if |k| <
1
2n
2n 1
2 = Vref ( n )
i=0
2
n1
X
i
(n-bit converter), |Vo| < |Vref | Note: even if all of the bits of B are set
2n 1
Vref 2n
to 1, the largest possible output value is: Vout =

Reminder: These derivations are all based on the assumption that the feedback resistor is of size
R. A different value of the feedback resistor will lead to different results and a different value
of k.
IX - 25
Analog Interfaces
353
Multiplying DACs (MDACs)

Most would consider Vref to be a fixed value, but
One could vary Vref and at the same time vary the digital control lines.
Multiplying DAC (M-DAC): A digital-analog-converter configured so that the analog input (voltage) signal (previously referred to as Vref ) is a varying signal. Such a system would have an
output analog voltage of: Vout = k B Vin as shown below.
Vin
(Vref)
Vout = K B Vin
M-DAC
B0
Bn
mdac2.
Thus, the M-DAC implements a programmable-gain amplifier for the analog input voltage.
If you attach an analog signal to Vin, then you control the gain with the digital signal (B).
IX - 26
Analog Interfaces
354
D/A Converter Characteristics Specifications

Resolution (DAC and ADC): The number of bits in the digital value used for the input to
the DAC (or the output from the ADC). Eg., 12-bits
Precision (DAC and ADC): The smallest distinguishable change in output. Ideally 1 LSB.
(Eg. for a 12-bit D/A 1 in 212 or 0.024% of full scale.)
Accuracy : Comparison of the actual output to the expected output.
A converter with 10V full scale and an accuracy of 0.2% max. error of 20 mV
(10 0.002).
Often specified as a fraction of the LSB (eg. 0.5LSB).
For example, since the precision of a 10-bit D/A is 1 in 210 or 0.1%, the accuracy
should ideally be 0.05%.
IX - 27
Analog Interfaces
355
D/A Converter Characteristics Specifications

Range: The maximum output value minus the minimum output value.
Dynamic Range: The New Penguin Dictionary of Electronics defines dynamic range as:
The range over which an active electronic device can produce a suitable output signal in
response to an input signal. It is often quoted as the difference in decibels between the
noise level of the system and the level at which the output is saturated (the overload level).
The noise level is at least 1 LSB. (In decibels 20 log(kVref ).)
saturation is 2n 1. (In decibels 20 log(kVref (2n 1)).)
Dynamic Range (in dB) = 20 log(2n 1) dB.
For example 4 bits 20 log10 15 20 db.
Errors: consider errors in 3 groups:
gain and offset errors: errors are independent of the applied digital value.
linearity errors: errors that may be considered to be dependent on the applied B
value.
environmental errors.
IX - 28
Analog Interfaces
356
D/A Converter Characteristics - Offset Errors

Offset Error : An analog shift in the output of a DAC that is constant over the full range of
digital input values.
Output
Sometimes specified as a percentage of the
range.
offset
100%
range
An offset error may be caused by leakage
currents in the switches or by some bias current at the input to the op-amp.
The offset error may also have a temperature coefficient.
Calibration can reduce the impact of these
errors.
Ideal
Actual
Input
FF
00
dacerr1.
IX - 29
Analog Interfaces
357
D/A Converter Characteristics - Scale Errors

Gain Error : An error in the analog output of the DAC that varies (linearly) with the digital value
applied. Errors in gain can often be attributed to errors (or drift) in resistor values. May also
be caused by changes in the reference voltage.
Output
May have a temperature coefficient (I.e., q parts per million

per degree C)
Gain errors can also be corrected through calibration (for
a given constant temperature). Often compensated for
at full-scale.
Ideal
Actual
Input
dacerr2.
IX - 30
Analog Interfaces
358
Note: A Mathematical Model of Linear Errors and Calibration
Ideal relationship: VOut = VIdeal = kVRef B
but there may be an offset error of VOf f set and the result would be:
Of f estError
VOut
= VIdeal + VOf f set
we could cancel this with calibration by subtracting the offset at 0 output (let VZeroCode be the voltage that is produced,
before calibration, when the code for 0 V is applied to the input.)
Of f setCalibrated
VOut
= VIdeal + VOf f set VZeroCode
but there could also be a gain error.

Of f setCalibrated
GainError
VOut
= VOut
GainError
we can calibrate this out as well. If we determine the ratio of the actual maximum output voltage (VMActual
ax ) and then alter
the gain as follows:.
Of f setCalibrated
GainCalibrated
VOut
= VOut
GainError
F SAR
VMActual
ax
IX - 30.1
Analog Interfaces
359
D/A Converter Characteristics - Linearity Errors Differential

Differential Non-Linearity (DNL): The differences between the analog values corresponding
to consecutive (input) digital values.
DN L = M ax(|(Vout(i + 1) Vout(i)) (V )ideal |)
E.g., DNL = 1 LSB means that moving from B = i to B = i + 1 will result in a change of
output between 2 LSBs and 0 LSB in magnitude. ((V )ideal is one LSB)
dacerr3a2011.
Not a DNL error here

(increase by 1 LSB)
High
Actual
Expected
Value
1 LSB
Differential Non-Linearity
Actual Analog Value
Analog Value Out
Note: Gain and offset errors have been

compensated for prior to this measurement
Low
Actual
Digital Value In
i+1
Digital Value
DNL < 1LSB
Expected Output
IX - 31
Analog Interfaces
360
Monotonicity Error
Low
Actual
i+1
Digital Value
DNL < 1LSB
(no monotonicity error)
Expected
Value
1 LSB
Expected
Value
High
Actual
Actual Analog Value
High
Actual
1 LSB
Actual Analog Value
Monotonicity Error : If, for any two consecutive digital values, increasing from i to i + 1
results in a decrease in output (analog) values, there is a monotonicity error. This can
occur if DNL > 1LSB.
Low
Actual
i+1
Digital Value
DNL >= 1LSB
(possible monotonicity error)
monotonicity.
IX - 32
Analog Interfaces
361
D/A Converter Characteristics - Linearity Errors Integral
Differential
non-linearity
Analog Out
Analog Out
Analog Out
Integral Linearity : The maximum deviation between the true output and a straight line
representing the ideal output. This calculation/measurement is based on the assumption
that all of the linear errors have been eliminated (compensated).
Digital In
Monotonicity Digital In
error
Expected Output
Integral error shown in

2 places only
Integral Digital In
linearity error
Actual Output
dacerr32011.
IX - 33
Analog Interfaces
362
Note: Error Example

Assume that you have a converter with the following output
In this example 1LSB has an analog value of 0.5 volts
DAC Expected
Actual
INL
DNL
Input
Output
Output
See
EO
AO
(EO-AO) Below
0V
0V
0V
NA
0.5 V
0.4 V
0.1 V
0.1 V
1.0 V
0.8 V
0.2 V
0.1 V
1.5 V
1.2 V
0.3 V
0.1 V
2.0 V
1.8 V
0.2 V
0.1 V
2.5 V
2.8 V
0.3 V
0.5 V
3.0 V
3.3 V
0.3 V
0V
7
3.5 V
3.5 V
0V
0.3 V
DNL Column Entry = ||AOi AOi1 | 0.5|
Result: Worst case INL is 0.3 V (or 0.6 LSB) and worst case
DNL is 0.5 V or 1 LSB.
Actual Output
Analog Out (Volts)
Expected Output
0
0
4
5
6
Digital Input (Digital)
DacDNL INL ErrorExample.
IX - 33.1
Analog Interfaces
363
D/A Converter Characteristics - Environmental Errors and Comments

Power supply rejection ratio: A measure of how sensitive is the converter to changes in
the power supply voltage.
%change f ull scale
S=
%change supply voltage
For example, if decreasing the power supply voltage by 5% (from 5.0 V to 4.75 V) results
in a decrease in Vref from 2.5 V to 2.0 V (I.e., a 20% decrease), S would be 4 (assuming
nothing else changed).
Error Specification:
as an absolute value (eg. offset 10 mV),
as a percentage of full scale
as a number (or fraction) of LSBs
are specified as independent of each other, and hence the impact of a gain error, an
offset error and a linearity error are cumulative.
IX - 34
Analog Interfaces
364
D/A Converter Characteristics Dynamic Performance

See Settling Time (starting on page 338)
Mostly of the output Amplifier
often specified as time until a certain percentage of the final output has been reached.
( 12 LSB) (Assuming a full scale transition)
ideal signal
+- 1/2 LSB
Vout
Undershoot
Ringing
Slew
Rate
Overshoot
time
t1
t2
settling time = t2 - t1
dacerr4.
Manufacturers often leave amplifier off of D/A and provide only a current source.
This simple change (make the DAC cheaper AND faster) is a good deal for the sellers.
(You will see this in an example shortly.)
IX - 35
Analog Interfaces
365
D/A Converter Characteristics - Dynamic Performance

Glitch Impulse: At the time that the digital value changes from one value to another, the
analog output may not change directly from one value to the other. For example not all
of the internal switches will change at the same rate and thus some erroneous values may
appear at the output. This is also referred to as Glitch impulse area ... it is the area in
the glitch caused by the different switching times.
glitch impulse response

8 (1000)
7(0111)
change input from 8 to 7 here

glitch
In this case, it may be that the switch for the current associated with 8 (I.e., b3) turns off
slower than the ones (I.e., b0, b1, b2) associated with 7 turn on. Thus there is a temporary
increase above either value.
IX - 36
Analog Interfaces
366
Factors Affecting Conversion Time

DAC settling time
settling time (Op-Amp)
switch response times
Note: conversion time limits the frequency of operation. If the converter requires t s to
change values, and the user changes the value at an interval of 3t s, the results will not
be as expected.
IX - 37
Analog Interfaces
367
Example TLV5621E (TI)

(Based on 1996 Data Sheet)
TLV5621E is a low-power, quad 8-bit D/A Converter.
Serial Interface (4 channels, 14-pin DIP Package)
Data is loaded serially
Data can be double buffered
Data (and control) are loaded as 10-bit units
data: 2-bit address and 8-bits data
control four 2-bit fields as control bits for the 4 DACs (enable/disable and 1/2
control) plus two chip level controls (single/double buffering)
Each channel is based on a resistor string (one resistor with 256 taps).
Ref. Voltages are buffered (so the sources see a high impedance)
Linearity comes from matching resistors
IX - 38
Analog Interfaces
368
-VRef
DAC
Switch
X2
Analog
Out
Vo
Range
8
Latch
CODE
Latch
Block Diagram for TI TLV5621E

Serial/
Parallel
tvl5621.
Output Voltage VO = Vref CODE

256 (1 + Range)
IX - 39
Analog Interfaces
369

Operating Characteristics from data sheet
Output Voltage VO = Vref CODE
256 (1 + Range)
Range = 0/1
Output source current 1 ma (code = 255)
Output sink current 5 A (DAC-A) and 20A Others
Ref. Current 10A
Output Slew Rate (DAC-A)
V
Rising 0.8 s
V
Falling 0.5 s
V
Output Slew rate (Others) 1 s
Output Settling Time (to 0.5 LSB) 10 s (For DAC-A)...75 s

IX - 40
Analog Interfaces
370

Errors
Integral Linearity 1 LSB
Differential Linearity 0.9 LSB (Max) 0.1 LSB Typical
Zero Scale Error (Error when CODE =00 ) 30 mV
Zero Scale Error Temp Coef. 10 V
C
Zero Scale Error Supply Rejection 2 mV
V
Full Scale Error (I.e. CODE = FF) 60 mV
Full Scale Error Temp Coef. 25 V
>C
Full Scale Error Supply Rejection 2 mV
V
IX - 41
Analog Interfaces
371
MAX 529
This DAC has the following characteristics.
8 analog output signals
serial interface to processing system (SPI Compliant)
single (5 Volt) or dual ( 5-20 Volt) supply
each pair of outputs can be placed in to one of the following modes of operation
unbuffered: attach directly to the output point of the R2R Ladder.
buffered: a built in buffer is provided with +5 mA (-2 mA) drive (sink) capability
half-buffered: lower power than fully buffered, but limited to unipolar output operation.
IX - 42
Analog Interfaces
372
MAX 529 - Static Characteristics

Parameter
Symbol
Relative
Accuracy
Differential
Nonlinearity
Full-Scale
Error
Gain Error
Gain Error
Zero-Code
Error
Zero-Code
Tempco
VDD Rejection
VSS Rejection
RLE
Conditions
Unbuffered Mode
Min Typ Max
0.3 1.0
0.3
DNL
Guaranteed
monotonic
FSE
RLOAD = open
1.0
Full-Buffered Mode
Min Typ
Max
0.3 1.0
0.3
1/2
5
5
DAC
0x55
DAC
0x55
LSB
LSB
LSB
0.2
1.3
RLOAD = open
RLOAD = 5 k
PSRR
VDD
PSRR
VSS
1.0
Units
2.5
60
%
%
mV
V/C
100
code
0.1
1.0
0.3
2.0
mV/V
code
0.1
1.0
0.8
5.0
mV/V
IX - 43
Analog Interfaces
373
MAX 529 - Static Characteristics

Operation
data shifted in serial into two 8-bit registers A (A7-A0) and D (D7-D0) with A7 in first
and D0 last.
programming:
The bits of A correspond to the DACs. (I.e., A= 0x7 means that the accompanying
D value is loaded into DACs 0, 1, and 2.)
If A= 0 and D7=1 then the rest of D is interpreted as command to select the buffer
mode. (An example of in-band signalling.)
IX - 44
Analog Interfaces
374
Analog-to-Digital Converters
(A/D Converters or ADCs)
System Bus
Address
and
Timing
Decoder
(ATD)
Control
Status
Data
Conversion Complete
Start Conversion
A/D Converter
VRef
Analog In
Analog Section
adcover.
IX - 45
Analog Interfaces
375
adc1.
Id
R ea
el l
at
io
ns
hi
p
Two Basic Operations:

Quantization (starting
on page 339)
Coding assign a binary code to each discrete range.
Note: if the digital value
of 010 is read, then the
applied (analog) voltage is
1.5 LSBs < VAnalog <
2.5 LSBs.
Digital
Representation
011
010
001
000
Analog Input
1
LSBs
Transition Point
Midpoint of the interval is the
analog voltage rep. by the code
+1/2 LSB
Quantization Error
+/- 0.5 LSB
-1/2 LSB
IX - 46
Analog Interfaces
376
sh
ip
Analog-to-Digital Converters Unbiased Error
Id
R ea
el l
at
io
n
Digital
Representation
011
010
001
000
Analog Input
1
LSBs
Transition Point
Midpoint of the interval is the
analog voltage rep. by the code
+1/2 LSB
-1/2 LSB
adc1a
IX - 47
Analog Interfaces
377
Analog-to-Digital Converters Biased Error

adc1biased.
Ideal Relationship
Digital Representation
011
010
001
000
Analog Input
1
Transition Point
Biased, digital output changes when voltage passes the value.
+1/2 LSB
-1/2 LSB
Quantization Error
0/-1 LSB
Note: if the digital value of 010 is read, then the applied (Analog) voltage is 2.0 LSBs
VAnalog < 3.0 LSBs.
IX - 48
Analog Interfaces
378
Some Types of ADCs

Direct Converters (voltage binary)
I Binary ramp (includes a DAC)
II Successive approximation (includes a DAC)
III Flash
Indirect Converters (voltage time binary)
IV Integrating
V Dual Slope
IX - 49
Analog Interfaces
379
I Binary Ramp ADC
Analog Section
A
-
Analog In
VAnalog
B+
Vref
DAC
(n-bit)
to parallel port
DV
Clock
Control
1 Flip-Flip
Comparator
Q
D
C
CLK
Q
CLR
B<A B>A
n bits
n-bit Counter
enable
Reset
Start of Conversion
Conversion
complete
adc2.
IX - 50
Analog Interfaces
380
I Binary Ramp ADC - Operation

Recall: C = 1 if A < B and C = 0 if A > B.
Start of Conversion signal resets counter and flip-flop
Free-running clock increments counter
DAC output is a discretized ramp. The output Digital Value is labelled as DV.
The processor starts the conversion by changing the start of conversion signal from a zero
to a 1. This signal resets the counter and the control flip-flop.
When DAC output exceeds analog input, comparator clocks a 1 into the flip-flop signalling
conversion complete, and stopping the counter.
The processor must detect (polling or interrupt) the conversion complete status and then
read the value.
IX - 51
Analog Interfaces
381
Note: I Binary Ramp ADC Commented
1
A
-
Analog In
VAnalog
Comparator
C
Q
D
CLK _ Control
Flip-Flop
B<A B>A CLR Q
B+
Vref
DAC
(n-bit)
to parallel port
DV
Clock
n bits
enable
n-bit Counter
Reset
Start of Conversion
Conversion
complete
Rising Edge Flip-Flop

Set to 1, when Comparator
detects B> A
(Up) Counter stops when

Comparator clocks the control flip flop
the value in the counter is
a representation of the value
required, by the DAC to produce
a value slightly larger than the
applied (analog) voltage.
Start at this time

by resetting the counter
to zero, and clearing the control flip-flop
adc2a.
IX - 51.1
Analog Interfaces
382
I Binary Ramp ADC - Sample Output
1.0
0.857
0.714
0.571
0.429
0.286
0.143
0.0
Binrary Code
(Counter Value)
Voltage
(DAC Output)
adc5a.
DV
111
110
101
100
011
010
001
000
Example: 3-Bit DAC, 1V Full Scale => 0.143 V/ Step
1 LSB = 0.143V
RAMP ADC
0.6V
Note: ADC converts

0.6V to 101
which is interpreted as 0.714 V
0.571 < VAnalog < 0.714
(biased high.
all analog voltages between
0.571V and 0.714V are
interpreted as 0.714V)
Time (in clock periods)

6 clock periods to convert, 0.6V = 101
IX - 52
Analog Interfaces
383
I Binary Ramp ADC - Software Version
adc3.
Parallel Port Out

DV
Parallel Port In
S
+
Vref
1-bit
n-bits
DAC
(n-bit)
Analog in
VAnalog
Use the processor to generate the values to

cause a ramp out of the DAC and
then check the output of the comparator
/* let n be the number of bits */

/* resolution in the DAC */
/* Assume DV is unsigned and represented */
/* by more than n bits */
/* let S be the Comparator output */
/* I.e., the status bit */
/* addressing not shown */
DV = 0;
/* sleep if necessary */
while ((S == 0) && (DV < pow(2,n)-1 ))
/* if conversion complete not set */
/* and not yet overflow set of values */
{
DV = DV + 1;
}
/* if DV is less than 2^n */
/*
then it is the value */
/* if DV is equal to 2^n then */
/*
an overflow has occurred */
IX - 53
Analog Interfaces
384
I Binary Ramp ADC - Comments

Conversion speed is a function of:
analog input voltage
clock frequency (hardware implementation); software execution time (software implementation).
DAC Speed
Conversion accuracy also depends on DAC and comparator.
The data output is persistent. (I.e., the data remains correct in the n-bit counter until a
new start of conversion is received.)
Advantage: simple to implement.
Disadvantages:
variable conversion time,
conversion slow for large n (Up to 2n clock cycles)
DAC overshoot (may, depending on magnitude of the overshoot) cause premature
triggering of flip-flop
speed limited by DAC settling time.
IX - 54
Analog Interfaces
385
II Successive Approximation ADC

Goal to improve the performance of the binary ramp ADC.
convert linear search of ramp to binary search
Fixed conversion time, for a given n (independent of analog input value)
Fast conversion ( n where n is the number of bits). This is a significant improvement
over the binary ramp which is 2n.
Implementation in hardware or software (relatively) straightforward.
IX - 55
Analog Interfaces
386
II Successive Approximation ADC - Structure

adc4
Analog Section
VAnalog
to Parallel Port
Vref
B
V-
DAC
(n-bit)
DV
n-bits
SAR
Clock
V+
C = A>B
(C is a 1 if DAC
output higher
than VAnalog)
Control
Control signals include:
Set/Clear Bit i
Start of Conversion
Conversion Complete
Note: SAR:Successive Approximation Register
IX - 56
Analog Interfaces
387
II Successive Approximation ADC Algorithm

Basic Algorithm
Assume the SAR bits are numbered 0 to n-1 (with n-1 = MSB)
Clear all bits of results (DVi = 0 i n 1)
1. set X = n 1(MSB)
2. set DVX = 1; wait for DAC to settle.
3. If Comparator output high, clear DVX , wait for DAC to settle
4. Decrement X and if it is 0 go to step 2.
IX - 57
Analog Interfaces
388
II Successive Approximation ADC - Sample Output
Successive Approx. Converter

DV
1.0
0.857
0.714
0.571
0.429
0.286
0.143
0.0
111
110
101
100
011
010
001
000
0.6V

adc5b.
IX - 58
Analog Interfaces
389
II Successive Approximation ADC - Sample Output Comments
Successive Approx. Converter

Note: if the bit is to be set and
reset in the same clock cycle
the DAC must settle with in 0.5 clock peiods
DV
0.6V
Bit 0
111
110
101
100
011
010
001
000
Bit 2
Bit 1
1.0
0.857
0.714
0.571
0.429
0.286
0.143
0.0
Note: ADC converts 0.6V to 100

which is interpreted as 0.571 V
0.571 < VAnalog < 0.714 (biased low)

adc5b1.
IX - 59
Analog Interfaces
390
II Successive Approximation ADC - Software Version
adc3.
Parallel Port Out

DV
Parallel Port In
S
+
Vref
1-bit
n-bits
DAC
(n-bit)
Analog in
VAnalog
Use the processor to generate the values for

the DAC and then check the output
of the comparator
/* let n be the number of bits */

/* resolution in the DAC */
/* let S be the comparator output signal */
/* (I.e. the status bit) */
/* addressing not shown */
DV = 0;
for (i=n-1; i>= 0; i--)
{
/* First, set the ith bit
DV = DV | (1 << i);
if (S == 1) /* DV too high */
{
DV = DV & ~(1 << i);
}
}
IX - 60
Analog Interfaces
391
II Successive Approximation ADC - Comments

Advantages: Simple to implement (H/W or S/W).
Disadvantages: Still multiple clock periods for conversion.
Very popular technique.
Its speed can be improved by observing that the DAC does not have to change very much
as the conversion progresses, thus it may be possible to clock the SAR faster as the bit to
be tested changes.
The data output is persistent. (I.e., the data remains valid in the n-bit SAR until a new
start of conversion is received.)
IX - 61
Analog Interfaces
392
Comparison Ramp Vs Successive Approx.

Ramp overestimates VAnalog (biased high)
Successive approximation converter underestimates VAnalog (biased low)
Both converters have very similar hardware and software costs, however the successive
approximation converter requires fewer clock periods (but may require a faster DAC if the
same clock period is used for both converters).
Conversion time, for the Successive Approximation ADC, is fixed (n clock periods) and
not affected by the voltage level being converted.
Note the curious time signal from the SA Converter.
May have fewer glitch problems: For example, the DAC on the ramp ADC must convert
values such as 2n 1 and then 2n without tripping the control flip-flop. However the DAC
in the successive approximation converter, only has 1 switch turned on/off at a given time.
IX - 62
Analog Interfaces
393
Flash ADC (Fast Brute Force Approach)

General Case (nbit converter)
VRef
VAnalog
R
R
Encoder
R
R
R
DV
n-bits to
the parallel port
All low => all 0's out

All high => all 1's out
R
R
R
(2n) -1 comparators
Etc.
Note: the comparators have a 1 output
if VAnalog>voltage from the resistor chain
adc6a.
IX - 63
Analog Interfaces
394
Flash ADC (Fast Brute Force Approach) Comments

General Case (nbit converter)
For the ith leg of the resistor chain
Vi = (i*R/(2nR)) * VRef
VRef
R
2n-1
R
VAnalog
Encoder
R
R
R
2
1
Encoder Example:
Input 00000000000111
Output 0100
DV
n-bits to
the parallel port
All low => all 0's out

All high => all 1's out
R
R
R
(2n) -1 comparators
Etc.
Note: the comparators have a 1 output
if VAnalog>voltage
from the resistor chain
adc6a1.
IX - 64
Analog Interfaces
395
III Flash ADC (Fast Brute Force Approach)

Specific Case (2bit converter)
VRef VAnalog
Z
R
3/4 VRef
R
1/2 VRef
R
1/4 VRef
R
Encoder Output
DV
11
Y
10
X
01
VRef
00
VAnalog
1/4 1/2 3/4
times VRef
Example, n=2, => 3 comparators
adc6b.
Z Y X
1 1 1
0 1 1
0 0 1
0 0 0
Comments
VAnalog > 34 Vref
1
3
V
>
V
>
ref
Analog
4
2 Vref
1
1
V
>
V
>
ref
Analog
2
4 Vref
1
4 Vref > VAnalog
Encoder
1
1
0
0
Output
1
0
1
0
IX - 65
Analog Interfaces
396
III Flash ADC - Comments

As shown, the data is transient
Biased low
There is no need for start/end of conversion. On the other hand there is no way to tell
the converter has stabilized.
Advantage: Very fast (up to video rates 750 M samples/s). It is only limited by the
settling time of comparator and encoder.
Disadvantages: Many accurate resistors needed, need 2n 1 comparators
IX - 66
Analog Interfaces
397
Indirect Techniques
Previous schemes were based on voltage comparisons
(Indirect) Integrating ADCs
Operation:
Converts voltage to time then
Converts time to a number by use of a counter
Versions:
Single slope and dual slope.
IX - 67
Analog Interfaces
398
Integrator from an Op-Amp
Recall the operation of an integrator.

Recall
dv
I=C
dt
So, in this case
dVout
Vin
= C
R
dt
Integrate both sides
Z
Z
1
T
T dVout
dt
=
dt
in
t0
t0
RC
dt
T
t0
adc7.
C
Vin R
If
-
Iin
Vout
Iin = - If
Iin = Vin/R
If = C dVout/dt
1
Vin dt = Vout(T ) Vout(t0)
RC
IX - 68
Analog Interfaces
399
Voltage Integrator Operation

Assume that the input voltage does not change during the interval t0 T
Z
1
T
Vin t0 dt = Vout(T ) Vout(t0)

RC
At time T , (T t0)
Vin Z T
Vout(T ) =
t0 dt + Vout (t0 )
RC
=
Vin
(T t0) + Vout(t0)
RC
IX - 69
Analog Interfaces
400
Voltage Integrator Timing Diagram
Vout
If Vin less than 0 the
slope will change to +ve.
Vout(t0)
Vin/RC
Vout(T)
Vout(T)=Vout(t0)-(T-t0)Vin/RC
t
t0
T
-Vin/RC
adc7a.
IX - 70
Analog Interfaces
401
IV Single Slope - Operation

Now using a voltage integrator to convert voltage into time, we can consider the single
slope analog-to-digital converter.
Its operation is based on creating a voltage ramp (with a known slope) and then determining how long the ramp takes to reach the unknown voltage.
V
out
VAnalog
Counter Stopped
VRef/RC
Time
adc9.
IX - 71
Analog Interfaces
402
IV Single Slope - Operation
adc8.
- VRef R
(VRef >0, but value

applied is neg.
eg. -5V)
Start
Clock (free runnning)
DV
Vout
Out
n-bit Counter
VAnalog +
Reset
Control
Logic
Conversion Done
The switch is held closed until conversion is started (Thus

Vout(0) = 0 and Vout(T ) =
T
RC Vref )
At start of conversion, control logic opens the switch
and resets counter. When the
switch is opened, Vout ramps
Vref
up with a slope of RC
Start of Conversion
IX - 72
Analog Interfaces
403
IV Single Slope ADC - Operation

when threshold is reached, the counter is stopped. (Time T .)
Thus Vout(T ) VAnalog and
T =
DV
f
where DV =binary value in counter
and f = clock frequency.

Thus
VAnalog
DV
T
RC Vref
Vref
RCf DV
VAnalog RCf
Vref
Note: the value read (DV) is dependent on values of R, C, f and Vref .
IX - 73
Analog Interfaces
404
Single Slope ADC - Component Selection

The values for the components can be selected to simplify the use of the results from the
converter. For example to convert values of VAnalog between 0 and VM ax (and no larger)
choose
Vref
RCf = (2 1)
VM ax
n
If n = 8, Vref = 5 V, VM ax 5 V, the product RCf must have a value of 255.
IX - 74
Analog Interfaces
405
IV Single Slope - Comments

As shown, this converter produces persistent data.
Advantages: Simple idea, reasonably good converter.
Disadvantages:
Error in clock frequency (f ) leads to conversion error (stable frequency source needed)
Error in R or C (or drift due to temperature or age) leads to conversion errors.
Sensitive to Vref errors
Conversion time proportional to VAnalog .
VAnalog =
T
RC Vref
Vref
RCf DV
IX - 75
Analog Interfaces
406
V Dual Slope ADC - Operation

adc10.
VAnalog
C
R
Vo
-Vref
Reverse
+
+
Switch Control
Control
Logic
Terminal Count
Counter
Clock of Freq f
Register(DV)
DV (this version may be made
persistent)
Load DV register
at appropriate time
When is the
appropriate time?
To Parallel Port
IX - 76
Analog Interfaces
407
adc11.
Vo
DV
T
VAnalog/RC
-Vref/RC
V0(T)
Conversion starts with Vo =

0, and counter = 0.
V
1 ZT
VAnalog dt =
Vo(T ) =
RC 0
Since VAnalog is positive, the
initial output voltage has a
negative slope.
N
(usually
VAnalog
n
=2
cycles) DV=
2n Cycles
Vref
Variable Slope,
Fixed Slope,
Fixed Time
Variable Time
IX - 77
Analog Interfaces
408
V Dual Slope ADC - Several Voltages
Consider 3 different applied voltages

Vo
T
t3
t2
t1
DV
t
V1,0(T)
V2,0(T)
V3,0(T)
adc11a.
IX - 78
Analog Interfaces
409

When the counter reaches some value N (I.e. T =
N
f)
the switch position is changed and
the counter reset.

Although not required, a very common value for N is 2n, where n is the number of
bits of resolution for the ADC, and the number of bits in the counter. (The remainder
of this section uses N = 2n.)
Note there will be a carry out from the counter when 2n clock periods have passed.
Now start integrating using Vref
1
Vo(T + ) = RC
Vref
RC
R T +
(Vref ) dt + Vo(T )
VAnalog
RC T
=0
IX - 79
Analog Interfaces
410

When Vo(T + ) = 0 stop the counter, copy the contents of the counter into a register
(DV) (with the value from the conversion), and then start integrating with VAnalog as the
input again.
This occurs when
Vref
RC
VAnalog
RC T
or
when VAnalog = Vref T

Note: =
DV
f
, and T =
2n
f
therefore
VAnalog
Vref
= n DV
2
M ax
VAnalog
2n 1
= Vref n
2
No R, C and f as part of the expression. Based on assumption that these values

will not change during the conversion.
IX - 80
Analog Interfaces
411
V Dual Slope ADC - Comments

Clocking the DV register may be performed to make the data as transient or persistent.
See the questions at the end of this section of the notes. (starting on page 431)
Output biased low and Vref VAnalog
Advantages:
Output does not depend on the precise values of R and C
Output does not depend on the precise value of f (It must be stable during one
conversion, but drift between conversions is tolerable)
Fairly simple to build.
Disadvantages:
Completion time is a function of the fraction
VAnalog
Vref
as the second slope takes that
long to complete its path to 0V (2n < Completion Time 2n+1 clock periods)
The number of clock cycles doubles with each 1-bit increase in resolution.
Popular at low-speed low-cost applications.
IX - 81
Analog Interfaces
412
A/D Converter Specifications and Errors

More or less the same issues as DACs: DAC specifications (starting on page 354) .
resolution, or quantization error
dynamic range the ratio of the largest value that can be converted to the smallest
step size. Eg. 10-bit ADC, with an input range from 0 - 4volts. Therefore the
quantization step is
4V 0V
210 1
or 3.9062 mV. Thus the dynamic range is
4.0 V
3.9062 mV
or
1023. (20 log 1023 60 db)

accuracy.
Missing Code: It may be that some digital values can never be generated due to some
errors in the ADC. If this is the case, the missing values are referred to as missing
codes.
offset errors, gain errors, linearity errors and
conversion time.
A/D Converter Specifications and Errors
IX - 82
Analog Interfaces
413
Time Varying Signals

Seldom do computers have to monitor signals that do not change. A changing signal may
cause the converter problems.
Converter Aperture Time: The (maximum) time that the converter output (result)
is sensitive to changes in the analog signal.
Analog Signal
Time
ADC Aperture Time
ADC Aperture Time
1/fSample
ADC Aperture Time
1/fSample
adcaperture1.
IX - 83
Analog Interfaces
414
Time Varying Signals Issues

A sample-and-hold circuit is often used to ensure that the ADC input signal does not
change during the converter aperture time.
The frequency of a periodic signal impacts the required sampling rate.
Nyquist Sampling Rate: If a time varying signal contains components of significant
amplitude only below f Hz, then a sample frequency of greater than
2f Hz
will suffice to reconstruct the frequency without generating lower frequency aliasing
signals. Or, inverted, if you sample a signal at f you will only be able to work with
signals below f /2 in frequency.
IX - 84
Analog Interfaces
415
Sampling of a Time Varying Signal Without a Sample-and-Hold Circuit

Motivating Example: What is the max frequency (fM ax) of a time varying signal that can
be sampled without adding a sample-and-hold circuit?
For simplicity, assume we are to sample a sine wave of some frequency.
The worst case would be at the point of maximum rate of change of the applied signal.
1.5
1
VPeak
0.5
V (t) = Vpeak sin(2f t)

dV
= 2f Vpeak cos(2f t)
dt
M ax Slope = 2f Vpeak
Max
Slope
0.5
1.5
SineWave.
IX - 85
Analog Interfaces
416
Sampling of a Time Varying Signal Without a Sample-and-Hold Circuit

Often it is assumed that the signal will change by no more than 14 LSB while the conversion
is taking place. Suppose that a 12-bit converter is used and that it requires 10 s to convert
a signal in the range of 10 V peak-to-peak (I.e., VP eak = 5 V). The converter aperture
time is 10 s. The amount that the input can change in 10s is 14 LSB.
1
4 LSB
= 14 212101 ' 0.6 mV
Thus there can be at most 0.6mV change in 10s (at the steepest slope).
V

= 2fM axVP eak

t M ax

0.6 103
= 2fM axVP eak
6
10 10
IX - 86
Analog Interfaces
417
Making a single sample of a varying signal without a sample-and-hold circuit

Or
fM ax =
0.6
2 5 10 103
0.6
101
2 Hz
For this system, without a sample-and-hold circuit we are limited to 2 Hz, despite a 100 kHz
converter!
IX - 87
Analog Interfaces
418
Sample-and-Hold Overview
shover.
Sample
Time Varying
Signal
Sample
and Hold
Sampled
Signal
A/D
Converter
Binary
Value
IX - 88
Analog Interfaces
419
Sample-and-Hold Overview
When does conversion start? (at the

start of start of conversion? at the end
of start of conversion? ... consider
the various designs
to date.)
Note the relationship between the
converter aperture
(Start of Conversion to CC) and
the
sample-andhold aperture time
(limited to the duration of the sample
signal).
Sample
Time Varying
Signal
Sample
and Hold
shover2.
Start of Conversion
CC
Sampled
Signal
A/D
Converter
Binary
Value
Sout
Time Varying
Signal
Sample
Sout
Start of Conversion
Conversion Complete (CC)
IX - 89
Analog Interfaces
420
Fixed sample rate block diagram
Sample/
Hold
A/D
Converter
CC
Digital
Value
Sampled
Analog
Signal
Analog
Signal
shover3.
Parallel
Port
Soc (or other)
Sample
CPU
Memory
Data Valid to Read
Sample
Period
SoC
Sample
CC
IX - 90
Analog Interfaces
421
Sample and Hold Circuits

A/D Converters require a stable input voltage during conversion. For our purposes consider
stable to mean that the value remains within 14 LSB (or some other fraction) for the time
required to perform the conversion.
IX - 91
Analog Interfaces
422
(From Circuit)
adc12.
Vin
Buffer 1
Vc
C
Sample
Vout
Buffer 2
Buffer 1 isolates the analog circuit from C when Q is on
To A/D Converter's
VAnalog
A sample-and-hold circuit is used to hold the input voltage constant during conversion
(ideally).
Buffer 2 isolates the converter from C.

When Q is on, Vc tracks Vin.
When Q is off, Vc retains the most recent Vin level.
Therefore Vout retains the most recent Vin value and can be used as the A/D Converter
input signal.
A sample-and-hold circuit may be included as part of the A/D Converter.
IX - 92
Analog Interfaces
423
Sample and Hold Circuit Errors

1. during sampling
2. during the sample to hold transition
3. during hold
4. during the hold to sample transition
Error Band
Vin
Droop Rate
Vout
4
t_acq
Ck
t_hs
Hold
Sample
sample1.
IX - 93
Analog Interfaces
424
1. During Sampling
Errors (in the input buffer)
offset the output for a zero input may not be exactly zero. ( 12 LSB for a given
temperature.)
non-linearity
non-unity gain.
IX - 94
Analog Interfaces
425
Performance Issues
The settling time is the time to attain a good estimate for the final value given a full
scale step at the input to within a specified error. In this case it is the time to couple the
voltage across the capacitor (through the two buffers) to the A/D input.
Vin
Vout
Bounds
Settling Time
adc13.
IX - 95
Analog Interfaces
426
2. During Sample-to-Hold Transition

Sample and Hold Aperture Time: the time required for Q to turn off once the hold signal
is asserted. (Tof f ).
Jitter
Sample-and-hold
Aperture Time
Toff
Toff
Sample
Hold
apertur.
This may contribute to sample-and-hold offset.
IX - 96
Analog Interfaces
427
2. During Sample-to-Hold Transition (Cont.)

(Sample and Hold) Aperture Uncertainty : the change in time between the command to
turn Q off and the actual time Q turns off. (Jitter in the figure) Changes in Tof f
Causes:
variables in the delay in turning off
variation in sample/hold transition.
variation in either of these caused by changes in temperature.
Effect: If sampling a signal at regular intervals (TSample(i) ) then you cannot miss a
sample by the time required for the signal to change by more than a fraction of the
LSB value.
IX - 97
Analog Interfaces
428
2. During Sample-to-Hold Transition - Example

If you need to sample a 10 kHz signal, using the 10 s converter described above how
much (sample and hold) aperture uncertainty could be tolerated?
Based on Murphys Law assume that the uncertainty occurs at the maximum rate of
change point. (Recall
1
4
LSB is 0.6 mV in the example.)

V
t
0.6 103
Taperture
Taperture
= 2f VP eak
= 21045
uncertainty
uncertainty
0.6 103
=
105
2 109 = 2 ns
Thus the uncertainty cannot be larger than 2 ns.

IX - 98
Analog Interfaces
429
3. Errors During Hold Time

Droop: A drop in the signal out of the sample and hold circuit. It is caused by discharge
of C due to:
input bias currents (in the output buffer).
leakage back through the switch
leakage across C
Vin
Ideal
Vout Actual
Sample/Hold
adc14.
Feed through leakage forward through the switch.

Hold Settling time (t hs in earlier figure) ... Time to stabilize after hold has started.
IX - 99
Analog Interfaces
430
4. Hold to Sample Transition

Acquisition Time: The time required before the capacitor voltage is within a specified
percentage of the final value (as distinct from the settling time which worries about the
voltage into the A/D converter, as opposed to the voltage across the capacitor.)
t acq shown on figure (starting on page 423) .
At times the input and stored values may appear to be close but still there may be transients
when sample starts due to stray inductance and capacitance that may be present in
the circuit.
IX - 100
Analog Interfaces
431
Questions of Interest: Detailed Answers Required

1.
For each of the converters examined this term, summarize if they result in biased high, biased low or unbiased results.
2.
For each of the Analog-to-Digital converter types examined this term, describe the impact of applying an input VAnalog larger
than the reference voltage.
3.
For each of the Digital-to-Analog converter types examined this term, describe the impact of an error of 10% in one of the
resistors in the design.
4.
The dual slope converter shows a register (DV) and indicates that depending on how it is clocked, the data will be either
transient or persistent. Assume that the converter itself runs continuously. Give the clock circuit for the DV register so that
it will provide persistent data, using a consumer sensitive model of synchronization.
IX - 100.1
Analog Interfaces
432
Note: Terms using in Analog Interfaces

Terms:
Comparator (page 327)

Inverting Amplifier (page 330)
Non-Inverting Amplifier (page 336)
Non-Inverting Buffer (page 337)
settling time (page 338)
slew rate (page 338)
Quantization (page 339)
LSB (page 339)
Multiplying DAC (M-DAC) (page 353)
Resolution (DAC and ADC) (page 354)
Precision (DAC and ADC) (page 354)
Accuracy (page 354)
Range (page 355)
Dynamic Range (page 355)
Offset Error (page 356)
Gain Error (page 357)
Differential Non-Linearity (DNL) (page 359)
Monotonicity Error (page 360)
Integral Linearity (page 361)
Power supply rejection ratio (page 363)
Glitch Impulse (page 365)
Missing Code (page 412)
Converter Aperture Time (page 413)
Nyquist Sampling Rate (page 414)
Sample and Hold Aperture Time (page 426)
(Sample and Hold) Aperture Uncertainty (page 427)
Droop (page 429)
Acquisition Time (page 430)
IX - 100.1
Section X:
Buses - Data Transfer
f2014-1.0
434
Buses - Data Transfer: Section Contents

Introduction (starting on page 436) Definitions of the terms and times used in this section of the notes including skew time,
propagation delay, select time and access time. There is also a discussion of the features common to all bus structures.
Synchronous Bus Transfer (starting on page 440) The synchronous bus is used as the basis for the other bus data transfer structures
in subsequent subsections. The single most important assumption/requirement for a synchronous bus design is that during every
transfer there are fixed, known points in time during in the transfer cycle where events occur. The design must be such that at these
event times all interfaces attached to the bus observe the same signal values on all bus lines. All transfers on a synchronous bus
require the same length of time. Ladder and timing diagrams are used to convey the information.
Asynchronous Bus Transfer (starting on page 453) An asynchronous bus transfer technique uses handshaking to allow synchronization
at times compatible with the master and the slave. The asynchronous bus is the first situation that considers, in detail, the fact that
signals have different values at different places on the bus at the same instant.
Partially Interlocked Asynchronous Buses (starting on page 464) The fully-interlocked asynchronous bus of the previous section is
extended to reduce the number of bus interactions required to synchronize a transfer.
Semi-Synchronous Bus Transfer (starting on page 467) Buses based on a semi-synchronous bus data transfer technique are very
common in microprocessor systems. The semi-synchronous bus provides a technique to permit interaction with slower interfaces.
This technique has only limited impact on the faster transfers.
Split Cycle Protocols (starting on page 471) The split cycle protocol provides improved performance in environments where there
are multiple bus masters. Each bus master can make a request of the slave, release the bus, and then receive the response from the
slave at some later time. This leaves the bus available for use by other interfaces during the slave access time.
Section Contents: Buses - Data Transfer
X - 0.1
435
Buses Resources
Vranesic and Zaky Section 6.2 (Synchronous Bus, Stone 3.2, Hamacher Vranesic and Zaky
Section 4.5),
V&Z Section 6.8 (Asynchronous Bus Example, Stone 3.2, 3.4, HV&Z Section 4.5 5th
edition),
V&Z Section 6.10 (Semi-Synchronous example 68000), HV&Z Section 4.5 5th edition,
V&Z Section 11.1 (Introduction)
V&Z Section Bus Arbitration (Stone 3.3, 3.7), HV&Z Section 4.4 5th edition
V&Z Section 11.2, 11.4 and 11.5 (Examples, Stone 3.6),
Mano (Digital Design) Asynchronous Sequential Logic, The chapter number varies with
edition. This reference is for the ECE 224 only.
Resources
X-1
436
Introduction
Bus Operations
Bus Signal Groups
Data transfer (Section X) (starting
Data transfer
on page 433)
address and data (information)
Bus arbitration (Section XI)
control: synchronization (time)
(starting on page 476)
and direction (There may be other
Direct Memory Access DMA
issues to control)
Section XII (starting on page 545)
Arbitration (select master)
Other signals (interrupt)
Special Topics
Timing of sets of signals (propagation delay, skew time, address decoding
time)
Transmission line effects (later in the
course)
What Makes a Wire Part of a Bus?
Where are buses found in Digital Systems?
Introduction
X-2
437
Data Transfer Synchronization Techniques

Synchronous Data Transfer : The transfer of data between communicating entities with
a common view of time. In this case there is a global clock and data is transferred at a
specific point in the clock period. Also all transfers are of fixed duration (one clock period.
There is no feedback from the consumer to the producer of the data to alter the rate of
transfer or to alter the duration that the data is valid.
Asynchronous Data Transfer : The transfer of data between communicating entities with
different views of time. In this case there is no global clock, and there is a mechanism to
permit variable transfer times. This mechanism may be either fully or partially interlocked.
Semi-synchronous Data Transfer : The transfer of data between communicating entities
which have a common view of time (a global clock), however permit variable transfer
times. The transfer times are an integral number of clock cycles in length where The
actual number of clock cycles is somewhat under the control of the slave.
Split-cycle Data Transfer : The transfer of data between communicating entities which
only permits a transfer from the producer to the consumer. As a result, read transfers are
accomplished in two cycles each of fixed duration, one in each direction. Write transfers
are accomplished in a single transfer.
Introduction
X-3
438
Note: Introduction to Bus Terminology

Bus terminology was introduced in Chapter V of the notes and the slides have not been repeated here, although the material naturally
fits here in the flow of the notes.
The notes are found at bus terminology (starting on page 136) .
In bus terminology the following terms were defined: Access Time (tAccess ), Store Time (TStore ), Skew Time (TSkew ), Margin Time
(TM argin ), Address Propagation delay (tP A , Data Propagation delay (tP D ), Bus Propagation delay (tp ), Setup Time (TSetup ), and
Hold Time (THold ).
Introduction
X - 3.1
439
Bus Operation Sequence

There is more to a bus transfer than simply applying address and data.
Typical sequence (read):
[MASTER] Get bus (arbitration see next section)
[MASTER] Apply address value and direction control signal(s) (read) to address lines
[MASTER] Be sure slave is ready
[SLAVE] Provide data
[MASTER] Accept data
Introduction
X-4
440
Synchronous Bus Transfer - Block Diagram (Read)
Address
and
Timing
Decoder
(Centralized ATD)
A0-Ae-1
(Chip) Select
or
Device Enable
Decentralized
ATD
Register
Select
Address
Lines
Ae-Ae+m-1
synchreadblock.
CPU/Bus Master
Consider the following structure

Clock and R/W
have been used
for signalling in
this case.
Device
Interface
R/W
Device
Clock
Data Lines
Internal Signals
for bus
Enable
Output
Data
Bus
X-5
441
Synchronous Read (Single Clock) - Ladder Diagram

synch3 ladder
Time at
Master
CK1

Single Clock
Time at
Slave
Address and
t +t
Control (Clk, R/W) PA Skew
Master Edge
tmargin1
Decode address on bus and select slave
tmargin2
tSetup
tHold
Slave Edge
tSelect
t Access
tPD+ tSkew
Slave removes data
Note: Next cycle must be delayed by

tHold.
Time at
Master
Time at
Slave
X-6
442
Synchronous Read (Single Clock) - Timing Diagram
Synchronous Read Bus Transfer (Master and Slave Timing the same at the edges)
Phase 1
tPA tSkew
Valid Read Address
Address
R/W
tSelect
Address
Decoded
>0
Enable
Output
tPD+tSkew+tAccess
Valid Read Data
Design Margin
tM1
tM2
tHold
Minimum
Phase 1
Data
Master Edge
Phase 2
tSetup
Clock
Slave Edge
tSelect+tAccess+tSkew+tPD+tSetup+tM2
One Bus Cycle
synch3.
X-7
443
Effects that limit bus bandwidth

For a READ operation (For a single clock synchronous bus)
Following the Master (Rising) edge of clock
propagation delay for the address going to the slave (tP A)
bus skew delay (tSkew )
tminimum,
phase1
Read
= tP A + tSkew
Following the Slave (Falling) edge of the clock

address decode time at the slave (tSelect)
response time (Read time) of the slave device (tAccess)
propagation delay for the data along the data bus (tP D )
skew delay (tSkew )
setup time (tSetup) at the master latch
tminimum,
phase2
Read
= tSelect + tAccess + tSkew + tP D + tSetup
X-8
444
Synchronous Read Minimum Bus Cycle Time

Recall: In the case of consecutive read cycles, the second cycle cannot start until tHold
following the start of phase 1. Thus
tminimum,
phase1
Read
= tP A + tSkew + tHold
These expressions can be used to derive a minimum time for a synchronous read bus cycle.
Assume: a single cycle clock and that the access time for the slowest interface permitted on the
ax
bus is tM
Access
Optimized,
Tbus
cycle
Synchronous, Read
= tminimum,
phase1
Read
+ tminimum,
phase2
Read
ax
= tSetup + tSelect + 2tSkew + tHold + tP A + tP D + tM
Access
The optimized clock is unlikely to have a 50% duty cycle.
X-9
445
Synchronous Read (Two Clocks) Reminder
Asymmetric 1 Phase Clock
2 Phase Clock
2phasesynchronous ladder2
X - 10
446
Synchronous Read (Two Clocks) - Ladder Diagram
Address and
Control
Time to Decode address on bus
t
Select
tmargin2
Time for
arbitration
see next
section
tSetup
tHold
tPA+ tSkew
t
margin1a
tAccess
tmargin1b
tPD+ tSkew
Remove address and

control
Place new address and
control on signal lines
CK2
CK1

Two Clocks
In this model it is more obvious that the

address can be removed in time for the
transfer that follows
tmargin1a is the margin to start the access and
tmargin1b is the margin to perform the access
In this case the access is performed
before the Slave edge
Note: In this case, the data is sampled by
the master on the rising edge of CLK 2 when
CLK1 is low
synch3 ladder2
X - 11
447
Address
and
Timing
Decoder
(Centralized ATD)
(Chip) Select
or
Device Enable
Decentralized
ATD
Register
Select
Ae-Ae+m-1
Address
Lines
CPU/Bus Master
Synchronous Bus Transfer - Block Diagram (Write)
A0-Ae-1
Device
Device
Interface
R/W
Clock
Data Lines
Data in
Register
Q
Reg
Clock
n-bit (D) Register

Data
Bus
synchwriteblock.
X - 12
448
Synchronous Write (Single Clock) - Ladder Diagram
Address, data
and control
CK1

Single Clock
tp+ tSkew
tmargin1
tSelect
t Store
tmargin2
New address and control
tSetup
tHold
Note: the next cycle can start sooner

than in the case of a Read.
synch4 ladder
X - 13
449
Write Bus Transfer

Phase 1
Clock
Slave Edge
Phase 2
Master Edge
t
tPA Skew
Valid Write Address
Address
tSelect
R/W
Address
Decoded
tStore+
tMargin2
TSetup
tHold
Data
tPD+tSkew
Reg Clock
synch4.
Note: RegClock = (R/W Clock AddressDecoded)

X - 14
450

In the figure below:
Clock1 = (R/W Clock AddressDecoded)
Clock2 = RegClock = (R/W Clock AddressDecoded)
Address Decoded
R/W
Clock
Clock 1
Clock 2
clockderived.
X - 15
451
Synchronous Timing - Write (Two Clocks) - Ladder Diagram
One Bus Cycle
CK2
address, data
and control
CK1

Two Clocks
tp+ tSkew
tmargin1
tSelect
tStore
tmargin2
tSetup
tHold
Next Address and Control

synch4 ladder2
X - 16
452
Comments on clock rate

Limits on Read Clock Rate
Limits on Write Clock Rate
For our purposes, a pure synchronous system is constrained to a single clock period and
Optimized,
thus the slower of the two times is taken as the time, Tbus
cycle
Synchronous, Read
(starting
on page 444) .
X - 17
453
Asynchronous Buses
Synchronous buses must run at the speed of the slowest interface/device.
Asynchronous schemes permit the speed of the bus to be compatible with a wide variety
of device/interface speeds.
Asynchronous Bus Transfer
X - 18
454
A0-Ae-1
R/W
(Chip) Select
or
Device Enable
Decentrailized
ATD
Register
Select
Ae-Ae+m-1
Address
and
timing
Decoder
(ATD)
Address
Lines
CPU/Bus Master
Asynchronous Bus Transfer - Block Diagram (Read)
Device
Interface
Master
Device
Slave
Data Lines
Internal Signals
for bus
Enable
Output
Data
Bus
asynchreadblock.
X - 19
455
Fully Interlocked Asynchronous Read - Ladder Diagram

asynchtime.
At Master
Place Address and
Control sig. on bus
tSkew+
tmargin
Assert Master
At Slave
Time A
Time
Time B
Act on address
tSelect
tAccess
tSkew+
tmargin
Clock Data in
Enable data and

Assert Slave
Time C
Time D
Time E
Deassert Master
Deassert Address
and R/W
Deassert Slave
Start next cycle

Time F
X - 20
456
Note: Fully Interlocked Asynchronous Read - Alternative Ladder Diagram
If there are
few
possible
masters, then it
would also be
reasonable
to
allow for tSkew
in the masters.
It would be
possible to place
the
responsibility for tSkew
in master and
slave as shown.
If the responsibility for tSkew
were
to
be
placed at the
slave, it would
likely increase
the complexity
of the slave.
asynchtimeslave.
At Master
Place Address and
Control sig. on bus
tSkew+
tmargin
Assert Master
At Slave
Time A
Time
Time B
Enable data
Act on address
tSelect
tAccess
tSkew+tmargin
Assert Slave
Clock Data in
Deassert Master
Time C
Time D
Time E
Deassert Slave
Start next cycle
Time F
X - 20.1
457
Fully Interlocked Asynchronous Read - Timing Diagram, at Master
Asynchronous Bus READ Operation (At the Bus Master)

Skew
Address
Control
Master
/Master
Slave
/Slave
Data
Skew,
and margin
Skew, margin and setup

(latch on D)
Select time +
READ time (access time)
+ 2 Propagation
Delays
Valid Data
READ
D
2 more
Prop. Del.
asynch1.
Note, time D is determined within the master.
X - 21
458
Fully Interlocked Asynchronous Read - Timing Diagram, at Slave
asynch2.
Asynchronous Bus READ Operation (At the Bus Slave)

Address
Control
Master
Slave
Data
Valid Data
Access Starts
Master signal is
driven by the master
interface. The master allows for all bus
skew!!
Slave signal is driven
by the slave interface. A much simpler signal, as it does
not use the bus characteristics to constrain the timing of
its signals.
tSelect +
t Access+
tmargin
Access must be complete and the data enabled to the bus lines
before Slave asserted.
X - 22
459
Fully Interlocked Asynchronous Write Transfer At Master
Asynchronous Bus WRITE Operation (At the Bus Master)

Address
Control
Data
Master
Slave
Skew and
margin time
A
B
Select time + Setup time +

Hold time +
2 Propagation Delays
2 more
Prop. Del.
E
F
asynch3.
X - 23
460
Fully Interlocked Asynchronous Write Transfer At Slave
In this case the rising edge of slave

(falling /slave) could happen using
either of the following models.
(Optimistic Design Alternative) Assume that once the
address decoded, save the
data in a temporary register
until it can be written into the
correct location (tStore later).
or
(Conservative Design Alternative) Await until the data is
correctly stored in the final location and then inform master. If this strategy is used,
then the delay between B and
C in the previous slide would
be increased by tStore.
asynch4.
Asynchronous Bus WRITE Operation (At the Bus Master)

Address
Control
Data
Master
T
T
Store+ Setup
One version of
RegClock
Slave
TSelect+
TMargin
Optimistic
Slave
Conservative
Slave
X - 24
461
Factors Limiting Bus Speed

Skew time: must be known by either master or slave, depending on bus implementation
Propagation time: unknown ... bounds?
Setup time: may need to be known by master
Hold times: known by master or slave depending on owner of latch.
Other device times: access time
X - 25
462
Minimum Read Times: Asynchronous and Synchronous

Consider the time for an optimized, fully interlocked, asynchronous bus. See timing diagram
(starting on page 457) for more information.
Asynchronous,
Tbus
cycle
F ullyinterlocked, Read
= tSkew + tSelect + 2 tp + tAccess

+tSkew + tSetup + 2 tp
= 2 tSkew + 4 tp
+tSelect + tSetup + tCurrent
Access
T ransf er
Asynchronous, Read
T ime Averaged
(An average value for Tbus
could
be
derived
from
t
)
Access
cycle, Average
Recall that the optimized synchronous read cycle was:
Optimized,
Tbus
cycle
Synchronous, Read
= 2 tSkew + 2 tp
aximum
+tSelect + tSetup + tHold + tM
Access
X - 26
463
Synchronous vs Fully Interlocked Asynchronous Transfers

Asynchronous
slower than an optimized synchronous bus in situations where all of the interfaces
attached to the bus have similar performance characteristics. (1 transfer requires at
least 4 tp)
supports a wide range of device/interface response times
verifies real values are being read. In the event of an attempt to access a non-existent
location, there is usually a time-out for the bus.
asynchronous transfers treat the data as persistent
Synchronous
transfer rate is limited by the slowest interface attached to the bus
synchronous transfers are faster if all of the attached interfaces have comparable
performance characteristics
synchronous transfers treat data as transient
X - 27
464
Partially Interlocked Asynchronous Bus Transfers
Based on constraining slave signals to a

fixed duration.
Non-interlocked
transitions
must
obey timing constraints.
Reduces the number
of bus propagation
delays to 2 from 4.
Consider
creating
your own ladder
diagram for this
problem.
There
are some interesting considerations
related to Master
and Slave timing
relationships.
partial
Address
and
Control
tSkew +
tmargin
tSelect+tAccess+
2*tp
Master
tDelay(+ tmargin)
(> tSetup+tSkew
+tHold)
tSetup+
tSkew+ tHold+
tmargin tmargin
Slave
Data
Partially Interlocked Asynchronous Buses
Fixed
Duration
X - 28
465
Fully Interlocked vs Partially Interlocked Asynchronous

Consider the time for a fully interlocked, asynchronous bus. See previous derivation (starting on
page 462) .
Asynchronous,
Tbus
cycle
F ullyinterlocked, Read
= 2 tSkew + 4 tp
+tSelect + tSetup + tCurrent
Access
T ransf er
as compared to the partially interlocked cycle time (also based on the actual transfer time).
Asynchronous,
Tbus
cycle
P artiallyinterlocked, Read
= tSkew + tSelect + 2 tp + tCurrent

Access
+tDelay
T ransf er
This version assumes that tDelay can be set to any value.
X - 29
466
Synchronous, Fully-Interlocked Asynchronous and Partially-Interlocked

Asynchronous
0.5 52.5
106
133.5 89.5 100 110
0.6
62
115
133.5
99 109 119
0.7 71.5
125
133.5
109 119 129
0.8
81
134
133.5
118 128 138
0.9 90.5
144
133.5
128 138 148
153
133.5
137 147 157
100
80
60
40
0
90 100
96
10
133.5
43
.5
0.4
90
91
81
81
.5
133.5 70.5
71
0.3 33.5 86.5
80
62
81
.5
71
52
61
77
43
133.5
24
100
.5
0.2
120
33
72
Synchronous
Partial(20)
140
24
62
160
.5
Partial(30)
133.5 51.5
Asynchronous
Partial(10)
Partial(30)
14
Partial(20)
0.1 14.5 67.5
Synchronous, Asynchronous (Fully and Partially

Interlocked)
Average Bus Cycle Time
Partial(10)
Synchronous
Average
as
Fraction
of Max
Avg Access
tAccess
tSetup
tHold
tSelect
tp
tSkew
tDelay
Asynchronous
Min AverageMax
5
100
1
0.5
2
10
5
10 20 30
Average Access Time

synchasynch.pdf
X - 30
467
Semi-Synchronous Bus Transfer

Hybrid of synchronous and asynchronous techniques
asynchronous transfers require 4 bus propagation delays in addition to any time required by the slave to respond to the request by the master
synchronous transfers require all transfers to be at the rate specified by the bus clock
semi-synchronous bus data transfers are implemented if most transfers are fast. If a
device is slow, it is possible to slow the transfer if the interface can notify the master
that the transfer cannot be completed at the time expected.
Transfer timing is based on 2 signals
Clock from the bus and
Wait (or Ready or Hold) from the Slave.
Only constraint is that the (slave) interface must be able to remove the Ready (or assert
a Wait) in time to stop the master from proceeding to read the data.
Speed of synchronous transfers and the flexibility of asynchronous transfers
X - 31
468
Semi-Synchronous Read Ladder Diagram
address and
control
tPD+ tSkew
tPA+ tSkew
tmargin1
tSelect
tAccess
Notify Master that

The slave is ready
tmargin2
tHold
Notify Master that

The slave is not ready
CK1
Semi-Synchronous Bus Read

One Clock
tSetup
Next master edge marks end of cycle

Remove address,
and control
semi synch ladder2
X - 32
469
Timing Diagram (Single Clock)
Phase 1
Clock
Slave Edge
Phase 2
Master Edge
Read Bus Transfer

Phase 1
Slave Edge
Phase 2
Master Edge
Phase 1
Slave Edge
Phase 2
Master Edge
tPA tSkew
Valid Read Address
Address
R/W
tSkew
Address
Decoded
Data
Enabled
Valid Data
Data
prior to Master Edge

Ready, /Wait ..
semisyn1.
X - 33
470
Semi-Synchronous Write Ladder Diagram
address, data and

control
tPD+ tSkew
tPA+ tSkew
tmargin1
tSelect
tStore
Notify Master that

The slave is ready
tmargin2
tHold
Notify Master that

The slave is not ready
CK1
Semi-Synchronous Bus Read

One Clock
tSetup
Next master edge marks end of cycle

Remove address,
and control
semi synch ladder2w
X - 34
471
Split Cycle Protocols

In the previous bus control strategies the bus was occupied by the master until the transfer
is completed.
Consider the case if there is a very slow device on the bus, but there are several possible
bus masters.
One option is a split cycle protocol
Writes are 1 quick transfer by their nature
Reads transformed into two write cycles
1. master sends address to the slave and requests a Read of that location
2. master releases the bus
3. slave (I.e., the slave in the original transfer) requests/gains access to the bus and
Writes the previous request result back into the original master.
Note a split-cycle protocol can implemented using: Synchronous, Asynchronous or SemiSynchronous buses.
X - 35
472
Split Cycle Transfers - Multiple Master Structure
Processor
Processor
Memory
Memory
split.
Memory
Memory
X - 36
473
Split Cycle Transfers - Ladder Diagram
Split Cycle Protocol Read

Synchronous Single Clock Bus
Address and
Control
CK
tp+ tSkew
tmargin1a
tSelect
t
margin1b

Any number of clock cycles
(Original) Slave becomes bus master
tAccess
tp+ tSkew
tmargin2
tSetup
tHold
split ladder
X - 37
474
Questions of Interest: Data Transfer Questions
Terms and times discussed in this section include: Synchronous Data Transfer, Asynchronous Data Transfer, Semi-synchronous
Data Transfer, Split-cycle Data Transfer, Address propagation delay, Data propagation delay, Bus propagation delay, Setup
Time, Hold Time, Select Time, Margin Time, Access Time, Store Time and Skew Time.
Engineering Questions.
Select any two of the bus structures and determine under which circumstances each of them would be preferred.
Either the Master or the Slave in a fully interlocked asynchronous bus could be responsible for de-skewing, that is
allowing for the skew time. Give circumstances when the slave should also be responsible for dealing with skew. Give
circumstances when it should be only the responsibility for the bus master.
Draw a timing diagram for a semi-synchronous bus write transaction and label all timing constraints.
List all signal dependencies in a fully-interlocked asynchronous bus.
Under what circumstances might a split cycle protocol be beneficial?
Why is it unlikely for semi-synchronous buses to support split cycle protocols?
(or) In the notes it was mentioned that a split-cycle bus can be constructed from: Synchronous, Asynchronous or SemiSynchronous buses. Why is an implementation based on synchronous synchronization the most reasonable?
Can a single wire have skew?
X - 37.1
475
Note: Terms used in Buses Data Transfer

Terms:
Synchronous Data Transfer (page 437)

Asynchronous Data Transfer (page 437)
Semi-synchronous Data Transfer (page 437)
Split-cycle Data Transfer (page 437)
X - 37.1
Section XI:
Buses - Arbitration
f2014-1.0
Buses - Arbitration
477
Buses - Arbitration: Section Contents

Introduction (starting on page 479) The general needs of arbitration are examined. The terminology for devices and interfaces and
arbitration is defined.
2-Wire Daisy Chain (starting on page 484) The first of the daisy-chained arbitration techniques is examined in more detail than
the other techniques. This subsection includes the detailed consideration of distributed digital systems. Of particular note is the
limited information that is available at each part of the distributed arbitration system to make the arbitration decisions. This section
considers a design example translating the needs of the arbitration system to the specification of a fundamental mode (asynchronous)
circuit.
3-Wire Daisy Chain (starting on page 519) The 3-wire arbiter structure presentation does not provide design details to the same
level as the 2-wire material. The material describes a system that permits global knowledge of the state of the shared resource (the
bus), while permitting a distributed arbitration system design. The coverage includes several detailed timing examples.
4-Wire Daisy Chain (starting on page 527) The 4-wire distributed arbitration technique is a modification of the 3-wire technique.
It permits the bus arbitration and the bus usage to be overlapped. The presentation emphasizes the differences between the 3-wire
and 4-wire and examines a small number of cases.
Summary of the Operational Characteristics of Daisy-Chained Bus Arbitration (starting on page 529) The characteristics of the
various daisy-chained arbitration techniques are summarized. In addition there is a more formal examination of the priority provided
by the various schemes. One of the key points is that there exists a window of time in which the arbiter with requests pending from
two devices will select the one furthest from the central arbiter to be the next bus master. The size of this window can be used to
compare the techniques.
Non-Daisy-Chained Bus Arbitration (starting on page 541) The non-daisy-chained arbiter is presented to illustrate that it is not a
requirement to have daisy-chained wiring to make a unique arbitration decision.
Section Contents: Buses - Arbitration
XI - 0.1
Buses - Arbitration
478
Buses Arbitration Resources

V&Z. Sections 7.6, Plus Examples in Chapter 11
Stone: Section 3.7
HV&Z (ECE 222), Section 4.4 (5th Edition)
Mano (ECE 124) Asynchronous Logic Chapter (Chapter 9)
Resources
XI - 1
Buses - Arbitration
479
Introduction
Previous discussions have assumed 1 Master and 1 (active) Slave.
Bus Arbitration: A process that seeks to select exactly 1 Master from one or more devices
requesting to be the bus master.
Examine:
distributed, daisy chain-based, 2-Wire,
distributed, daisy chain-based, 3-Wire
distributed, daisy chain-based, 4-Wire and
decentralized, parallel.
Introduction
XI - 2
Buses - Arbitration
480
Distributed Wiring Structures
Daisy Chain
Wiring structures play a role
in the bus arbitration scheme
alternatives
Star
busringstar.
Introduction
Bus
XI - 3
Buses - Arbitration
481
Purpose of Arbitration
Goal Unique Selection.
possible (not necessarily consistent) sub-goals
fair (round robin, rotating priority, first come first serve)
cheap
unfair (fixed priority)
Non-pre-emptive arbitration: Once a master has started using the bus it will continue
to use the bus until completion. Specific bus structures may place limits on the
maximum number of cycles or the maximum time that a master may keep control of
the bus.
This term we will not consider preemptive arbitration.
Introduction
XI - 4
Buses - Arbitration
482
Terminology for Distributed Arbitration

Central Arbiter (CA): The portion of the arbitration system responsible for detecting that
there is a bus request and causing a grant to be issued, if appropriate.
Distributed Arbiter (DA): The portion of the arbitration system that is repeated in each
device interface that has a requirement to become a bus master at some time.
the remainder of this section deals with alternative methods for using this general structure.
Introduction
XI - 5
Buses - Arbitration
483
Interconnection with the Other Interface Components

interface1.
Interface Connections for a 3-wire Daisy-chain1 Connected

Bus Arbitration Scheme
Address
Data
Control
CA
DA
Previous
Discussion
Not able to
become bus
master
DA
Note: Some interfaces

may not have DAs.
Device Interface
CPU
Device
Note 1: Several other techniques are to be examined this term, this is one
example to demonstrate the relationship of the arbitration circuitry to the
rest of the interface.
Introduction
XI - 6
Buses - Arbitration
484
2-Wire Daisy Chain
Request_1
Grant_1
and the rest
of the
Interface
Bus_Request_2
Rout
Unit 2 Rin
Distrib.
Arbiter
Gin
Gout
Request_2
No
Request
Bus_Grant_2
Bus_Grant_0
Central
Arbiter
Bus_Request_1
Rout
Unit 1 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Grant_1
Bus_Request_0
Cheap, easy conceptually ... hard to make work.
Grant_2
and the rest

of the
Interface
arbcct1.
2-Wire Daisy Chain
XI - 7
Buses - Arbitration
485
Design of One 2-Wire Distributed Arbitration Unit

How to describe the problem?
Straightforward Cases no arbitration required.
Case A (IDLE): no one lower in the chain requesting use of the bus, and local device
interface not asking to use the bus.
Rout = Rin (= 0) and Request = 0
Gout = Gin (=0)
Case B (LOCAL ONLY): if only the local device interface (i) requests service.
Requesti goes to a 1 Rout goes to a 1. (and thus BusRequesti1 also goes to
a 1).
later Gin 1 (I.e. BusGranti1 goes to 1), the ith arbiter claims bus and informs
the interface with a 1 on Granti.
Case C: if only a device to the right (lower priority?) wants to use the bus.
Rout tracks Rin
Gout tracks Gin
2-Wire Daisy Chain
XI - 8
Buses - Arbitration
486
Design of One 2-wire Distributed Arbitration Unit

Cases requiring arbitration
Case D: while the local interface is using the bus a request from the right occurs
When the local interface is finished what to do?
Case D1: forward Grant to the right when local device finished, (not a good solution)
Case D2: wait for new arbitration cycle. (a better solution)
Case E: after interface to the right has raised Rin, a local Request occurs. What do you
do if:
Case E1: Gin has not yet occurred ?
Case E2: Gin has already been passed to Gout?
2-Wire Daisy Chain
XI - 9
Buses - Arbitration
487
Bus_Request_1
Request_1
Grant_1
and the rest
of the
Interface
Rout
Unit 2 Rin
Distrib.
Arbiter
Gin
Gout
Request_2
Bus_Request_2
Bus_Grant_2
Central
Arbiter
Rout
Unit 1 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Grant_1
Bus_Grant_0
Case B (LOCAL ONLY):

if only the local device interface (i) requests service.
Requesti goes to a 1
Rout goes to a 1. (and
thus
BusRequesti1
also goes to a 1).
Later Gin 1 (I.e.
BusGranti1 goes to
1), the ith arbiter claims
bus and informs the interface with a 1 on
Granti.
Bus_Request_0
Case B: Only Local Request Block Diagram
Grant_2
and the rest

of the
Interface
arbcct1b
2-Wire Daisy Chain
XI - 10
Buses - Arbitration
488
Case B: Only Local Request Ladder and Timing Diagram
Device1
Distributed
Arbiter1
Central
Arbiter
1
2
Device2
Distributed
Arbiter2
assert
Request1
Typical Timing (Assume that the Request

signal remains high as long as the device
wishes to use the bus.)
Local Request/Use (Interface 1)
assert
Bus_Request0
Request_1
Bus Reserved
for use by
Device1
assert
Bus_Grant0
Bus_Request_1
assert
Grant1
Interface1 uses
the bus
deassert
Request1
deassert
Bus_Request0
deassert
Grant1
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
deassert
Bus_Grant0
Grant_1
2-Wire Bus Arbiter (Only Device 1 Active)

Case B
2wire4 1.
arbit2wireCaseB.pdf
2-Wire Daisy Chain
Note: Falling Edge of Request removes Grant1.

XI - 11
Buses - Arbitration
489
Case B - Lines Added
Local Request/Use (Interface 1)
I/F 1 uses bus
Request_1
Bus_Request_1
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
Grant_1
Case B Showing Relationships
2wire4 1a.
2-Wire Daisy Chain
XI - 12
Buses - Arbitration
490
Case C: Non-Local Request Block Diagram

Case C: if only a device
to the right (lower priority?)
wants to use the bus.
Rout tracks Rin
Gout tracks Gin
Bus_Grant_0
2-Wire Daisy Chain
Bus_Request_1
2
5
Request_1
Grant_1
and the rest
of the
Interface
Rout
Unit 2 Rin
Distrib.
Arbiter
Gin
Gout
1
Request_2
Bus_Request_2
Bus_Grant_2
Central
Arbiter
Rout
Unit 1 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Grant_1
Bus_Request_0
arbcct1c
Grant_2
and the rest

of the
Interface
XI - 13
Buses - Arbitration
491
Case C: Non-Local Request Ladder and Timing Diagram
Distributed
2-Wire Bus Arbiter
2
ArbiterDevice
2
(Only Device 2 Active)
1
Device1
Case C
Request2
2
Distributed
assert
Arbiter1
Bus_Request1
assert
Central 3
Bus_Request0
Arbiter
assert
Non-Local Request/Use (Interface 2)

Request_2
Interface 1 detects
bus reserved
Bus Reserved
assert
Bus_Grant0
assert
5
assert
Grant2
Bus_Grant1
6
Interface2 uses
the bus
Bus_Request1
deassert
deassert
Grant2
deassert
Bus_Request0
Deassert could
happen at any time
deassert
Bus_Grant0
Bus_Request_1
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
4
5
Grant_2
deassert
Bus_Grant1
arbit2wireCaseC.pdf
2-Wire Daisy Chain
6
2wire4 2.
Note: this is a pass through mode only.
XI - 14
Buses - Arbitration
492
Case C - Lines Added
Bus Usage
by I/F 2 as
seen at I/F 1
Non-Local Request/Use (Interface 2)
Request_2
Bus_Request_1
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
Grant_2
Case C with relationships
2wire4 2a.
2-Wire Daisy Chain
XI - 15
Buses - Arbitration
493
Bus_Request_1
Request_1
Grant_1
and the rest
of the
Interface
Rout
Unit 2 Rin
Distrib.
Arbiter
Gin
Gout
5
Request_2
Bus_Request_2
Bus_Grant_2
Central
Arbiter
Rout
Unit 1 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Grant_1
Bus_Grant_0
Case D: while the local interface is using the bus a request

from the right occurs
When the local interface
is finished what to do?
Case D1:
forward
Grant to the right when
local device finished,
(Not Advised as the
complexity of the implementation may not be
justified.)
Case D2: Wait for new
arbitration cycle.
Bus_Request_0
Case D1: Remote Request During Use Block Diagram
Grant_2
and the rest

of the
Interface
arbcct1d
2-Wire Daisy Chain
XI - 16
Buses - Arbitration
494
Case D1: Remote Request During Use

No Re-Arbitration Ladder and Timing Diagram
Device1
Distributed
Arbiter1
Central
Arbiter
1
2
Request During Use (Dev. 1 then 2)
2-Wire Bus Arbiter (Request While

Local Device Using Bus)
assert
Case D1
Request1
DO NOT Wait for Next Cycle
assert
Bus_Request0
Distributed
Device2
Arbiter2
3
assert
assert
Bus_Grant0 Grant1
4
Bus Reserved
Request_1
assert
Bus_Grant_1
Interface1 uses
the bus
5
assert
Request2
6
Interface 2 asserts
Bus_Request1
deassert
Grant1
7
assert
Grant2
Interface2 uses
the bus
deassert
Request2
deassert
Bus_Request1
deassert
Grant2
Request_2
Bus_Request_1
Bus_Request_0
Bus_Grant_0
3
7
Bus_Grant_1
Grant_1
Grant_2
2wire4 3.8
arbit2wireCaseD1.pdf
2-Wire Daisy Chain
XI - 17
Buses - Arbitration
495
Case D1 Lines Added
Request During Use (Dev. 1 then 2)

Case D1 with Relationships
Request_1
Request_2
Bus_Request_1
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
Grant_1
Grant_2
I/F 1
I/F 2
2wire4 3a.
2-Wire Daisy Chain
XI - 18
Buses - Arbitration
496
Bus_Request_1
Request_1
Grant_1
and the rest
of the
Interface
Rout
Unit 2 Rin
Distrib.
Arbiter
Gin
Gout
5
Request_2
Bus_Request_2
Bus_Grant_2
Central
Arbiter
Rout
Unit 1 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Grant_1
Bus_Grant_0
Case D: while the local interface is using the bus a request

from the right occurs
When the local interface
is finished what to do?
Case D1:
forward
Grant to the right when
local device finished,
(This is not advised as
the complexity of the
implementation may not
be justified.)
Case D2: wait for new
arbitration cycle.
Bus_Request_0
Case D2: Remote Request During Use Block Diagram
Grant_2
and the rest

of the
Interface
arbcct1d2
2-Wire Daisy Chain
XI - 19
Buses - Arbitration
497
Case D2: Request During Use (Re-arbitrate) Ladder and Timing Diagram
Remote Request during Use (Dev. 1 then 2)

Wait For Re-Arbitration
2-Wire Bus Arbiter (Request While
Device1
Local Device Using Bus)
Case D2 Wait for Next Cycle
Re-Arbitration Distributed
Arbiter1
Bus Reserved
Central
Arbiter
Device2
Distributed
Arbiter2
Request_1
assert
1
Request1
2
assert
Bus_Request0
3
assert
Bus_Grant0
assert
Grant1
4
Request_2
Interface1 uses
the bus
Bus_Request_1
Bus_Request_0
assert
5 Request2
6
assert
deassert Bus_Request1
deassert
Request1
Bus_Request0
deassert
Grant1
deassert
Bus_Grant0
Bus_Grant_0
Bus_Grant_1
Grant_1
Grant_2
Reassert
Bus_Request0
to get bus for
Device 2
(Now a Case C).
arbit2wireCaseD2.pdf
2-Wire Daisy Chain
2wire4 4.
Rising signal on BusRequest0,

at point A caused by falling Gin
(BusGrant0) and a request from
Rin.
XI - 20
Buses - Arbitration
498
Case D2
Remote Request During Use (Dev. 1 then 2)

Wait For Re-Arbitration
Case D2 with Relationships
Request_1
Request_2
Bus_Request_1
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
Grant_1
Grant_2
I/F 1
I/F 2
2wire4 4a.
2-Wire Daisy Chain
XI - 21
Buses - Arbitration
499
Simultaneous Requests with 2-Wire Arbitration. (Cases E1 and E2)
Gin
Request 1
Gout
Bus Request 1
Rout
Rin
Unit 1
Bus Grant 1
Bus
Arbiter
(Central Unit)
Bus Grant 0
Bus Request 0
What happens when Unit 1 requests bus, after Unit 2 has requested the bus?
Unit 2
Grant 1
Rest of
Interface
Data
Address
Control
2wire3.
2-Wire Daisy Chain
XI - 22
Buses - Arbitration
500
Simultaneously Pending Requests with 2-Wire Arbitration

Case E1, Request1 occurs early enough that device 1 gets the bus as if it were the first
to request the bus
Case E2, Request2 precedes Request1 by sufficient time that Device 2 gets the bus first.
This situation means that Granti cannot be a simple combinational function of Requesti,
BusRequesti, and BusGranti1.
But for Case E2 there had to be a number of assumptions
Case E2-A: Once BusRequest1 was removed, Grant1 was issued without further
arbitration by the Central Arbiter (CA). Unit 1 would be designed to assume that
Unit 2 would release the bus quickly enough for Unit 1 to use the bus. What does
this do to the meaning of priority? (A poor alternative.)
Case E2-B: Once BusRequest1 was removed by Unit 2s distributed arbiter a rearbitration cycle would be initiated.
Note: non-preemptive service, the arrival of Request1 does not terminate Unit 2s
use of the bus.
2-Wire Daisy Chain
XI - 23
Buses - Arbitration
501
Case E1: Remote Request First, Local Shortly After
Bus_Request_1
Rout
Unit 2 Rin
Distrib.
Arbiter
Gin
Gout
Request_1
deassert
Grant_1
Request_2
Grant1
Grant_2
and the rest

and the rest
of the
of the
deassert
Interface
Interface
Bus_Grant0
Device1
Distributed
Arbiter2
1
Central
Arbiter
Now same
as Case D
Device2
assert
Request2
2
assert
Bus_Request1
assert
3
Bus_Request0
Bus Reserved
Rout
Unit 1 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Request_2
Bus_Grant_2
Bus_Grant_0
Central
Arbiter
2-Wire Bus Arbiter (remote request

and while waiting for grant
local request occurs) Distributed
Case E1
Arbiter1
deassert
Bus_Request0
Bus_Grant_1
Bus_Request_0
Case E1
5
assert
Bus_Grant0
assert
4 Request1
Interface1 uses
the bus
6
assert
Grant1
deassert
Request1
arbit2wireCaseE1.
Reassert
arbcct1e
Bus_Request0
to get bus for
Device 2
(Now a Case C).
2-Wire Daisy Chain
XI - 24
Buses - Arbitration
502
Case E1A: Local Request Before Grant Timing Diagram

Non-Local Request/Use Then Local Request
(Dev. 2 then 1)
Case E1 A (Local Request Before Grant)
(Propagate Grant)

(Dev. 2 then 1)
Case E1 A (Local Request Before Grant)
(Propagate Grant)
Request_2
Request_2
Request_1
Request_1
Bus_Request_1
Bus_Request_1
Bus_Request_0
Bus_Request_0
Bus_Grant_0
Bus_Grant_0
Bus_Grant_1
Bus_Grant_1
Grant_1
Grant_1
Grant_2
Grant_2
I/F 1
I/F 2
2wire5 1.
2-Wire Daisy Chain
I/F 1
I/F 2
2wire5 1p.
XI - 25
Buses - Arbitration
503
Case E1B: Local Request Before Grant Re-Arbitrate

(Dev. 2 then 1)
Case E1 B (Local Request Before Grant)
(Rearbitrate Grant)
Request_2
Request_1
Bus_Request_1
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
Grant_1
Grant_2
I/F 1
I/F 2
2wire5 1a.
2-Wire Daisy Chain
XI - 26
Buses - Arbitration
504
Case E2: Remote Request First, Local Request After
arbcct1e2
arbit2wireCaseE2a.
Bus_Request_1
Request_1
Grant_1
and the rest
of the
Interface
Request_2
Grant_2
and the rest

of the
Interface
2-Wire Daisy Chain
2-Wire Bus Arbiter (remote request

and while waiting for grant
local request occurs)
Distributed
Case E2
Device1
Distributed
Arbiter2
Arbiter1
Decision Point
lower device
finished
re-arbitrate?
Central
Arbiter
Bus Reserved
Rout
Unit 2 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Request_2
Bus_Grant_2
Bus_Grant_0
Central
Arbiter
Rout
Unit 1 Rin
Distrib.
Arbiter
Gin
Gout
Bus_Grant_1
Bus_Request_0
Case E2
Device2
assert
Request2
assert
Bus_Request1
3
assert
Bus_Request0
assert
4
assert
Bus_Grant1
Bus_Grant0 5
6
assert
Request1
deassert
Bus_Request1
assert
Grant2
Interface2
uses
the bus
deassert
Request2
E2A: Issue Bus_Grant1 immediately

E2B: Deassert Bus_request0 await
deassertion of Bus_Grant0, then
re-assert Bus_Request 0.
XI - 27
Buses - Arbitration
505
Cases E2A and E2B: Local Request After Grant
No Re-arbitration

(Dev. 2 then 1)
Case E2 A (Local Request After Pass Grant)
No Re-arbitration (Note Priority)
Request_2
With Re-arbitration

(Dev. 2 then 1)
Case E2 B (Local Request After Remote Grant)
with Re-arbitration
Request_2
Request_1
Request_1
6
Bus_Request_1
Bus_Request_1
Bus_Request_0
Bus_Grant_0
Bus_Request_0
Bus_Grant_0
Bus_Grant_1
Grant_1
Grant_2
Bus_Grant_1
7
Grant_1
2wire5 2.
Also a problem with priorities, not a

recommended model.
2-Wire Daisy Chain
Grant_2
2wire5 3.
XI - 28
Buses - Arbitration
506
Some Alternatives
Re-Arbitrate for every use of the bus. (Option B would require the local unit to ignore all
bus grants except if there were a rising edge on the BusGranti1 signal ... as shown in
E2B and E1B above)
As above (E2A), permit the local arbiter unit to claim bus if all devices to the right (lower
priority?) have no bus request pending. Question: What happens if the local device
changes its mind? It releases BusRequesti1, but before BusGranti1 is removed it
reasserts BusRequesti1 there could be 2 bus masters.
2-Wire Daisy Chain
XI - 29
Buses - Arbitration
507
Fundamental Mode Circuit Design

Mano provides a detailed design strategy for fundamental mode digital circuits. The design is
based on the following assumptions.
Fundamental Mode Assumptions:
(1) inputs only change one at a time. That is, the probability of two signals changing simultaneously is 0 and
(2) the output (state) signals stabilize before the next input change is received.
2-Wire Daisy Chain
Combinational
Circuitry
Input
Signals
fundamental1
Output Signals
XI - 30
Buses - Arbitration
508
Design of a 2-Wire Arbiter Fundamental Mode Design

Inputs specified as Rin, Gin, Request
Outputs specified as Rout, Gout, Grant
indicates an error condition. In this derivation, the design has not included the circuitry
required to act on erroneous conditions. However, some of the erroneous conditions are
notes.
S indicates the column with the state ID.
First, consider the basic single request (no other action.)
Note: A primitive flow table has only 1 stable state per row.To save space, some states have been
merged in the primitive flow table examples that follow.
2-Wire Daisy Chain
XI - 31
Buses - Arbitration
509
Design of a 2-Wire Arbiter (Almost) Primitive Flow Table
S Mnemonic Input Conditions (Rin,

000
001
011
a Idle
a000 b-00 b Lreq
b100 e10c Rreq
d LRreq
b100 e Lgnt
e101
f Rgnt
g LRreqG
h other
a000 b-00 h000
i LgntRreq
e101
j RgntLreq
h100
Gin, Request)
010
110
f1-0
h-0h- -0 f110
h100
h000 h000
h100
f110
111
g10i101
j110
g101
h000
i101
j110
101
d100
d100
d100
d-00
100
c-00
c100
c100
c-00
-
Note: the entries in the table represent the next state followed by the output values (Rout, Gout,
Grant)
2-Wire Daisy Chain
XI - 32
Buses - Arbitration
510
Note: Primitive State Summary
State a is the idle state
The system is in state b during a local request (Request) when there is no remote request (Rin ). (I.e., no other request
pending or active.)
The system is in state c during a remote (only) request. (I.e., no local request is pending.)
The system is in state d while awaiting a Gin signal. It remains here until the Gin signal is received. Note: if the request
(local (Request) or remote (Rin )) disappears, although unusual, an error could be avoided.
The system is in state e once a Gin has been received to service a local request
State e Grant for local use received. Note, in the event of a second request (Rin ) the next state is the i state.
The system is in state f once a grant for remote use received. Note if a local request (Request) is received while in state f
the next system state is the j state.
The system is in state g when there are two requests pending, The local request wins when grant is detected. In this state
when going from state g to state h, the output has been specified as h100 to force Grant to be turned off first. We should
change only 1 output at a time.
2-Wire Daisy Chain
XI - 32.1
Buses - Arbitration
511
Note: Primitive State Summary (continued)
The system is in state h for all cases when the arbiter must wait for grant to fall after Rout has been lowered. The use of
state h, rather than separate lines for all the possible ways to get here is one of the places the primitive flow table has been
simplified.
The system is in state i when the local device interface is the bus master, and there is a request received from some arbiter
further down the daisy chain (Rin ). If the remote request (Ri n) disappears before a grant for it is received (a second Gin )
then return to state e. In this state when going from state i to state h, the output has been specified as h100 to force Grant
to be turned off first.
The system is in state j when a local Request arrives while a remote interface is using the bus. In this state, it is assumed
that on the transition from state j to state h that h100 is reasonable as it turns the Grant off before Gin has been received.
(This is subtly different from the version shown in the timing diagrams.)
2-Wire Daisy Chain
XI - 32.2
Buses - Arbitration
512
Primitive States and Arbiter Cases

Several arbitration situations are listed (starting on page 485) . The table below relates some
of these situations to a sequence of states in the previous primitive flow table.
Case Sequence of Steps in Primitive Flow Table
A
idle state a only
B
local only request: States: a, b, e, h (when done) then back to a. Note:
it will remain in state b until the local arbiter wins the bus.
C
remote only request States: a, c, f, h, a. Note: it will remain in state c
until the local arbiter wins the bus.
D2
remote request after local starts to use the bus. a, b, wait arb, e, (then
remote requests), i, h, wait for Gin to drop, c, wait arb, f, h, a
E1
remote request first, then local request (before Gin): a, c, d, bus arb,
g (local use, remote pending), h (re-arbitration so turn off Rout), wait
arb (to turn off Gin), c, f (remote use), h, a
2-Wire Daisy Chain
XI - 33
Buses - Arbitration
513
Note: State Reduction (Merging)

Assume that the following table is a complete flow table (There are a number of cases not handled in this table.)
Mnemonic
Input Conditions (Rin , Gin , Request)

000
001
011
010
110
111
101
100
Idle
a000
b-00
c-00
Lreq
b100
e10-
d100
Rreq
f1-0
d100
c100
LRreq
b100
g10-
d100
c100
Lgnt
e101
h-0-
i101
Rgnt
h- -0
f110
j110
LRreqG
h100
g101
other
a000
b-00
h000
h000
h000
h000
d-00
c-00
LgntRreq
e101
h100
i101
RgntLreq
h100
f110
j110
Note: Table entries: Next State Rout , Gout , Grant
2-Wire Daisy Chain
XI - 33.1
Buses - Arbitration
514

Implication Table.
One Pass Implication Table
merger.
merger1.
b
c
Completed assuming that

E states can be merged without
problem. This should be checked
for a complete design.
d
e
f
g
h
i
j
a b
d e
f g
2-Wire Daisy Chain
XI - 33.2
Buses - Arbitration
515

Completed Implication Table
Initial Merger Diagram
merger2.
merger3a.
h
Continuing from previous foil
d
f
2-Wire Daisy Chain
XI - 33.3
Buses - Arbitration
516
Merge a,b,c, and f to A

and d,e,g and i to B,
rename h to C and
rename j to D
g
d
f
e
merger4a.
2-Wire Daisy Chain
XI - 33.4
Buses - Arbitration
517

One alternative from the merger graph:
States a, b, c, and f can be merged (A)
States d, e, g, and i can be merged (B)
State h is now C and
State j is now D
This results in the following reduced state table, ignoring the merging of error states () and foolishly assuming that they wont
happen.
Input Conditions (Rin , Gin , Request)

000
001
011
010
110
111
101
100
A000
A100
B1- -
C- -0
A110
D110
B100
A100
A100
B101
C-0-
C100
B101
B100
A100
A000
A000
C000
C000
C000
C000
B100
A100
C100
- - -0
A110
D110
B100
Note: Table entries specified as: Next State Rout Gout Grant
2-Wire Daisy Chain
XI - 33.5
Buses - Arbitration
518
Note: Final Points
Then one must allocate state vars etc. and finish the design. Note that only 4 states seem to be needed
You must also determine if the values in the blank boxes can remain as dont cares, or if there is some race condition that
requires a value to be specified.
May wish to specify dont cares to obtain predictable results.
2-Wire Daisy Chain
XI - 33.6
Buses - Arbitration
519
3-Wire Daisy Chain Arbitration
Use two passive pull-up

(open-collector) bus lines
BusBusy
and
BusRequest
and one daisy chained wire
BusGranti.
Three Wire Structure

BusBusy
BusRequest
Central
Bus
Arbiter
(CA)
BusGrant0
Distributed
Bus
Arbiter
1
Distributed
Bus
Arbiter
2
Distributed
Bus
Arbiter
3
Request1
Grant1
Rest of
Interface
3wire1.
3-Wire Daisy Chain
XI - 34
Buses - Arbitration
520
3-Wire Daisy Chain Arbitration Functionality and Operation

When should the Central Arbiter (CA) grant the bus?
What cases must be handled?
The Distributed Arbiter(DA) associated with the Interface using the bus pulls BusBusy
low.
The DA associated with the interface wanting to use the bus pulls BusRequest low,
The CA issues BusGrant0 as follows:
BusGrant0 = BusBusy BusRequest
i.e., when the bus is idle (BusBusy is floating high) and there is a request pending
note the CA requires only an inverter and an AND gate.
3-Wire Daisy Chain
XI - 35
Buses - Arbitration
521
3-Wire Daisy Chain Arbitration Operation (Cont.)

Any DA unit that does not have a Request pending, passes the grant onto the next DA
in the chain
A DA (say DAi) claims (takes over, starts to use) the bus when:
Requesti = 1 (I.e. a request is pending) and
BusBusy = 1 (I.e. no-one else is using the bus) and
a 0 to 1 transition occurs on BusGranti1.
The CA removes BusGrant0 when BusBusy goes low.
Once a DA has control of the bus it releases its BusRequest.
3-Wire Daisy Chain
XI - 36
Buses - Arbitration
522

3wire2 1.
Distributed
Arbiter
(DA)
BusGrant1
Central
Arbiter
(CA)
BusGrant0
BusBusy
BusRequest
Distributed
Arbiter
Decreasing
Priority
DA2 only receives a grant

if DA1 has no local request.
Request2
Request1
Grant2
Grant1
3-Wire Daisy Chain
XI - 37
Buses - Arbitration
523
3-Wire Daisy Chain Arbitration Ladder Diagram
Central
Assume Bus Arbiter
Idle to start
Device
Interface1
Distributed
Arbiter1
assert
Request1
assert
/BusRequest Bus
Arbitration
at CA
Bus Reserved
Note /BusBusy
and
/BusRequest
change at
similar times
Device
Interface2
3-Wire Bus Arbiter

(Only Device 1 Active)
Distributed
Arbiter2
arbit3wireCaseB.
Arbitration
assert
BusGrant0
assert
Assert
Grant1
/BusBusy
Deassert
/BusRequest
Deassert
BusGrant0
Deassert
/BusBusy
Device1 uses
the bus
Deassert
Request1
deassert
Grant1
3-Wire Daisy Chain
XI - 38
Buses - Arbitration
524

3wire2 2.
Not to scale (none of the figures are to scale)

Request1
Request2
BusRequest
BusBusy
BusGrant0
BusGrant1
Grant1
Grant2
At DA1
At DA2
At the CA
Arbitration(1)
Bus Use(1)
Arbitration(2)
Arbitration(1)
3-Wire Daisy Chain
Bus Reserved(1)
Bus Use(2)
Arbitration(2) Bus Reserved(2)
XI - 39
Buses - Arbitration
525
Note: 3-Wire Daisy Chain Arbitration, Bus Idle Timing Diagram
Three device interfaces

Bus idle
Non-local request
3wire3 1.
Arbitration
Bus Use
Request1
Request2
Request3
BusRequest
BusBusy
BusGrant0
BusGrant1
BusGrant2
Grant1
Grant2
Grant3
3 Wire Bus Arbitration

Bus Idle
3-Wire Daisy Chain
XI - 39.1
Buses - Arbitration
526
Note: 3-Wire Daisy Chain Arbitration, Bus Busy Timing Diagram
Three devices
Initially used by interface for
device 2
Requests by interface for device 3 then interface for device 1
Use by interface for device 1
then interface for device 2
3wire3 2.
Request1
Request2
Request3
BusRequest
BusBusy
BusGrant0
BusGrant1
BusGrant2
Grant1
Grant2
Grant3
3 Wire Arbitration
Bus Busy,
Note Priority
3-Wire Daisy Chain
XI - 39.2
Buses - Arbitration
527
4-Wire Distributed Bus Arbitration

One way to overlap arbitration and bus usage is to introduce a third passive pull-up (opencollector) bus signal (BusAck).
BusAck is set when the next DA to use the bus has successfully received a BusGrant.
BusBusy
BusRequest
BusGrant1
BusGrant0
BusAck
Request1
Request2
Grant1
Grant2
4wire1 1.
4-Wire Daisy Chain
XI - 40
Buses - Arbitration
528
4-Wire Distributed Bus Arbitration

4wire1 2.
Request1
Request2
Either Order
BusRequest
BusAck
BusGrant0
BusGrant1
BusBusy
Grant1
Grant2
DA1
Arbitration
(1)
DA2
4-Wire Daisy Chain
Bus
Use (1)
Arbitration
(2)
Bus
Use (2)
XI - 41
Buses - Arbitration
529
Arbitration System as a Whole

distributed
Distributed vs System View
Central
Arbiter
3-wire bus arbitration system shown as a distributed system

each DA only has information provided by signals attached directly
to the DA. There is no central point that has all of the information
Distributed
Arbiter
(DA)
Distributed
Arbiter
(DA)
Distributed
Arbiter
(DA)
Distributed
Arbiter
(DA)
Central
Arbiter
Arbitration System (4 request and 4 acknowledge signals)
Distributed
Arbiter
(DA)
Distributed
Arbiter
(DA)
Distributed
Arbiter
(DA)
Distributed
Arbiter
(DA)
When viewed as a monolithic arbiter, all that can be observed it

the 4 requests and 4 acknowledge signals. The circuit can
be caracterized by the response to these signals
Summary of the Operational Characteristics of Daisy-Chained Bus Arbitration
XI - 42
Buses - Arbitration
530
Summary of Daisy Chain Characteristics Bus Idle Delay

Consider a request by the nth distributed arbiter in a daisy chain.
Assume that the bus is idle, so the delay between Request and Grant is related only to
the time to decide on the next user.
Delay (tarbitration,
bus idle )
if the bus is idle:
2-wire: (t2wire
arbitration,
bus idle )
delay through 2 n distributed arbiters.
3-wire: (t3wire
arbitration,
bus idle )
delay to drive a bus line (BusRequest), delay through
n links in the daisy chain plus the time through the CA, plus the time to assert
BusBusy. The time to drive Grant is part of the n delays in the distributed arbiter
chain. 4wire
4-wire: (tarbitration, bus idle) delay to drive BusRequest, delay through n links in the
daisy chain, the delay through the CA, delay to drive BusAck, and finally the delay
to assert BusBusy
for the 3-wire and 4-wire the BusGrants are deasserted during bus usage and the time
associated with that activity is ignored here.
XI - 43
Buses - Arbitration
531
Note: A few comments on counting delays

In some sense the goal of this exercise is to be equally fair (or unfair) to all the alternatives just to permit comparisons. However, as
each reader may interpret the counting differently this note is provided to indicate how this particular count has been accomplished.
Delay through the distributed arbiter (tDA ) Any delay from the arrival of a change at an input to a change at one (or more)
output(s). Although the actual design of the fundamental mode circuit would provide more precise numbers, here they have all been
treated as the same. Thus, for example, in a 3-wire arbiter, the device at position n receives its Grant after delays though arbiters:
1, 2, ... n 1, and n, or n tDA after the CA creates the first grant.
Bus line delays (tBL ). As each bus line may have added driver requirements, this derivation assumes that if a bus line is to be
driven it requires tBL time in addition to any other time (most notably tDA ).
Central Arbiter (tCA ). In these models the central arbiter has been modelled as a constant. In the case of the 2-wire, since the
central arbiter is a wire, it has been modelled as tCA = 0.
XI - 43.1
532
Buses - Arbitration
Summary of Daisy Chain Characteristics Bus Idle Priority

Nominal priority if the bus is idle and two or more simultaneous requests are received:
2-wire: fixed priority starting from central arbiter
XI - 44
Buses - Arbitration
533
Bus Idle tuncertainty

idle1.
Distributed Arbiter
for one interface (q)
Priority uncertainty: consider the

situation when the bus is idle and
there are 2 or more requests. If device i requests the bus more than
tuncertainty before the interface at
device n would receive the bus
(i n) then priority is as expected
and device i received the bus.
2-wire: t2wire
uncertainty = (n i) tdistributed
arbiter delay
3-wire: t3wire
arbiter delay
4-wire: t4wire
arbiter delay
requests
from n and i.
n-i
i
XI - 45
Buses - Arbitration
534
Note: Daisy Chain Characteristics Bus Idle

idle1a.
Distributed Arbiter
for one interface (q)
Consider the ladder digram for a 2-wire daisy chained bus arbiter
shown.
Assume that the bus is idle, and has been idle for sufficient
time to stabilize. (I.e., there are no signal changes propagating through any of the distributed arbiters.)
Assume that the nth interface makes a bus request at time
trequest n .
Interface i can make a request at any time.
if the request is prior to the time marked as CT in
the figure then interface i will get the bus.
if the request arrives after CT, then interface n will
become the bus master.
it is important to note that when the request
from device i arrives the bus is idle,
it is also of note that i is the highest priority
interface requesting the use of the bus.
despite this, n gets the bus.
this is the uncertainty time, i.e., the time during
which the natural daisy chain priority may be
violated.
Simultaneous requests
from n and i.
n-i
i
CA
tRequest n
tRequest i1
Critical Time CT
tRequest i2
Interace i gets the bus
(n-i)*tdistributed arbiter delay
XI - 45.1
Buses - Arbitration
535
Summary of Daisy Chain Characteristics Bus Busy

Consider a request by the nth distributed arbiter in a daisy chain.
Assume that the current user is the cth distributed arbiter. (Note c may be larger or smaller
than n.)
Assume that the bus is busy, so the delay (following the completion of the current operation) is related to the time to decide on the next user.
What is the delay between the completion of one user and the start of the next user,
assuming that the request by the next user was already present at the DA when the
current user finished as bus master? (tarbitration, bus busy )
XI - 46
Buses - Arbitration
536
Summary of Daisy Chain Characteristics Bus Busy 2-Wire
Distributed Arbiter
for interface (c)
currently using bus
busy1.
Central
Arbiter
n>c
Remove Request
2-Wire
Re-Arbit.
(n>c)
Re-assert Request
Detect Rising Grant
Central
Arbiter
n<c
c
2-Wire
Re-Arbit.
(n<c)
3c+n
Detect falling Grant
n
n
n
c
Remove Request
c+3n
Detect falling Grant

Re-assert Request
Detect Rising Grant
XI - 47
Buses - Arbitration
537
Summary of Daisy Chain Characteristics Bus Busy continued

Delay (tarbitration,
bus busy )
3-wire: (t3wire
arbitration,
if the bus is busy (continued):
bus busy )
delay to deassert BusBusy, delay through CA, delay
through n links in the daisy chain including the delay to assert Granti and then to
assert BusBusy. (delay to deassert the BusRequest and BusGrant signals is
within the bus usage time and can be ignored here.)
4-wire: Assume request is greater than t4wire
arbitration,
bus idle
before the bus becomes
idle so that arbitration selection process is complete before the previous user has
finished using the bus. Thus t4wire
arbitration,
bus busy
is just the time to assert Grant and
BusBusy
XI - 48
Buses - Arbitration
538
Summary of Daisy Chain Characteristics Bus Busy Priority Uncertainty

Nominal priority if the bus is busy when the request arrives:
2-wire: fixed priority starting from CA
3-wire: fixed priority starting from CA
4-wire: DA, closest to the CA, that is making a request when the current bus user
starts to use the bus, has the highest priority.
Priority uncertainty if the bus is idle and there are 2 or more requests. If device i requests
the bus more than tuncertainty before the interface at device n would receive the bus (i n)
then device i gets the bus.
2-wire: t2wire
arbiter delay
3-wire: t3wire
arbiter delay
4-wire: t4wire
arbiter delay
+ tcurrent
usage
user
XI - 49
Buses - Arbitration
539
Note: Tabular Summary of Daisy Chained Comparison
Bus Status
Parameter
2-wire
3-wire
4-wire
Bus Idle
Bus Busy
tarbitration, bus idle

tuncertainty
tarbitration, bus busy
tuncertainty
2ntDA
(n i)tDA (3c + n)tDA or (c + 3n)tDA (n i)tDA
ntDA + 2tBL + tCA (n i)tDA
ntDA + 2tBL + tCA
(n i)tDA
ntDA + 3tBL + tCA (n i)tDA
tBL assuming
(n i)tDA+
user
selection complete
tcurrent
usage
tDA The time for a signal to propagate through one DA. This is assumed to be the
time from any input to any output.
tCA The time for Grant0 to be produced following the arrival of the last signal to
permit a grant to be issued.
tBL The time for a bus line to be driven and arrive at its destination.
n the ID of the (first) new request.
i in the case of non-simultaneous requests, i is the ID of the second DA to request
the bus. It requests the bus after n requests the bus but before the bus is granted
to n. Assume: n > i.
XI - 50
Buses - Arbitration
540
Question: How to use Arbitration in Synchronous, Asynchronous and

Semi-Synchronous Data Transfer Buses
Data Transfer
2-wire
chain
Arbitration Structure
Daisy- 3-wire Daisy- 4-wire Daisy- Decentralized
chain
chain
Synchronous
FullyInterlocked
Asynchronous
PartiallyInterlocked
Asynchronous
SemiSynchronous
Split-cycle
XI - 51
Buses - Arbitration
541
Non-Daisy-Chained Bus Arbitration

(Similar to the IEEE-696 bus or S-100)
Structure There is a number (4-bits in this case) associated with each devices interface.
The higher the ID the higher
the priority.
An ID of 0000 is reserved for
an idle bus.
nondai2.
DMA3
DMA2
DMA1
DMA0
ID3
ID3
ID2
ID2
ID1
ID1
ID0
ID0
Interface 1
Interface 2
XI - 52
Buses - Arbitration
542
Non-Daisy-Chained Bus Arbitration Operation
nondai1.
DMA3
DMA2
DMA1
DMA0
RequestBus
ID3
open collector driver
ID2
HighPriority
when a device interface wishes to become the bus master, it asserts its ID
on lines ID0 .. ID3. If the device does
not wish to use the bus it applies and
ID value of 0000.
The device with the highest ID that is
seeking to be the bus master becomes
the bus master during the next arbitration cycle.
ID1
ID0
This circuitry is repeated in every device interface.

(the HighPriority signal indicates that the local device interface is now bus master.
The start of a bus arbitration cycle is signaled by lines not shown in the figure.
The names of the signals (DMA0, DMA1, DMA2, and DMA3) are the same names used
in the standard bus.
No daisy chain, no special bus slots
Faster no O(n) step there is no delay that is linear in the number of device interfaces.
XI - 53
Buses - Arbitration
543
Questions of Interest: Bus Arbitration Questions
Terms discussed in this section include: Bus Arbitration and Non-pre-emptive arbitration
priorities in daisy chained bus arbiters.
what is the key feature of daisy chained arbitration techniques? How is this feature replaced in the non-daisy-chained
structure?
Assume that the delay through a DA is 9 ns and that there is a system with 5 devices that may be bus master. Compare
and contrast the tuncertainty among the various arbiters for various bus conditions.
a two-wire arbitration scheme requires the fewest connections and is the best for all uses.
since 4-wire bus arbiters use more of the available bus time, they are the preferred solution.
the non-daisy-chained bus arbiter is faster than the 3-wire bus arbiter.
XI - 53.1
Buses - Arbitration
544
Note: Terms used in Buses Arbitration

Terms:
Bus Arbitration (page 479)

Non-pre-emptive arbitration (page 481)
Central Arbiter (CA) (page 482)
Distributed Arbiter (DA) (page 482)
Fundamental Mode Assumptions (page 507)
XI - 53.1
Section XII:
Direct Memory Access(DMA)
f2014-1.0
546
Buses - DMA: Section Contents

Block Oriented Program Controlled I/O (starting on page 548) Block oriented program controlled I/O operation and requirements
including sample hardware, C-interface software, assembly language interface software and special purpose instruction software
(and hardware) alternatives.
DMA Example (starting on page 558) Examines the fundamental needs of DMA without considering all of the background and
interacting issues. It presents a complete DMA example which, as will be seen later, is based on one set of alternatives.
Complete DMA Cycle (starting on page 567) Considers the DMA cycle from the perspectives of the controller, the interface, and the
device. Provides significantly more structure to the needs of a block oriented transfer using DMA. It also provides ladder diagrams
to compare the timing for program controlled I/O and DMA.
DMA Controller Architecture (starting on page 572) The next three subsections examine DMA controller related issues that are, to
a large extent, independent design alternatives.
A Intimacy Between DMAC and Interface - Detached vs Integrated (starting on page 574) Compares DMA controllers that are
general in nature, designed for use with different and varied interfaces, with those that are part of the interface for which they are
providing service.
B Addressing Structure Implicit Addresses vs Dual Addresses (starting on page 575) Implicit addressing provides a bus cycle that
transfers data directly between interface and memory. This subsection examines the cost in using interfaces that are not designed
for DMA in a DMA environment.
C Bus Structure (starting on page 584) Considers the impact of one and two bus structures on the connectivity of the DMA
controller.
Specialized Topics (starting on page 587) Multiple channel controllers are examined. The specialized needs for transferring data in
long blocks are examined.
Performance Summary (starting on page 591) Comparison of performance of DMA and non-DMA systems. General discussion of
the meaning of performance with respect to I/O systems.
Section Contents: Buses - DMA
XII - 0.1
547
Buses DMA Resources

Vranesic and Zaky: Section 7.6, 7.7, and 7.8
The 6809 and 68000 sections give good concrete examples of DMA controllers and
the description below is a generalization of that material.
Hamacher, Vranesic and Zaky (ECE 222) Section 4.4 (5th Edition), very short.
Stone: 4.3 and 4.4
Resources
XII - 1
548
Program Controlled I/O for Block Oriented Transfers
progcntl.
CPU
Reg
IReg
Interface
MLoc
Memory
To transfer data from a device to memory

1. CPU determines data is available
through interrupts or polling
2. CPU transfers data from interface to a
CPU register
Reg IReg
3. CPU transfers data from the CPU register to memory
M Loc Reg
Device
Block Oriented Program Controlled I/O
XII - 2
549
Block Transfers to/from Devices

Many systems require the transfer of large blocks of data.
mass storage units (eg. floppy drive, hard drive, CD drive)
sensors (eg. camera, scanning range sensor, tactile array)
actuators (eg. displays, printers)
distributed systems (eg. network interfaces)
Block oriented device interfaces
tend to be more complex than character oriented devices
may have built-in buffers to permit synchronization less frequently than every byte
XII - 3
550
Block Transfer - Assumed Interface
progControl2a
High
Address
Bits
Decoder
Bus Clock
R/W
Address Bus
Chip
Select
2 Address
Bits
Data Bus
IRQ
Data Reg
00
01
10
11
2-Bit
Register
Select
ATD
Address Manipulation
Reset
Data Pending
When Data
Read
Data From the Device (Dev Data)

(Transient)
Control Reg.
Int.
Enable Status Reg.
Data Pending
O/C
Device is assumed to be
unidirectional and only
provide data.
Data is applied by the external device, and then
clocked by that device.
When data is clocked the
flip-flop is set to 1, and
this 1 can be read by the
bus master when the status register is queried.
When the data is read,
the
status
register
(ready-bit) is cleared.
D
Ck
D=1
Asynch
reset
Data Available
(rising edge)
XII - 4
551
Block Transfer - Assumed Timing

progControl2 time
Dev Data
Data Available
Data Pending
Address Bus
Status
Data
Register Address Register Address
Bus Clock (Ck)
Unrelated bus activity
XII - 5
552
Terminology Recall
Recall from Section IV of the notes:
CPU Activity
Device and
Interface
(Polling synch
time shown)
tinterdata
Data Available
Interrupt
(n = 2)
Polling
(n = 2)
tsynch-poll
Other CPU Activity
Time
tsynch-intr
ttransfer producer
ttransfer consumer
Note: if
IRQ used,
a diffferent
device
timing is
needed
repeat if
Read Operation,
multiple transfers
Consumer
required
Sensitive
I/O Device
Two Transfers per
Synchronization
progcontrol3.
XII - 6
553
Block Transfer - Example

A block of data (256 bytes assumed here) can be transferred in several ways.
Using a C-like language
i = 0;
/* single byte transfer */
while ((Status_Register & 0x80) != 0x80) {}
value [i] = Data_Register;
/* this can be converted to a loop */
/*
to read 256 items.
*/
for (i = 255; i >= 0; i--)
{
/* test for the presence of data */
teststatus: while
((Status_Register & 0x80) != 0x80)
{}
value [i] = Data_Register;
}
Note:
Number of items transferred is 256.
The
number of tests at
location
teststatus
is unknown, but the
time required is known
(tsynchpoll ). It can be
calculated if you know
the delay between data
(tinterdata).
XII - 7
554
Block Transfer - Example

Using assembly language
; assembly language for a 68000-like
; assume that A0 points to the next place to store a value
; and D0 is the counter (number of values left to read)
; values shown as [2] indicate the number of memory cycles
;
needed for the instruction.
;first initialize (set up the counter) Note
MOVE #256, D0 ;
[2]
Number of useless (not part of
the actual data transfer) memory
; synchronize with the data
(bus) cycles, assuming no cache,
Loop: AND #$80, Status_Register [4]
2 + 256 (6x + 7) where x is the
BEQ Loop
[2]
number of cycles needed for syn;<<Transfer The Data>>
chronization.
MOVE Data_Register, (A0)+
[4]
The faster the device and its interface the smaller x
; now the counting
DEC D0
[1]
BNE Loop
[2]
XII - 8
555
Block Transfer Example - Special Instruction

Could the overhead be reduced by reducing the number of instructions that must be read?
Assume a (very) special machine instruction as part of the CPU
For example:
CopyBlock R2, R3, R4, R1
; copy R1 bytes of data from
; a device with
;
a status register at [R2]
;
a data register at [R3] to
;
a memory block starting at [R4]
XII - 9
556

Consider the single bus CPU shown below.
../222rev/222rev.pdf
IR
Read Write
Rn
Control
...
R1
Processor
Control
Unit
MFC
PC MAR MDR
To Memory
M UX
Internal CPU BUS
Const 4
ALU
Select
XII - 10
557
Assume that the instruction has been fetched.

Assume: the following registers
How many control steps are needed?
are present in the processor
R1 Counter
Step Operations
Comments
R2 Address of the sta1
R2out, MARIn, READ
tus register
2
C1out, Yin, WMFC
R3 Address of the data
3
MDRout, AND, Set Flags
=0 GOTO 1
register
R4 Base data address
4
R3out, MARIn, READ
C1 Constant-register
5
R4out, Add, Zin, Clr Y,
($80)
Set Carry, WMFC, MARIn
wait Data
6
Zout, R4in, WRITE
7
R1out, Clr Y, set Carry, Sub1, Zin
8
Zout, R1in, WMFC
!=0 GOTO 1
Alternative: Use a second CPU-like device. (A DMA Controller)
XII - 11
558
Motivating Example
Many details and choices to come, but first one specific example with specific design decisions
including the items listed below.
Integrated DMA controller (DMAC) and device interface
One DMA enabled interface
Terminology
Basic DMA cycle
DMA control software
Complete DMA cycle
DMA performance comparison
DMA controller issues
DMA Example
XII - 12
559
A Basic, Integrated DMA Controller
Status/Control Register
CPU
Memory
Mode
R/W
Up / Down
Start
Interrupt Enable
Busy
MAR
Byte Count
Register (BCR)
Status/Control
Integrated
DMA Controler
and
Device
Interface
Device
Interface
Interrupt Request
Read-Only Status Bits
Read/Write Control Bits
Device
dmacntl3.
DMA Example
dmareg.
XII - 13
560
Logical Interface
Memory Address Register(MAR): pointer to the next byte in memory to be transferred.
Byte Count Register(BCR): Number of bytes yet to be transferred in the block.
Status/Control Register:
Mode number of transfers per bus mastership
R/W direction
Up/Down how to change the MAR (I.e., increment or decrement.)
Start start the transfer
Interrupt Enable enable/disable interrupt
Busy synchronization bit for processing one block of data
Interrupt Request interrupt pending asserted at the conclusion of processing one block
of data
DMA Example
XII - 14
561
Logical Interface - Transfer Mode

Transfer Mode:
Cycle Stealing : Transfer only 1 byte (word) per bus mastership
May have excessive bus request/bus grant cycles
Transparent: If the processor makes idle cycles known, then it is possible to structure the
system so that DMA controllers only claim the bus when the processor does not need it.
What if long delays between idle times?
There is true parallelism processor is never waiting to get the bus
Requires special signals from the processor. These may be handshaking signals, or
status values.
Burst: Multiple transfers are permitted per bus mastership. This would permit the transfer
of (up to) the entire block in one bus mastership.
Eliminates latency caused by multiple request/acknowledge cycles, but the processor
may be blocked for as long as the bus is required by the I/O device to transfer
some/all of its data.
DMA Example
XII - 15
562
Comments on Burst Length Trade-offs

There is a significant trade-off that must be made when using burst mode. As a result
there are often constraints on the number of transfers that may be permitted in one burst.
(This does not limit the size of the block.)
During a burst transfer the CPU is prevented from accessing anything on the bus.
As a result, if the instruction memory is on this bus, then any requests for interrupts
will be deferred until the end of the burst transfer.
The length of a burst is usually constrained by the following:
the amount of data available to be transferred. If the device has produced 100
bytes of data, then the maximum burst length would be 100 transfers (assume
one-byte transfers), even if the actual block size was 1000 bytes. The completion
of the burst does not (necessarily) signal the end of a block.
the number of bus cycles that the processor is willing to give up the bus. Some
processors are designed in such a way that they cannot stop for more than n
cycles, meaning that they must continue processing within a limited window of
time.
there may be some other limits on the burst length such as limits on the consumer
side or limits on the latency that some other part of the system can tolerate.
DMA Example
XII - 16
563
Basic DMA Data Transfer Sequence

After the global and the device-specific block initialization has been completed, the transfer
sequence is listed below
1. CPU loads DMA controller (DMAC) with starting memory address (in the MAR), the byte
count (in the BCR), and control values
2. When the device has data ready or is ready for more data, it sends a DMARequest
3. DMAC requests the bus and waits until it is granted through arbitration
4. DMAC provides addresses and control to make the transfer occur
5. DMAC increments (or decrements) address (MAR) and decrements byte count (BCR)
6. If burst mode and BCR 6= 0, and more data is available
AND not out of max transfer count length go to 4,
else if BCR 6= 0, release bus and goto 2
7. Transfer is complete; release bus, synchronize CPU and DMAC
DMA Example
XII - 17
564
DMA Request Generation and Interface
simpdma1a.
High
Address
Bits
Decoder
Clock
R/W
Address Bus
Chip
Select
2 Address
Bits
Data Bus
IRQ
Data Reg
00
01
10
Control Reg.
Reset
Data Pending
When Data
Read
Int.
Enable Status Reg.
Data Pending
Q
D
Ck
D=1 Data
Available
DMA Example
O/C
DMA Enable
Asynch
reset
DMARequest
ATD
Data From the Device

(Transient)
11
2-Bit
Register
Select
The block transfer

device (starting on
page 550) can be
modified to permit
DMA transfers.
Note: Only IRQ or
Request DMA would
be enabled at one
time.
XII - 18
565
DMA Transfer from CPU Point of View (C/C++)
Continuing the 256 byte example,

only using the DMA enabled version
of the interface.
A block of 256 bytes can be transferred using DMA
Assume all global initialization has been completed
Assume that device interface
has been set up to produce (or
accept) the block of data
Assume an integrated DMA
controller, and
Assume polling synchronization (for DMAC at the end of
the block)
DMA Example
unsigned char value[MAX_VALUE];

...
/* set up DMA controller */
dma_control =
DMA_UP | DMA_BYTE_MODE | DMA_WRITE;
dma_memory_address = value;
dma_byte_count = 256;
dma_control = dma_control | DMA_START;
/*Note: dma_control is read/write */
/* CPU executes other code */
...
/*CPU polls DMA controller to see if done */

while (( dma_control & DMA_BUSY ) != 0 ) {}
XII - 19
566
DMA Transfer from CPU Point of View Assembler Version

A transfer of 256 bytes in assembly language
...
LOOP:
MOVE A0, dma_memory_address

MOVE #256, dma_byte_count
MOVE #$10, dma_control
[4]
[4]
[4]
AND #$08, dma_control

BEQ LOOP
[4]
[2]
Number of useless memory cycles 12 + 6x

If DMA controller completes first, x = 1
DMA Example
XII - 20
567
Complete DMA Cycle Initialization

System view of DMA steps
Global Initialization (Executed once)
CPU configures the global aspects of the DMA Controller (DMAC)
CPU configures the unchanging aspects of the interface and device (if needed)
CPU configures the unchanging aspects of the DMAC interrupts (if appropriate)
CPU issues read/writes to memory (normal operations)
Block Initialization (Executed once per block)
it may be necessary to setup the device or device interface for each block
CPU writes control values into the DMA controller registers (block size - the byte
count in the BCR, starting address - in the MAR, interrupt enable/disable, etc.)
CPU issues read/writes to memory (normal operations)
Complete DMA Cycle
XII - 21
568
Complete DMA Cycle Data Transfer

Data Transfer (Once per transfer)
Device: some event causes the device to have data or to be ready for data this could
be indicated by setting a status bit
Device Interface: requests a transfer from the DMA Controller
DMAC: requests/receives control of the bus through the bus arbitration system
One or more of the following cycles occurs. The actual number depends on the
transfer mode. (starting on page 561)
DMAC: causes either
memory data to be written to an interface (read) or
an interfaces data to be written to the memory (write)
DMAC: decrements BCR and increments MAR
DMAC: releases the bus
Block Synchronization (Once per block)
the DMAC tests the BCR and if it is now zero sets the DMAC status bit or interrupts
the CPU if DMA interrupts are enabled. Although the test is performed for each
DMA transfer, the action of informing the CPU is performed once per block when
the BCR has a value of 0.
Complete DMA Cycle
XII - 22
569
DMA Transfer Ladder Diagram - Cycle Stealing
Is DMA always worthwhile?
sequence1.
CPU
DMAC
Interface
Global
initialization
Set up DMAC
Set up Interface
(and device)
Set up processor
(interrupts)
Normal CPU
activity
Block
initialization
CPU sends commands

to DMAC and interface
(last one start)
Normal CPU
activity
Normal CPU
Activity, except
some bus cycles
used by DMA
transfer
Device
DMAC requests
bus mastership
DMAC bus master
causes exchange
between interface
and memory
Inform CPU
transfer complete
Block
synchronization
(interrupt/polling)
Complete DMA Cycle
Event occurs that

permits transfer
Device informs
interface
Interface requests
DMA Cycle
Repeat until
all transfers
specified to
DMAC are
complete
Block
synchronization
XII - 23
570
Polling Comparison
CPU
DMAC
Interface
Device
Set up Interface
(and device)
Set up processor
CPU sends
commands
to device
Normal CPU
activity
Event occurs that

permits transfer
Device informs
interface
Polling until
device/interface
ready
Transfer
data
Interface requests
service (set bit)
Repeat until
all transfers
are complete
Block
synchronization
Example Using Polling Synchronization

for the Data Transfers
sequencepoll.
Complete DMA Cycle
XII - 24
571
Interrupt Comparison
CPU
DMAC
Interface
Device
Set up Interface
(and device)
Set up processor
(interrupts)
CPU sends commands
to interface
Normal CPU
activity
Event occurs that

permits transfer
Device informs
interface
Normal CPU
activity
Normal CPU
activity, except
some cycles
used by interrupt
service routine
execution
First
request
Interface requests
interrupt
Repeat until
all transfers
are complete
Block
synchronization
Example Using Interrupt Synchronization

for the Data Transfers
sequenceinter.
Complete DMA Cycle
XII - 25
572
DMA Controller Architecture Considerations

A Intimacy between the interface and the DMAC
Integrated DMA Controller : The DMA control functions (Byte Count Register, MAR,
Control Register and Status register functions) are part of the device interface that
is using the DMA functionality.
Detached DMA Controller : The DMA control functions are implemented as an interface separate from both the processor and the interface(s) that use the DMA
functionality.
B Addressing structure (detached only)
Dual Address Protocol : In this DMA protocol two address cycles are used per transfer,
one to read the data from the source and one to write the data to the destination.
Implicit Address Protocol: In this DMA protocol only one address cycle is used
per transfer. The controller causes the source to place the data on the bus and the
destination to copy the data from the bus at the appropriate time.
C Bus structure
Single bus (memory mapped I/O)
Separate I/O and memory bus (non-memory mapped I/O)
DMA Controller Architecture
XII - 26
573
Note: A DMAC is just an interface with a number of control, status and data
registers!
In the examples that follow, detached vs integrated is presented for single bus structures only.
DMA Controller Architecture
XII - 26
574
A - Intimacy Between DMAC and Interface
Detached
Integrated
Synchronization Signal
CPU
DMA
Controller
CPU
System
Bus
System
Bus
DMA /
Interface
Interface
Memory
Memory
Device
dmacntl2.
Device
dmacntl1.
A Intimacy Between DMAC and Interface - Detached vs Integrated
XII - 27
575
B DMAC - Dual Address - Detached Only

Dual addresses: The DMA controller acts as a surrogate CPU.
1,2 DMAC requests and claims the bus
3,4 DMAC reads the data from the device or the memory depending on direction of
transfer
5 DMAC temporarily stores the data to be written.
6,7 DMAC writes the data to the memory or the device depending on the direction of
transfer
Twice as many bus cycles as implicit version of the transfer, but
No hardware changes to device interfaces.
Note: Each DMA cycle requires 2 bus cycles. A read and a write. The same cycles
as required for the data transfer portion of
the program controlled I/O. Of course there
is still the saving from the reduced synchronization bus traffic.
progcntl.
CPU
Reg
IReg
Interface
MLoc
Memory
Device
B Addressing Structure Implicit Addresses vs Dual Addresses
XII - 28
576
B DMAC - Dual Address
3
6
3
Bus
Arbitration
Arbitration
Address
5
Data
6
Control
Bus
Interface
1
Detached
DMAC
(dual address,
single bus,
single channel)
Buffer
DIAR
MAR
BCR
Control
DIAR is the
Device Interface
Address Register
4. Memory places
value onto bus
7. Device Interface
reads the value
from the bus
The Buffer
holds the value
between cycles
Request
SingleDualA.
XII - 29
577
B Implicit Addresses vs Dual Addresses Detached Only

Implicit and dual address techniques use a separate DMA request line between the interface and
the DMAC for synchronization. These techniques differ in the data transfer addressing.
The address for memory must be provided by the DMAC. How is the I/O interface accessed?
Always an issue in single bus (memory mapped I/O) structures; may be an issue in separate
memory and I/O buses
Implicit addresses:
Devices requests service from interface which in turn seeks service from the DMAC.
DMAC requests and claims bus
DMAC asserts memory address and the control signal(s) for the desired memory
action
DMAC issues a signal (Acknowledge) to the interface indicating that the interface
should take the appropriate action (for example, if it is a memory read, then the data
on the bus should be written to the interface data register for use by the device).
Interface releases request (if appropriate) and the DMAC completes the transaction.
One of the steps during completion is the removal of the acknowledge signal.
XII - 30
578
B Signals Between DMAC and Interface - Detached
Detached DMA Controller

Arbitration
Address
Control
Data
CPU
Memory
DMA
Controller
I/O
Interface 1
Ack
Ack
Implicit address only
Master only
Slave only
Master and slave
operation modes
Req
I/O
Interface 2
Req
Note: Control lines (Clock and

R/W), direction of control changes
with function. There would be
even more dramatic changes with
Slave and Master (asynchronous
bus transfers).
detach.
Which signals are driven/observed by which unit?

XII - 31
579
B Signal flow between the DMAC and Interface - Detached Bus Drivers

CPU As Master
Arbitration
Address
Control
Data
CPU
Memory
DMA
Controller
I/O
Interface 1
Ack
I/O
Interface 2
Req
Req
Ack
detachCPU.
Assume Synchronous Bus
XII - 32
580
Note: B DMAC Bus Usage

detachDMAMaster.

DMA As Master
(General)
CPU
Memory
DMA
Controller
Ack

DMA As Master
(Specific - Memory Read and Write to Interface 2)
Arbitration
Arbitration
Address
Address
Control
Control
Data
Data
I/O
Interface 1
Ack
dashed lines only required
for implicit adressing
detachDMAMasterSpecific.
I/O
Interface 2
CPU
Memory
DMA
Controller
I/O
Interface 1
Ack
Req
Req
Ack signal only required for

implicit addressing
Ack
Req
I/O
Interface 2
Req
Note: Direction of data lines differs if dual vs implicit

address implementation.
XII - 32.1
581
B DMAC - Implicit Address
Arbitration
Address
Data
Control
Bus
Arbitration
Bus
Interface
Detached
1
DMA
controller
(implicit address,
single bus,
single channel)
MAR
BCR
Control
Req
4. Memory places data on bus
5. Interface copies data from bus
Ack
4.5
SingleImplicit.
XII - 33
582
B Interface Connection to the Memory Bus for Implicit Addresses

Note: to transfer from memory to interface:
Memory address (on bus)
Read (on bus)
CS at the interface
Write at the interface
However, you may also want to read/write from the interface when no DMA is active
XII - 34
583
B Interface Connection to the Memory Bus for Implicit Addresses
Data Portion of the Bus

Address Signals on the Memory Bus (Assume 16 bits of address)
Address required to select
2
interface registers
Address Bits
(memory mapped)
Address
Override bus
Address
Manipulation
address
Decoder
2 address lines
(ATD)
(14
Address Bits)
R/Wbus
Device Interface
(connected as before)
Ck
R/WInterface
(Normal) Chip Select
IRQ
00
01
10
Chip Selectinterface
11
I/O Interface
(simpdma
shown previously)
Acknowledge
(Ack. from DMAC)
DEVICE
Request (Req. To
DMAC)
Note: Figure excludes Hold, Master and other bus synchronization signals
implicita.
XII - 35
584
C Single Bus vs Separated Memory and I/O Bus

Previous examples have been presented using a single bus view.
Memory
Memory Bus
Separate
Bus
DMAC
CPU
I/O Bus
I/O -1
I/O -2
Notes:
Where would DMA controller fit?
Although logically separate buses,
most/all of the wires could be shared.
(If the same physical wires are used,
then the DMAC would require local
storage.)
Single bus implies memory mapped
I/O, while separated Memory and
I/O buses implies non-memory mapped
I/O.
separat.
C Bus Structure
XII - 36
585
Considerations for Separated I/O and Memory Buses

Options for separate I/O bus implementation
2 physical buses (two sets of address, data and control lines)
1 physical bus and a mode bit - one set of address, data and control lines and a mode bit.
For example, a mode bit of 1 for memory transfers with 32-bit addresses, 32 bit of data,
and no (automatically inserted) wait states, and a mode bit of 0 for an I/O transfer with
16-bit addresses, 8 bits data and (at least) 2 wait states.
C Bus Structure
XII - 37
586
Separated Bus Example

separatemerged
Single Bus, all address lines invloved in all transfers

Hold line driven by device that requires 1 extra cycle per transfer
Assume a central address decoder
Enable (CS)
(A31, A30)
A31, A30, A7 .. A2
Enable (CS)
(A31 ... A5)
Memory Subsystem
Requires 30 address
bits and 1 chip select.
The memory can
respond at the speed of
the semi-synchronous bus
Complex
I/O device.
Requires 5
address lines
(and a chip select) it
cannot run at bus speed
C Bus Structure
I/O interface
Requires 4
address
lines
(can run at
bus speed)
Enable (CS) (A7 ... A2)
Addr
Decode
A31 ... A00
Hold
Bus Master
Bus Master
Assume a central address decoder
Enable (CS) (A31 ... A2)
Addr
30 bits Decode
A31 ... A00
(Virtually) Separated Bus. Mode Bit = 1 (memory bus 32 address)

mode bit = 0 (I/O bus, 8 address bits active one extra wait state)
Enable (CS)
(A31, A30)
Enable (CS)
(A7 ... A5)
Hold
Memory Subsystem
Requires 30 address
bits and 1 chip select.
The memory can
respond at the speed of
the semi-synchronous bus
Complex
I/O device.
Requires 5
address lines
(and a chip select) it
cannot run at bus speed
I/O interface
Requires 4
address
lines
(can run at
bus speed)
XII - 38
587
Structure of a Multiple Channel Controller
control1.
Multi-Channel, Implicit Address DMAC
Arbitration
Address
Data
Control
Bus
Arbitration
Bus
Interface
Control
Priority among channels set during global

initialization.
Ring
Fixed
Interleaved or
non-interleaved
Status
DMA Controller
Internal Bus
Channel 0
Channel 1
Channel 2
Channel 3
MAR
MAR
MAR
MAR
BCR
BCR
BCR
BCR
Control
Control
Control
Control
Req0 Ack0
Req1 Ack1 Req2 Ack2 Req3 Ack3

To/From Device Interfaces
Specialized Topics
XII - 39
588
Long Transfers and Fast Devices

The DMAC structure described on the previous slide (either single or multiple channels)
works fine for simple one block transfers or if the I/O device has buffering.
Consider the case where there is a very fast device, which requires 1K of data from memory,
but that data is stored in two different 512 byte blocks in memory and there is no buffering
at the device? As a result, during a read the new DMA channel setup must be loaded
very quickly.
I/O Device
Memory
512
1K
512
chain1.
Specialized Topics
XII - 40
589
Continuation Registers
(as in the 6844 described in V&Z, section 7.8.1)
Continuation Registers: are registers, within the DMAC that contain an image of the next
values for MAR, BCR and Control Registers. When the current transfer is complete, these values
are copied in to the active channel. Often the continuation registers are implemented using an
unused channels control registers.
continue2.
Arbitration
Address
Data
Control
Bus
Arbitration
Bus
Interface
Channel 2 set for

Continuation
Register Operation
in the
Control Register
Control
Status
DMA Controller
Internal Bus
Channel 0
2000
512
Control
Channel 1
Channel 2
MAR
Content Copied when
Byte = 0
Byte Count
Control
Channel 3
1000
MAR
512
Byte
Control
Control
Req2
Ack2
Specialized Topics
XII - 41
590
Data Chaining
Data Chaining : In this model, two channels registers are used. One, the data channel, points
to the data that is being read or written. The second channel, the chaining channel, points to a
list of future DMA transfers (setup in memory by the processor). When the byte count register
of the data channel reaches 0, the next values pointed to by the chaining channel registers are
transferred from memory to the data channel registers.
chain2.
Arbitration
Address
Data
Control
Bus
Arbitration
Channel 2 set for

Chain Operation
Control Register
content copied from Memory Control

Bus
(pointed to by Channel 0 when
Status
Interface
Byte
Count = 0)
DMA Controller
Internal Bus
Channel 0
Channel 1
Channel 2
Channel 3
3000
MAR
1000
MAR
15
Byte
512
Byte
Control
Control
Control
Control
Req2 Ack2
Specialized Topics
XII - 42
591
I/O Performance
Optional
DMAC
Interface
Processor
Device
Consider the system described below.
Memory
Processor: 20 MIPS, no cache, 2 memory accesses per instruction,

(25 ns per memory access, 50 ns per instruction)
Data to transfer: 1000 bytes, 10 ms interdata gap, 1 byte per transfer
Block Synchronization: Subroutine to call at the start of block: 40 bus cycles
Subroutine to call at the end of block 40 bus cycles
Data Transfer: IRQ response time 5 bus cycles (time to start ISR)
Subroutine to transfer data and to update counter
for number of transfers 20 bus cycles (used in polling and to transfer data
in an interrupt version)
example1
Performance Summary
XII - 43
592
I/O Performance (tight loop) Polling

In this example the transfer is from the device to the memory (that is a write).
Assume that the interface is spontaneous and as a result that tinterdata starts as soon as the
previous block of data is available.
Polling Times:
Data is read every 10 ms, thus 10 s is required to read all 1000 bytes. This derivation
assumes one byte per transfer. There is an additional 80 bus cycles are required for block
synchronization.
Processor time: 10 s plus block synchronization time 200,000,040 instructions. This can
be represented as 400,000,080 bus cycles (bc)
Bus time: same as processor time.
Performance Summary
XII - 44
593
I/O Performance Interrupt

Interrupt Times:
Each of the 1000 bytes requires one subroutine (20 bc) and one interrupt response times
(5 bc). There is also the block synchronization cost (80 bc).
Processor time: 25,080 bc times.
Bus time: same as processor time.
Performance Summary
XII - 45
594
I/O Performance Dual Address

DMA Times (Dual Address Synchronous Bus Data Transfer):
Each of the 1000 transfers requires two bus arbitration cycles (bac) one for the DMAC to
become master and one for the CPU to become master, and two bc for the actual transfer.
assume that both transfers required for the DMA transfer are completed in one bac. That
is, the DMAC can keep the bus to make both transfers.
Each block of transfers requires 1 setup (40 bc) and 1 interrupt at the end for synchronization (5 bc + 40 bc)
Processor time: 85 bc
Bus time: 85 bc + 2000 DMA bc + 2000 bac. If a 4-wire bus arbitration mechanism were
to be used, then there would not be any of the bac required.
Performance Summary
XII - 46
595
I/O Performance Implicit Addressing

DMA Times (Implicit Address Synchronous Bus Data Transfer):
Each of the 1000 transfers requires two bus arbitration cycles (bac) to transfer, and one
bc for the actual data transfer.
Each block of transfers requires 1 setup (40 bc) and 1 interrupt at the end for synchronization (5 bc + 40 bc)
Processor time: 85 bc
Bus time: 85 bc + 1000 bc + 2000 bac
Performance Summary
XII - 47
596
I/O Performance
If we assume that 3-wire is used, and that bus arbitration is comparable to a memory bus-cycle
(it will be faster in many cases) and as a result 1bc = 1bac. The following comparison results.
Synchronization
Polling
Periodic Polling
Interrupt
DMA (Dual)
DMA (Implicit)
Processor Time
10 seconds
(400,000,080 bc)
Bus Time
10 seconds
(400,000,080 bc)
25,080 bc
85 bc
85 bc
25,080 bc
4085 bc (2085 bc + 2000 bac)
3085 bc (1085 bc + 2000 bac)
Note the savings on the synchronization side.

The actual transfer time in all cases is slightly more than 10 s.
Also note the impact of changing the bus cycle time from 25 ns to 250 ns: the number of bus
cycles required for polling drop by a factor of 10, while the others stay the same.
Performance Summary
XII - 48
597
What is Performance of an I/O System?

An I/O activity has (at least) three participants:
the I/O device,
the processor, and
the I/O interface.
Performance is a relative concept. Perspective is everything.
Consider performance from the following perspectives (see Part I of the notes)
The device sees the best performance with polling: the data is picked up more quickly
with polling than when interrupts are used.
The processor may perceive the best performance with interrupts: the processor performs
fewer instructions when interrupts are used. As a result, there is more time to do other
tasks, and computing resources are used more effectively.
The overall cost/complexity may be better with polling: the polling interface is less complex
and may be less costly
Performance Summary
XII - 49
598
What is the Performance of an I/O System?

Device Perspective
Latency: How long is the delay between the data being available and the data being read
(by the CPU or DMAC).
Transfer Rate: How quickly is the data transferred out of the buffer?
Effective Transfer Rate: What is the highest sustained rate of transfer?
Processing Hardware Perspective
How much processing time is needed for the transfer?
How much bus time is needed for the transfer?
Device latency: How long is the delay between making a request and the first data item
being available?
Transfer Rate: How long is the delay for subsequent transfers?
Effective Rate: What is the highest sustained rate of transfer?
Performance Summary
XII - 50
599
Questions of Interest: DMA Questions
Terms and times discussed in this section include: Burst, Cycle Stealing and Transparent.
Signal connections: Which unit drives which signals? Which units use which signals?
for each of the DMAC structures in the DMAC architecture subsection (starting on page 572) consider the impact of
switching from a one bus to a separate memory and I/O bus structure. Also consider the impact on the performance of the
systems.
How could DMA techniques be used to facilitate a memory to memory transfer?
How could you structure DMA to permit more than one memory address to (receive) the data from the interface?
How could you structure DMA to permit transfers from device interface to device interface. (For example, could you use
DMA to transfer data from one serial interface to another?)
How could you use DMA if you did not know the size of the block to transfer? (For example, the size of a block of data
coming from the internet may not be known until the first few bytes of the block are received.)
Detached performance vs integrated performance
Dual address vs implicit addressing
interaction between bit-stuffing and DMA.
Performance Summary
XII - 50.1
600
Note: Terms used in DMA Section

Terms:
Cycle Stealing (page 561)

Transparent (page 561)
Burst (page 561)
Integrated DMA Controller (page 572)
Detached DMA Controller (page 572)
Dual Address Protocol (page 572)
Implicit Address Protocol (page 572)
Continuation Registers (page 589)
Data Chaining (page 590)
Performance Summary
XII - 50.1
Section XIII:
Grounding, Shielding and Transmission Line Issues
f2014-1.0
602
Section Contents: Shielding, Grounding and Transmission Lines

Introduction and Resources (starting on page 603) This section of the notes covers a number of realities in digital circuit design.
This subsection provides some structure to the remaining notes in the section.
Grounding (starting on page 605) Considers issues associated with grounding. Of particular note is the impact of different paths to
ground on the interpretation of the resulting signal levels.
Shielding (starting on page 613) Considers the needs to shield some circuits from outside influences. Various shielding requirements
are examined. Techniques to transfer signals from one shielded environment to another are also examined. The techniques considered
are optical fibre, balanced, single-ended, opto isolators.
Transmission Lines (starting on page 627) Transmission lines could be a complete course. The differences between lumped and
distributed circuit models are introduced and situations when transmission line effects are significant to the digital designer are
presented. The characteristic impedance expression (Z0 ) is derived and its meaning examined.
Reflections in a Linear System (starting on page 650) Reflections in linear systems, source and load matching, and the linear reflection
coefficient (Labelled as in some literature.). Analytical and graphical solution techniques are shown.
Reflections in a Non-Linear System (starting on page 662) Although analytical solutions to non-linear load and source impedances
are beyond the scope of this course, a graphical technique is described that can be used to estimate the amount of time required for
a given transition to settle to a final value.
Section Contents: Grounding Shielding and Transmissions Lines
XIII - 0.1
603
Introduction
Resources:
Vranesic and Zaky section 10.2, 10.3 and 11.4.1.
Stone: 2.1, and 2.2
Transmission Lines only:
National Semiconductor Application Note AN-806
(http://www.national.com/an/AN/AN-806.pdf). This provides an introduction to transmission line characteristics.
National Semiconductor Application Note AN-807
(http://www.national.com/an/AN/AN-807.pdf). This provides an introduction to transmission line effects (reflections).
In fact the National Semiconductor Application Note site contains many
interesting notes:
http://www.national.com/appnotes/apnotes all 1.html)
Introduction and Resources
XIII - 1
604
Introduction
Already a number of realities are

known:
gate delay is not zero,
all gate delays are not the same,
frames may be lost in serial transmission.
buses
propagation time,
skew time
Introduction and Resources
Added reality topics:

Grounding issues (starting on
page 605)
Shielding issues (starting on page
613)
circuit paths, not included in
the original design
Transmission line effects (starting
on page 627)
XIII - 2
605
Grounds
Ground has been used in this course (and others) to refer to several different concepts. In this
section it is necessary to separate this term into a number of different ideas.
Signal Ground: A point in a circuit used to reference all signal values. This point is often
considered the zero voltage point.
It is possible to separate the AC component of a signal from the DC component of a signal.
Hence there could be separate reference points for each component. It is also possible to
separate analog signals from digital signals and use different reference points.
DC Ground : The reference point for all DC signals in a given circuit block.
AC Ground : The reference point for all AC signals in a given circuit block.
Digital Ground : The reference point for all digital signals in a given circuit block.
Analog Ground : The reference point for all analog signals in a given circuit block.
Shield Ground : It is often important to shield a circuit (or a cable). As described later,
one requirement for this is a shield ground.
Building Ground : The point in a building where the power lines are attached to earth
ground.
Earth Ground : The common point used to reference building grounds.
Grounding
XIII - 3
606
Connecting Grounds
Although it is convenient to consider the different grounds as distinct, they are all connected.
The figure below illustrates the floor-level connections.
rooms1.
Power
Panel
On each floor there will be a power panel that will provide ground
to the various outlets on that floor. Note: some grounds are common
in the same room as the equipment, while other grounds do not get to
a common point until the power panel.
Grounding
XIII - 4
607
Connecting Building Grounds Direct Connection

The building grounds may be directly connected.
buildings.
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
The ground connection in each power panel is routed to a common

panel (not shown) and then to an outside ground. In this case a
conductive pipe is assumed.
Grounding
XIII - 5
608
Connecting Building Grounds Ground Rods

The building grounds may be connected via ground rods and the earth.
buildings1.
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Power
Panel
Appropriate number
size and spacing of
ground rods.
The ground connection in each power panel is routed to a common
panel (not shown) and then to an outside ground. In this case
ground rods are used.
Grounding
XIII - 6
609
Chassis Grounding - Close Proximity

Consider 2 chassis in close proximity
ground1a.
VGA = I1*R1
(WRT Building Ground)
VGB = I2*R2
(WRT Building Ground)
Connect Chassis Ground

IGL
+
VGA
-
I2
Resistance in
R1 the Ground R2
Connection
I1
+
VGB
-
Building Ground
Grounding
XIII - 7
610
Chassis Grounding Close Proximity - Continued

Note: VGA and VGB are voltages with respect to some common point.
Ground Loop: The current flow in the ground circuit. (As distinct from the current flow
in the neutral signal.)
The ground loop current is:
IGL VGA VGB = I1 R1 I2 R2
If current flow to the building ground (i.e., in this case the first point in common in the
ground path) causes a different voltage drop in each line, (either because I1 6= I2 or
R1 6= R2) then VGA 6= VGB and IGL 6= 0.
aggravated as voltage differences increase.
thus two chassis should only be connected if there is only a small difference in voltage
levels (VGA VGB ) and thus the ground loop current IGL is small. For example,
computers in a single rack or plugged into a common receptacle.
Grounding
XIII - 8
611
Chassis Grounding - Significant Separation

ground2a.
VGA = I1*R1
(WRT Building Ground'
V'Gnd)
VGB = I2*R2
(WRT Building Ground''
V''Gnd)
Significant
Distance
(CPH and DC)
Connect Chassis Ground

IGL
CPH
I2
I1
R1
Resistance in the Ground

R2
Connection
VGnd = V'
Gnd-V''Gnd -
VGA
Building Ground'
V'Gnd
(at CPH)
DC
+
VGB
Building Ground''
V''Gnd
(at DC)
Earth Ground
(real?)
Grounding
XIII - 9
612
Chassis Grounding Significant Separation - Continued

The ground loop current is:
0
00
IGL (VGA + VGnd
) (VGB + VGnd
)
= I1 R1 + VGnd I2 R2
The voltage differential may be several volts, and the ground loop current IGL quite large.
(possibility of severe damage).
This leaves several problems:
if we pass signals between buildings as a value (voltage) then we must also share
grounds (leading to ground current).
if we need to shield the signals from external interference then the shield must be
attached to ground.
Grounding
XIII - 10
613
Shielding - Sources
Some circuits need protection from electromagnetic interference.
Sources:
computers and other digital systems 1 MHz - 3000 MHz
AM radios 455 kHz
FM radios 10.7 MHz
AC power lines 60 Hz
Most common protection is a shield:
enclose circuit in a metallic conductive cage,
enclosure remains at the same potential, and
external radiation raises or lowers the cage potential
but, the details are beyond scope of the course.
The remainder of this subsection of the notes considers the impact of adding shielding
to digital circuits.
Shielding
XIII - 11
614
Shielding - Floating
Can the shield be left to float?

Consider an ungrounded
shield
As frequency increases, (the
parasitic capacitance) C3
passes more signal back to
the input.
Consider the feedback voltage
2
V = Z1Z+Z
Vout
2
shield1.
Equivalent Circuit
C3
C3
C1
Vout
Note
Feedback
Vout
C1
C2
V
C2
Shield
Shielding
XIII - 12
615
Shielding - Grounded Cage

shield2.
Equivalent Circuit
C3
C3
C1
C2
Shield
C1
No Feedback Path
Shield Rule #1. The shield of an electronic circuit must be connected to the
signal ground (the zero reference point) of that circuit in order to reduce or
eliminate the feedback effects induced by the shield.
Shielding
XIII - 13
616
Multiple Chassis Shielding Zero Ref. Point to Shield - Option A

Now extend to signals transmitted between two chassis. Assume that circuits in both
chassis are within shields (and the shields are to be connected).
Option A: shield to zero reference point and zero ref. point to ground at different points.
(This is the bad choice!)
Chassis
Shield
Signal Zero
Ref. Point to
Ground
AC Ground
Rule 1: Shield
to Zero Ref. Point
shield3aintro.
Shielding
XIII - 14
617
Multiple Chassis Shielding Zero Ref. Point to Shield - Option A
Shield
Chassis
Noise Current
in signal line
Noise Source
shield3a.
Ground loop current changes the zero ref. point. erroneous voltage levels. The AC
component of the ground current can be treated as a noise source.
Should attempt to minimize current flow in zero ref. line.
Shielding
XIII - 15
618
Multiple Chassis Shielding Zero Ref. Point to Shield - Option B
Shield to zero ref. point

and zero ref. point to
ground at the same point
(Preferred).
Current flows in shield
rather than in the zero
ref. line.
Shield Rule #2: The
shield should be connected to the earth
ground at the zerovoltage
reference
point for the input
signal.
Remember shield ground
and signal ground in serial section of the notes
(See Serial notes (starting on page 229) ).
Shielding
shield4a.
Noise Current
in shield
Noise Source
XIII - 16
619
Multiple Chassis Shielding - As the distance increases

Problem: what if the chassis are so far apart that the shields cannot be connected safely?
(Issue: potential for high IGL.)
Alternative: do not connect the two shields (and hence there is no ground path). But
how?
do not pass signal electrically (optical fibre or opto-isolator)
do not reference the signal to a ground/zero reference point. Pass the reference point
and the signal between the chassis.
Shielding
XIII - 17
620
Multiple Chassis Shielding - Optical Fibre Links
Neither shield nor

Ground are connected
Fibre Optic Cable
Noise Source
shield5a.
Shielding
XIII - 18
621
Multiple Chassis Shielding - Optical Isolator
Shields and Grounds

are not connected
Noise Source
shield6a.
Shielding
XIII - 19
622
Multiple Chassis Shielding - Balanced Connection (Non-optical solution)

Pass signal as two wires, not as one signal plus ground.
Common technique: balanced connections.
use twisted pair cable
use balanced drivers and receivers
balanced driver
two (complementary) outputs
(one high the other low)
transitions very close to the same
time
balanced receiver
two inputs
comparator
(Output = V + > V )
High input impedance
balanc1.
Balanced Transmitter
+
Balanced Receiver
Interference raises and lowers both signal lines and thus if the receiver compares the two
values it may be unaffected by the interference.
Common Mode Rejection Ratio: The ability of the receiver to ignore the changes common
to both input lines is indicated by the receivers common mode rejection ratio.
Shielding
XIII - 20
623
Multiple Chassis Shielding Balanced Connection - Receiver and Transmitter
balanc2a.
Shields are not connected
Noise Source
Shielding
If grounds are at the same

potential.
very little current
flows
most of this current is due to signal
value.
voltage drop in the
signal lines is minimal.
therefore the voltage levels at the input and output are
more or less the
same.
XIII - 21
624
Multiple Chassis Shielding Balanced Connection - Receiver and Transmitter
balanc2a.
Noise Source
Shielding
If the grounds are at different

potentials.
current flows in both of
the twisted pair lines.
but all of the voltage
drop, due to ground current, will be across the
receiver (as it has the
high impedance).
balanced receiver will
cancel (subtract) common mode signal.
This technique attempts to
admit that there will be noise,
however it will tend to cancel
some of its effect.
XIII - 22
625
Multiple Chassis Shielding Balanced Connection - Receiver Only

Compare balanced transmitter and receiver with a balanced receiver only approach. This
is described in the RS-422 and RS-423 section of the notes (starting on page 689) .
Noise Source
balanc3a.
Twisted-pair, balanced receiver will cancel external noise.
Shielding
XIII - 23
626
Multiple Chassis Shielding Balanced Connection - Receiver Only

Assume a power supply with VS and VS .
thus a one for a balanced driver is +VS on one line and VS on the other, while a
zero is a VS on the first line and a +VS on the other line.
for the single-ended driver a one has a value of +VS and a zero has a value of VS
V+
Balanced
VS
Single Ended VS
Shielding
At the Receiver
0-Level
1-Level
Noise Margin
V (V + V ) V + V (V + V )
VS
2VS
VS VS
2VS
2VS
0
VS
VS
0
VS
VS
XIII - 24
627
Transmission Lines - Introduction

Not intended to replace an ECE 370 like course.
Consider the following lumped model of a circuit.
trans1.
Switch closed at T=0
+
V1
-
RS
RL
Waterloo
Toronto
Transmission Lines
How much current will flow immediately following T=0?

Previous courses have all dealt with low
speed circuits, where it was reasonable
to assume that signal propagation was
instantaneous and the signal received
was the same as the one sent by the
transmitter.
High-speed circuits suffer transmission
line effects:
signal distortion and
signal delay.
XIII - 25
628
When are Transmission Line Effects Important?

When the wavelength is comparable to the size of the circuit.
Consider sinusoidal signals on wires, nominally at the speed of light (more later).
the wavelength () of electro-magnetic waves in free-space (a reasonable estimate
for our purposes here) is
c
f
where c is the speed of light (3 108 m/s) and f is the frequency of the wave.
is about one (very large) hand span if we take f to be 1 GHz (109). = 0.3
meters.
recall that a square wave is composed of a number of higher frequency odd harmonics.
Thus circuits of 1 to 3 cm may have transmission line effects if they are expected to
operate at 1 GHz.
Transmission Lines
XIII - 26
629
A Small Section of a Transmission Line

Distributed Model: consider a small section of the transmission line (idealized). Assume
the length is x.
trans2.
v
Iin
+
Vin
Transmission Lines
At time 0, Vin = V1 (the voltage applied to the transmission line),

Current i starts to flow through the inductor (in the first section of the transmission line)
As the current charges the capacitor,
the voltage across the capacitor increases, and the increasing voltage is
applied to the next section of the transmission line.
Exact expressions are beyond the scope
of this course however ... we can consider a sinusoid simplification ...
XIII - 27
630
A VERY Small Section of a Transmission Line

Consider the following, less ideal, model of a section of a transmission line.
L, R, G, and C are values per
unit length. Recall from ECE
140, GenE 123 or ME 123
that the conductance (G) relates voltage and current as:
I =GV
trans3a.
dV
Iin
R
dI
C
Vin
dx
Transmission Lines
XIII - 28
631
The Voltage and Currents on A VERY Small Section of a Transmission Line

Consider the same (less ideal) segment of the line.
trans3.
dV
Iin
+
Vin
RI
L
- +
jLI
jCV
dI
GV
Consider a simple sine wave

(j)
dV = (Rdx + jLdx)Iin
(1a)(I.e. Voltage drop)
dI = (Gdx + jCdx)Vin
(2a) (dI is the current that is
diverted from the signal and
may be considered the effective current loss/drop)
dx
Note: jLI is the incremental voltage drop across the inductor
and jCV is the incremental change in the current caused by
the capacitor
Transmission Lines
XIII - 29
632
A VERY Small Section of a Transmission Line - Continued

For simplicity of notation, the in subscripts have been omitted from the rest of this
presentation.
Or in a more conventional form
dV
dx
= (R + jL)I (1)
dI
dx
= (G + jC)V (2)
Transmission Lines
XIII - 30
633
Overview of Derivation of Z0
Differentiate (1) w.r.t. x
d2 V
dx2
dI
= (R + jL) dx
, but we know
Substituting for
d2 V
dx2
dI
dx
dI
dx
from (2)
results in (2)
= (R + jL)(G + jC)V or
d2 V
dx2
= 2V (3)
where (R + jL)(G + jC) = 2.

And (3) has a solution of the form
V (x) = V 0ex + V 00ex (4)
where V 0 and V 00 are constants.
note this is an expression for the voltage wave as a function of x, the distance along
the transmission line.
similarly I = I 0ex + I 00ex (5)
Transmission Lines
XIII - 31
634
Differentiating (4) and substituting for I leads to
dV
= V 0ex + V 00ex (= (1))
dx
= (R + jL)I (replace I with (5) )
= (R + jL)(I 0ex + I 00ex)
= (R + jL)I 0ex (R + jL)I 00ex
Now by equating similar exponents. Note similarity with V = RI.
For ex V 0 = (R + jL)I 0
(6)
For e+x V 00 = (R + jL)I 00

Transmission Lines
XIII - 32
635
Using the expression for ex (6) and

Ohms Law (R = VI )
V0
=
0
I
(R + jL)
(R + jL)(G + jC)
v
u
u
u R + jL
u
= u
t
(G + jC)
= Z0
(I.e. Z0 is the ratio of voltage to current!)
or the Characteristic Impedance of the
transmission line.
r
Transmission Lines
or
Z0 =
Similarly
V 00
I 00
v
u
u
u
u
u
t
R + jL
G + jC
= Z0.
XIII - 33
636
Note: An Alternative Derivation

An alternative derivation for Z0 is presented in National Semiconductor Application Note AN-806
http://www.national.com/an/AN/AN-806.pdf. This derivation is based on an infinite sequence of lumped impedances.
small segment of line
trans3c
Zs= x * (R+jwL)
R
Zp=1/(x*(G+jwC))
Zp
Length x
Transmission Lines
XIII - 33.1
637
Note: Alternative Derivation Extending this to an Infinite Line

larger segment of line
Calculate the input impedance,

based on an assumed characteristic
impedance of Z0 (as shown).
trans3b
Zs
Vin
Zp
length x
Assume
impedence= Z0
Repeated
to infinity
Zs
Zs
Zp
length x
Transmission Lines
Zin
=
=
Zs + Parallel(Zp , Z0 )
Z0 Zp
Zs +
Z0 + Zp
Zp
length x
XIII - 33.2
638
Note: Alternative Derivation Completing the algebra

But Zin must also be equal to Z0 in the infinite chain. Thus
Z0
Zs +
(Z0 Zs )(Z0 + Zp )
Z0 Zp
Z02 Z0 Zs Zs Zp
Z0 Zp
Z0 + Zp
Using the quadratic formula and then substituting for
Zs
x(R + jL)
Zp
1
1
G + jC x
Results in the following (if we assume that length shrinks to very small) and the only term remaining (the lengths have cancelled) is
Z0 =
Transmission Lines
v
u
uR
t
+ jL
G + jC
XIII - 33.3
639
What is Z0 and the Speed of Transmission?

What does it mean (for our purposes)?
voltage (current) at any point x on the line is the sum of two waves, one moving east
and one moving west. There are times that the terms incident and reflected may be
used to differentiate between these two waves.
Characteristic Impedance (Z0): The ratio of the propagated voltage to the propagated current at every point on the line. Z0 is the characteristic impedance of the
line.
special case: R 0 and G 0, Z0 =
L
C.
(On Page 534 in V&Z Chapter 10)
propagation speed along the transmission line

s=
1
LC
(Stated, not proven, in V&Z)
If L is measured in henrys per meter and C is measured in farads per meter then s
will be in meters per second and Z0 in ohms.
Transmission Lines
XIII - 34
640
Note: More Comments on the Special Case

When can the R and G terms be ignored in the Z0 expression?
Z0 =
v
u
uR
t
+ jL
G + jC
As increases, the impact of R and G decreases. When the frequency increases, the terms multiplied by start to dominate.
(Conversely if is small the R and G terms may increase in importance.)
For frequencies above 100 kHz ( > 628 krad/s) it is reasonable to assume that transmission line effects have started to
set in.
Transmission Lines
XIII - 34.1
641
What is Z0 and the speed of Transmission? - Example

For example: L = 0.4 H/m and C = 70 pF/m
s
Z0 =
s=
0.4106
701012
= 76 and
1
0.4701018
= 1.89 108 m/s
Note the relationship with c used in the earlier motivating example.
Transmission Lines
XIII - 35
642
Note: Current Question

Previously we have assumed that the current flow in a line (a bus line in particular) could be estimated by:
I=C
dv
dt
(Assuming time is in seconds, voltage in volts and capacitance in farads, the result will be current in amperes).
If we assume a voltage step, and long lines, the current appears to grow linearly with length. In the case of cables, C is specified per
meter. However, the transmission line model provides an alternative view: the initial current is constrained by Z0 . (I = ZV0 )
Transmission Lines
XIII - 35.1
643
Note: Initial Current Flow (continued)

How do the currents predicted by the two models compare? See next slide for example using previous transmission line, a step from
0 to 3 volts in time t (1 ms to 1 ns). It should be noted that both of these estimates are abstractions and one must be aware of
both models. For our purposes it is reasonable to assume that the actual current flow will be the smaller of the 2 calculations.
On the figure note the following:
3V
12 pF
At low slew rates (1 ms rise time) I = C dv
[ m ]100 m 0.001
dt constrains the current. For example, at 100 m I = 7010
s =
2.1 105 A.
At high slew rates (1 ns rise time) the transmission line effect will limit the current and the estimate of the current based on
Z0 is better for all of the lengths of the transmission lines shown. For example, I =
on the next page.
3V
76
= 40 mA, the solid horizontal line
Between these extremes note that as the length increases, the slew rate necessary for the transmission line effect to constrain
the initial current flow decreases. (And vice-versa.)
The remainder of the notes on transmission line effects assume that the slew rate is fast enough that Z0 is the correct way
to estimate initial current flow.
Transmission Lines
XIII - 35.2
644
Note: Alternative Views of Current

discussionCurrent.
Current Calculations (C dv/dt vs V/Z0)

1.00E+05
1 ns
1.00E+04
Initial Current (AMPS)
1.00E+03
1.00E+02
1.00E+01
1.00E+00
1.00E-01
1.00E-02
1 ms
1.00E-03
1.00E-04
1 ms
100 microS
10 microS
1 MicroS
100 nS
10 nS
1 nS
Char Imp.
70 pF/meter Capacitance
0.4 microH/meter Inductance
Line length in Meters
1.00E-05
1.00E-06
10
100
1000
10000
100000
Line Length (m)
Transmission Lines
XIII - 35.3
645
Sample Cable Specifications
One part of the Belden site http://www.belden.com/pdfs/03Belden Master Catalog/2006 Belde
Transmission Lines
XIII - 36
646
Operation of Transmission Lines - Initial State

Now that we can compute Z0 we can look at how to estimate the behaviour of the signals after
the switch is closed (or opened).
An alternative presentation of these ideas is found in National Semiconductor Application Note
AN-807(http://www.national.com/an/AN/AN-807.pdf).
Consider the following situation
Transmission line (Z0)

RS
Ir
Ii
VS
Load ZL
trans4.
Transmission Lines
XIII - 37
647
Operation of Transmission Lines - Immediately After Time T0
At time T=0, the switch

closes, how much current
flows?
the current matches the
impedance of the line
(Z0). I.e. Vi = VS
Vi
Z0
and
I
=
i
Z0 +RS
Z0
But what happens when the
propagating wave reaches
ZL?
The current-voltage
relationship
must
obey
Ohms Law at the load.
(I.e. IL = ZVL . If ZL = Z0
L
then Ohms Law is satisfied.
Otherwise?)
Transmission Lines
trans4a.
Equivalent Circuit when T = 0

Ir
+
Ii
RS
VS
IL
Z0
Voltage Across Z0 = Z0 * I
and I = VS/(RS+Z0)
Therefore Vi = VS*Z0/(Z0+RS)
VL
-
Load ZL
XIII - 38
648
Operation of Transmission Lines - At the Load One Propagation Delay Later

There will be a reflected wave generated so that Vr , and Ir add to the incident wave to
make a combined value at the load that obeys Ohms Law.
Note VIii = Z0 6= VI L = ZL but
L
* IL = Ii Ir and Ir = ZVr0
and
* VL = Vi + Vr
(from Vr = VL Vi)
trans4b.
Ii
Vr
Ir
V
i
I =V /Z
L L L
RS

VS
V =V +Vr
L i
I=Ii-Ir
Ir=Vr/Z0
Transmission Lines
Load ZL
XIII - 39
649
Note: Possible Concerns

About this point there is often some concern about the signs of the VL expression.
One option is to consider the voltage at any point on the transmission line as the sum of the voltage associated with the voltage
waves (I.e. VL = Vi + Vr ).
An alternative is to consider the conservation of power argument sketched below.
Currents:
IL = Ii Ir (Note direction of current flow
shown in figure)
Ii = ZV0i (Magnitude of current wave)
Ir = ZVr0 (Magnitude of current wave)
Transmission Lines
Incident power (before reflection) must equal the sum

of the power dissipated in the load and the power
reflected.
Vi Ii
Vi2
Z0
2
Vi Vr2
Z0
2
(Vi Vr2 )
(Vi Vr )(Vi + Vr )
Vi + Vr
VL
=
=
=
=
=
=
=
VL IL + Vr Ir
Vr2
VL (Ii Ir ) +
Z0
V L Vi VL Vr
Z0
Z0
VL (Vi Vr )
VL (Vi Vr )
VL
Vi + Vr
XIII - 39.1
650
Reflections in a Linear System

Assume that the transmission line is ideal (I.e. R=G=0), and thus Z0 is real.
rho1.
VReflected
r=
VIncident
VIncident
VReflected
Impedance
Z
Transmission Line (Z0)
Note: (Using Vi and Vr for VIncident

and VRef lected)
Vi = IiZ0 and
Vr = Ir Z0 (i.e. the current wave
flowing into the transmission line
at either end sees an impedance
of Z0.)
Vi + Vr = (Ii Ir )Z. (I.e. the
net voltage and the net current
through Z satisfy Ohms Law.)
Reflection Coefficient : The reflection coefficient specifies the ratio of the reflected voltage
(current) to the incident voltage (current). It is useful as an abstraction only in systems where
the various loads and sources can be modelled as linear components. In some literature the
reflection coefficient is referred to as .
XIII - 40
651
Reflection Coefficient
These expressions can be manipulated to eliminate the I terms.
Vi + Vr = (Ii Ir ) Z
Vi
Vr
= ( )Z
Z0 Z0
Z0Vi + Z0Vr = ViZ Vr Z
Vi (Z0 Z) = Vr (Z0 + Z)
(Z Z0)
Vr
=
=
(Z0 + Z)
Vi
Similarly, is the reflection coefficient for current
Ir
Ii .
XIII - 41
652
Reflection Coefficient - Continued
Ir
Ii
ZS
VS
Load ZL
trans4c.
In this figure
The voltage reflection coefficient at the and the voltage reflection coefficient at the
source is
load is
ZS Z0
S =
Z0 + ZS
ZL Z0
L =
Z0 + ZL
XIII - 42
653
Reflection Coefficient - Characteristics

Note that 0 || 1
the magnitude of the reflected wave is never larger than the incident wave
the reflected wave can be negative
if ZL = 0 then = 1
if ZL = then = 1
if ZL = Z0 then = 0
if < 0 then the reflected (voltage) wave reduces (cancels part of) the incident
wave. In some ways this may be thought of a destructive interference.
if > 0 then the reflected (voltage) wave re-enforces the incident wave. (E.g. 0.5
V in, 1.0 V out! ?Perpetual motion?). (In some ways this may be thought of a
constructive interference.)
XIII - 43
654
Reflection Coefficient - Example #1: ZL = , L = 1
trans5.
Ir

Ii
ZS<<Z0
ZS = 0.01*Z0
Load ZL=inf
r =1
L
VS
At Source
VS
VS*Z0/(Z0+ZS)
=0.99*VS
1
At Sink
Time
(Propagation
Delays)
V=0.99Vs + 0.99Vs
1.98Vs
Vs
Load voltage changes at

T= 1, 3, 5, 7, ... propagation delays while the voltage at the source changes
at times 0, 2, 4, 6, .. propagation delays.
At the load end L = 1,
and at the source
0
S = ZZS Z
0.98,
+Z
0
S
At time 0 the switch closes
After settling VL = VS and
IS = IL = 0
Time
(Propagation
Delays)
XIII - 44
655
Reflection Coefficient Example #1: ZL = , L = 1 - Comments

Voltage
Reflected Voltage
Source
Sink
0
0
0
LVS1 = VS1
S (LVS1)
0
Time
Source
Sink
0
VS1
0
1
VS1
VS1 + L VS1 = 2VS1
2
VS1 + L VS1 + S (LVS1)
2VS1
(2 0.98)VS1
3
(2 0.98)VS1
2VS1 + S (LVS1)
0
L(S (LVS1))
+L(S (LVS1))
2VS1 1.96VS1
0.04VS1
To keep the table less cluttered, VS1 = 0.99 VS . That is the initial voltage applied to
the transmission line at time 0: VS1 =
Z0
(Z0 +ZS )
VS =
1
1.01
VS .
For example, in time step 2 (propagation delays) the voltage at the source is the sum
of: The original voltage (VS1), the incident voltage (LVS1) and the reflected voltage
(S (LVS1)).
XIII - 45
656
Reflection Coefficient - Example #2: ZS = Z0 S = 0(Line matched at source)
trans7.
Ir
Ii
ZS=Z0
Load ZL=inf
r =1
L
VS
At Source
S = 0; L = 1.
one round trip delay for the signal to
reach terminal value.
VS
2 is the initial value,
note impact on performance as a function of threshold.
Vs
Range of VThreshold
Vs/2
At Sink
Vs
Range of VThreshold
XIII - 46
657
Reflection Coefficient - Example #3: ZL = Z0, L = 0 ( Matched at Load )
trans6.
Ir
Ii
ZS<<Z0
Load ZL=Z0
r =0
L
VS
At Source
VSZ0/(Z0+ZS)
At Sink
VSZ0/(Z0+ZS)
Line settles in 1 propagation delay

Note, as ZS increases the
final value shrinks, therefore try to make ZS as
small as possible.
After settling
VL
=
!
L
VS Z Z+Z
(Z0 is not
L
S
part of the long term
expression!) In this case
ZL = Z0.
Note the current at the
load: the load is not
high impedance. This is
quite different from the
bus transceiver assumptions earlier in the term.
XIII - 47
658
Reflection Coefficient - Example #4. Generalized problem
Ir
Ii
ZS
Load ZL!=Z0
VS
trans8.
S =
ZS Z0
Z0 +ZS
6= 0; and L =
After settling: VL =
ZL Z0
Z0 +ZL
L
VS Z Z+Z
L
S
6= 0
(Z0 is not part of the long term expression!)
Note: multiple receivers/loads is the norm! Each tap may be considered as a separate
transmission line.
XIII - 48
659
Application Alternatives for Linearized Model of Reflections

Wait long enough for the reflections to die out (I.e. make no attempt to reduce the
reflections.)
acceptable for low speed applications.
Match impedance at the load: no reflections, but ...
typical (50 wire) ribbon cable Z0 150
if the signal level is 5V, the load current is 33 mA and
the power is 165 mW (per wire).
if 50% duty cycle then 83mW per wire,
if 50% of the wires are not ground, then 2.1 watts are consumed to reduce reflections in 1 cable.
Match impedance at the source.
hence only one reflected wave
can use high impedance receivers and thus there is only a small steady state current
XIII - 49
660
Graphical Organization for Voltage Calculations for Linear Components
Assume that a system is composed of

linear source and termination resistors.
trans9.
Ir
Transmission line (Z0=93)
ZS=25 Ohms
VS=1V
Load ZL=inf
V
Ii
XIII - 50
661
Graphical Organization for Voltage Calculations for Linear Components
trans9a.
Ir
ZS=25 Ohms
Load ZL=inf
VS=1V
Ii
r =1
L
r = -0.58
S
0.0V
Note: the two stable (long

term) points are: Switch
open, VL = 0, and Switch
closed, VL = VS .
1*(93/(93
+25)) = 0
.79V
0.0 + 0.79
0.79
0.79+0.79-0.46
= 1.12
(Note
0.46= -.58*0.79)
0.79+0.79
= 1.58
-0.46
1.58-0.46-0.46
= 0.66
-0.46
1.12-0.46+0.26
=0.92
0.26
0.26
0.66+.26+.26
=1.18
0.88
XIII - 51
662
Graphical Evaluation Techniques

The graphical technique described here can be used for systems with either linear and non-linear
source and load impedances. Consider the same example only use load lines this time.
trans10.
Ir
ZS=25 Ohms
Load ZL=inf
VS=1V
Ii
1/Z0
40 ma
40 mA
40 mA
-1/Z0
-1/ZS
1/Z0
0
1
1V
1V
Reflections in a Non-Linear System
Slope -1/Z0
1V
Slope -1/Z0
XIII - 52
663
Graphical Evaluation Techniques - At the Source

The load line from VS and the 25 resistor is a line with a slope of
1
ZS
as shown running
from 40 mA and 0V through 0 mA and 1V.

The line from the origin (with a slope of
1
Z0 )
represents the acceptable points for the
transmission line impedance.

Their intersection (0) corresponds to the initial voltage wave transmitted along the transmission line.
0.79V, and I 8 mA
XIII - 53
664
Graphical Evaluation Techniques - At the Load

The load line associated with the Load (ZL) is the X-axis (i.e. any amount of voltage
results in 0 mA current flow).
The load line for the transmission line is a line with a slope of
1
Z0
passing through the
point 0. It crosses the ZL load line at point 1.

These two lines intersect at the Load Voltage, Load Current at the load after 1 transmission
delay.
1.58V, 0 mA
This can now be repeated, next a line with slope
1
Z0
passing through 1, then
1
Z0
passing
through 2 etc.
XIII - 54
665
Graphical Evaluation Techniques

Now consider an example with a load resistor and still only use load lines.
trans10a.
Ir
Transmission line (Z0=93 W)
ZS=25 W
Load ZL= 10 W
VS=1V
Ii
40 ma
1/Z0
40 mA
1/ZL
40 mA
-1/Z0
5
-1/ZS
3
1
1/Z0
1
Slope -1/Z0
1V
1V
4
2
0
V
1V
XIII - 55
666
Graphical Evaluation Techniques - Comments and Example Introduction

Please note the following:
The reflected current is out of the load, and thus in the opposite direction to the current
shown in the I-V plot. Hence the slope of the line associated with the reflected wave is
negative.
The voltages and currents can be read directly from the I-V plot, however the voltages and
currents between the points are meaningless. There is only meaning at the intersection
points.
Even numbered points are at the source.
Odd numbered points are at the load.
Consecutive points are separated in time by one propagation delay.
Nonlinear examples next:
Z0 = 50 (or 2V 40 mA)
Z0 = 100 (or 2V 20 mA)
Z0 = 200 (or 2V 10 mA)
XIII - 56
667
Examples (Worked in class)
30mA
Output (High)
20mA
10mA
-2V
-1V
1V
2V
3V
4V
5V
-10mA
-20mA
-30mA
Output (Low)
Input
iv1.
XIII - 57
668
Example 50 Cable
Estimate values for a 0 -> 1 transition on a 50 W cable
30mA
Output (High)
20mA
10mA
-2V
-1V
1V
2V
3V
4V
5V
-10mA
-20mA
-30mA
Output (Low)
Input
iv1 50.
XIII - 58
669
Example 100 Cable
30mA
Output (High)
20mA
10mA
-2V
1V
-1V
2V
3V
4V
5V
-10mA
-20mA
-30mA
Output (Low)
Input
iv1 100.
XIII - 59
670
Example 200 Cable
30mA
Output (High)
20mA
10mA
-2V
-1V
1V
2V
3V
4V
5V
-10mA
-20mA
-30mA
Output (Low)
Input
iv1 200.
XIII - 60
671
Examples (Worked in class)
30mA
Output (High)
20mA
10mA
-2V
-1V
1V
2V
3V
4V
5V
-10mA
-20mA
-30mA
Output (Low)
Input
iv1.
XIII - 61
672
Questions of Interest: Questions?
Make sure you understand the terms listed on the next page of the notes.
Given L and C for a transmission line, calculate: Z0 and s.
Using your results from above, a (linear) source impedance, a (linear) load impedance and a transmission line of given length,
calculate the reflection coefficients and the wave form at each end of the transmission line assuming that there has been a
0 V to 10 V step at time 0. (repeat for a 10 V to 0 V step at time 0.)
Compare and contrast source and load matching. Consider any impact on the designer, builder and user of these schemes.
How would the use of an unmatched transmission line affect the operation of your system?
Why is a ground loop a problem for some systems?
Why might a designer separate the analog and digital grounds in a system?
How does current in a zero reference line affect a system?
XIII - 61.1
673
Note: Terms used in Grounding Shielding and Transmission Lines

Terms:
Signal Ground (page 605)

DC Ground (page 605)
AC Ground (page 605)
Digital Ground (page 605)
Analog Ground (page 605)
Shield Ground (page 605)
Building Ground (page 605)
Earth Ground (page 605)
Ground Loop (page 610)
Common Mode Rejection Ratio (page 622)
Characteristic Impedance (Z0 ) (page 639)
Reflection Coefficient (page 650)
XIII - 61.1
Section XIV:
Examples (Signalling and Buses)
f2014-1.0
675
Examples: Section Contents

Introduction (starting on page 678) The examples can be thought of as in two groups: signalling examples, showing variations and
extensions to the electrical signalling examples used earlier in the notes; and bus examples, illustrating and extending the earlier
material in the course. These examples also show systems that combine various sections of the course into a single structure.
20 mA Current Loop (starting on page 681) The 20 mA current-loop is an example of passing digital information using current rather
than an absolute voltage value or a relative voltage value. This section also shows a sample circuit design that uses an opto-isolator.
It is another example of dealing with grounding realities.
RS-232 Electrical Signalling Properties (starting on page 685) Describes the RS-232 signalling levels and how cross-talk is handled
RS-232.
RS-422 and RS-423 Electrical Signalling Properties (starting on page 689) RS-422 and RS-423 provide improved signalling characteristics. Some of the differences are examined. Of particular note is the use of balanced transmitters and receivers as well as the
mixed mode of operation (RS-423). RS-449 provides one example of connecting grounds where there may be a different potential at
each end of the communication channel.
RS-485 Bidirectional Drivers (starting on page 692) RS-485 is a logical extension to RS-422. It provides the noise protection of
RS-422 and the flexibility of bidirectional communication. In fact, RS-485 provides for multiple drivers on a given pair of wires,
however only one driver can be enabled at a given instant.
Serial Peripheral Interface (SPI) (starting on page 698) A description of the operation of the SPI interfacing technique. SPI provides
an inexpensive, somewhat standardized technique for connecting peripheral devices to processing elements.
Excalibur Avalon Bus (starting on page 706) The Avalon Bus is an unconventional bus structure. It is based on non-shared
communication paths with multiplexers to select interconnections between masters and slaves.
VME Bus (starting on page 709) The VME bus example is used to show the use of termination resistors to provide load balancing.
It also shows the use of a daisy-chain wiring technique to facilitate multiple interrupt service providers.
Section Contents: Examples
XIV - 0.1
676
SCSI (Small Computer System Interface) Bus (starting on page 715) The SCSI bus is used to interconnect relatively complex devices.
The coverage emphasizes: the unique scheduling and data transfer structures (there are no address lines used during normal transfers,
and the T arget (somewhat like the slave) controls the transfer), and the use of one-hot addressing.
IEEE-488 (starting on page 732) The IEEE-488 bus structure is intended to be used to interconnect lab instruments. The structure
provides for multicast transfers (where one source can send to multiple receivers in a single transfer) that are fully-interlocked. In
this case there are also no address lines used during the transfer.
Peripheral Component Interconnect (PCI) (starting on page 742) PCI is used in many PC systems to connect complex device
interfaces. It is a bus structured for block transfers. The arbitration is based on a star connection.
Section Contents: Examples
XIV - 0.1
677
Resources
HV&Z, Section 4.7 (PCI, SCSI, and USB) (5th Edition)
V&Z Section 11.2 (VME Bus IEEE-1014)
V&Z Section 11.4 (Interface standards RS-232 etc. The higher level issues were discussed
in the serial interfacing section of the course notes.)
V&Z Section 11.5 (Peripheral Buses)
V&Z Section 11.5.1 Small Computer System Interface (SCSI)
V&Z Section 11.5.2 IEEE-488 Instrumentation Bus
B&B Electronics RS-422 and RS-485 Application Note
http://www.bb-elec.com/bb-elec/literature/tech/485appnote.pdf
A comparison of 422 and 485 can also be found in National Semiconductor Application
Note: AN-216 http://www.national.com/an/AN/AN-216.pdf
An application note that illustrates the transmission line effects related to termination
in an RS-485 system is provided by Maxim at
http://www.maxim-ic.com/appnotes.cfm/appnote number/763/ln/en
Other resources listed in the specific section.
Resources
XIV - 1
678
Electrical Signalling Examples

The design of any signalling system requires a number of issues to be considered, including
Grounding characteristics
Driving characteristics (voltage and current thresholds)
Noise characteristics
This section of the notes contains a number of diverse examples. Only some of these topics will
be covered in class in a given year.
The set of topics in this section of the notes is listed below.
20 mA current loop (starting on page 681)
RS-232 (starting on page 685) the higher levels were described in the serial section of the
notes. In this section, the lower level signal issues are examined.
RS-422, RS-423 and RS-449 (starting on page 689) describes the levels required and
considers balanced vs single-ended signalling.
RS-485 (starting on page 692) a half-duplex, multiple driver version of the RS-422 communication structure.
Introduction
XIV - 2
679
Bus Structure Examples

USB (starting on page 295)
Excalibur Avalon (starting on page 706)
VME (starting on page 709) The points here are the multiple interrupt management and
the impedance matching techniques.
SCSI (starting on page 715) The point here is the address encoding scheme (one-hot)
and the re-use of lines during arbitration.
IEEE-488 (starting on page 732) This is an example of asynchronous synchronization of
broadcasting to several bus addresses.
PCI (starting on page 742)
Introduction
XIV - 3
680
Electrical Signalling Techniques for Serial Communication

20 (or 60) mA current loop
dates back to motors and switches as the signal generators
very easy to implement
no standards exist
RS-232
not as old as 20/60 mA current loops
very common
RS-422, RS-423, and RS-449
more robust
permit higher transmission rates
RS-485
permits bi-directional, balanced communication
points out some of the issues discussed previously
Introduction
XIV - 4
681
Note: Interesting Antique: the 20 mA Current Loop

Although the 20 mA current loop is not used very often in modern circuitry, there are a number of ideas embodied in the 20 mA
current loop communication system. The ones of particular interest to an MTE 325 or ECE 224 student are listed below:
Digital signals are not always passed as an absolute voltage value.
By using current as the value, the problems described in the grounding section (starting on page 605) can be handled easily.
Each of these items is addressed while considering one implementation of a 20 mA current loop communication structure.
20 mA Current Loop
XIV - 4.1
682
20 mA Current Loop
Transmitter
Receiver
Serial Link
Current
Detector
N.B. The current source could be

in Tx or Rx.
serial4.
Use current instead of voltage

20 mA logic 1
0 mA logic 0
Designed for electromechanical teletypes (to drive solenoids)
the transmitter was a switch attached to a motor
the receiver was either a solenoid, or a relay
20 mA Current Loop
XIV - 5
683
Rs
Receiver
R0
R1
Opto-Isolator
Receiver Circuit
Transmitter
Serial Connection
20 mA Current Loop - Current Detector
serial51.
Component Selection
One option is to use an opto-isolator
Assume the transmitter provides: 20 mA with at least 4 V will be delivered to the receiver
and the voltage at the load will not exceed 12 V.
Assume the LED requires 10 mA to provide sufficient light to saturate the photo transistor.
There is 0.8 V drop across the diode when 10 mA are flowing through the LED.
Select R0 and R1 to limit LED current and voltage.
20 mA Current Loop
XIV - 6
684
20 mA Current Loop Advantages/Disadvantages

Advantages:
Opto-isolator can tolerate 1 kV to 2 kV across input/output gap so the significant separation slides (starting on page 611) described in the grounding section (starting on page
605) can be handled in a straightforward manner.
Good common mode rejection common mode voltage (raises or lowers both signal
lines) does not affect detector
Disadvantages:
No complete standard exists
20 mA Current Loop
XIV - 7
685
RS-232 Electrical Configuration
MC 1488
+12V
TTL
-12V
MC 1489
+5V
'1' < -3V

'0' > 3V
TTL
Signal Ground
Shield Ground
TTL => '1' >=2.0V

'0' <= 0.8V
serial9.
Standard components used for RS-232 systems (such as 1488/1489 above)

special characteristics include: 3V used as the 0/1 level
convert between more standard logic levels (TTL) with a 0 less than 0.8V and a 1
greater than 2.0V
The larger voltage swing the larger noise threshold
Ground loops are possible with this ground configuration
RS-232 Electrical Signalling Properties
XIV - 8
686
Implementation Issues - Cross-Talk

Problem: digital signals have sharp edges
harmonics at high frequencies
these harmonics couple easily into adjacent wires
mutual inductance
parasitic capacitance
Parasitic Capacitance
capacitor.
XIV - 9
687
Implementation Issues - Cross-Talk

Solution: eliminate (some) of the high frequency components in the signals
seria12a.
Change the slew rate of the signal (by modifying the drivers) and thus lower the power in
the high frequency harmonics.
RS-232 permits a slew rate 30 V/s (max)
For example: -15 V to +15 V in 1 s or -3 V to +3 V in 200 ns.
XIV - 10
688
Implementation Issues - Rise Time Control in a Current Loop
Receiver
Current
Limit
Stray capacitance charges exponentially

stray cap. charges linearly
The RS-232 drivers (MC-1488) have

built in current limit.
since
dV
I=C
dt
if
we
assume
that
I =constant
dV
I
=
dt
C
and hence no unit steps.
seria12b.
XIV - 11
689
RS-422/423 Standards
(HV&Z Section 11.4.2)
Other standards define standard drivers and receivers just as in the RS-232 case.
RS-422 a double-ended (balanced) interface
MC 3487
MC 3486
+3V/-3V
-3V/+3V
seria10a.
RS-423 an unbalanced interface with a maximum speed less than 20 kbps

specifications very close to RS-232
MC 8T13
(RS-232)
MC 3486
(RS-422)
3V/-3V
0V/0V
seria10b.
RS-422 and RS-423 Electrical Signalling Properties
XIV - 12
690
RS-422 and RS-423 Signal Levels
serial10c.
Logic 1
serial10d.
Logic 1
Logic 0
+3
Logic 0
+3
-3
RS-422 Signalling
-3
RS-232 and RS-423 Signalling
XIV - 13
691
RS-449 Standard: Mechanical and Connector Specifications

Note: all grounds were not created equal.
serial11.
transmit data
rcv data
transmit common
Ground
signal ground
DTE - "Terminal"
DCE "Modem"
receive data
receive common
transmit data
shield ground
no connection
100 Ohm resistors optional
RS-449 connection standard showing the connection
of an RS-423 unbalanced link
XIV - 14
692
RS-485 Communication Standard

Resources: B&B Electronics RS-422 and RS-485 Application Note
http://www.bb-elec.com/bb-elec/literature/tech/485appnote.pdf
Similar to RS-422 except multiple drivers and receivers permitted on each line.
Up to 32 drivers permitted (only 1 can be enabled at a time). The drivers provide tri-stated
differential signalling.
Parallel terminations are used, there are two termination resistors (one at each end of the
line).
As the stub-lines are not terminated, they should be as short as possible.
Although various structures could be used, a 2-wire and 4-wire model are the most common
in the literature.
RS-485 Bidirectional Drivers
XIV - 15
693
RS-485 Structure
485Structure
DataIn
Enable
DataOut
termination resistors
(120 W each)
at two ends only
2-Wire RS-485
Structure
XIV - 16
694
RS-485 Termination Issues
Cable: Z0 = 120 (Assumed)

Termination: parallel 120 on each
end. (60 resistance)
Bias: if no one is driving a differential
line, what will the value be? Include
extra resistors to pull the + and - lines
to a known value. (Limited current)
VA VB > 200mV
485Termination
VA
Floats to a valid
value when signal
is undriven
VB
XIV - 17
695
RS-485 Direction Control
The standard does not

(seem to) provide any
guidance on how to prevent two units from driving
the lines at the same time.
485FourWire.
Device B
4-Wire RS-485
Structure
Device A
Device D
Master Link
Device E
Device C
Device B
Device D
Slave Link
Device E
Device A
Device C
XIV - 18
696
RS-485/RS-422 Tabular Comparison

(A more complete comparison can be found at National Semiconductor Application Note: AN216 http://www.national.com/an/AN/AN-216.pdf)
Characteristic
Receivers
Drivers
RS - 422
Multiple
Single
Signal Rate (12 m)

Max Cable Length (100 kbps)
Driver Open Circuit Voltage
Loaded Output Voltage
Magnitude of Short Circuit Current
Receiver Common Mode Range
10 Mbps
1200 m
10 V
2.0 V
150 mA
7 V
RS - 485
Multiple
Sequentially single (Up to
32 drivers supported)
10 Mbps
1200 m
6V
1.5 V
250 mA
7 V to +12 V
XIV - 19
697
Note: Summary of Common Serial Signalling Standards

EIA
RS-232-C
RS-423-A
RS-422-A
RS-485
ITU
V.28
V.10/X.26
V.11/X.27
Data Rate
20kbps
300kbps
10Mbps
10Mbps
Maximum Distance
15m
1200m
1200m
1200m
Number of Drivers
32
Number of Receivers
10
10
32
Driver Voltages
15 V
6 V
5 V
5 V
Number of conductors
per signal (plus one
ground if needed)
Notes:
EIA Electronic Industry Association
ITU International Telecommunications Union
XIV - 19.1
698
Serial Peripheral Interface

Serial Peripheral Interface (SPI) is a synchronous serial communication standard from
Motorola
provides economical board-level communication between Microcontrollers and devices
synchronous communication using a shared clock, rather than encoding the clock as part
of the data (which we will see later)
Serial Peripheral Interface (SPI)
XIV - 20
699
SPI Concepts
data is loaded asynchronously at master and slave and then serially shifted synchronously
SS
SPDR Write
enable
SS
MISO
data
MISO
MOSI
data
MOSI
SPDR Read
master
SPDR Write
SPDR Read
SCK
clock
SCK
slave
SS slave select, signifies channel between master and slave is active

SCK symmetric clock, used for bit and byte synchronization, polarity and phase are programmable
MOSI master-out-slave-in, output line from master to the slave device
MISO master-in-slave-out, input line to master from the slave device
SPDR serial peripheral data register, buffered on read, on write data is written directly into
the serial shifter (Motorola standard) or into a buffer (Nios implementation)
XIV - 21
700
Serial Shifting
n bit data registers (SPDR) are linked to form a distributed 2n bit register
when data transfer is performed, the 2n bit register is serially shifted by n bits
data may be shifted MSB or LSB first (MSB-first as shown in the figure)
Motorola standard defines n = 8, Nios processor SPI allows 1 16 bits
Before
MOSI
1 1 0 1 0 1 0 0
MISO
MISO
0 0 1 1 0 1 1 0
SPDR
SPDR
master
slave
MOSI
After
MOSI
0 0 1 1 0 1 1 0
MISO
MISO
1 1 0 1 0 1 0 0
SPDR
SPDR
master
slave
MOSI
XIV - 22
701
Data Transfer Using SPI

transfers are controlled by the master
slave cannot interrupt the master, although master can interrupt itself when data transfer
is complete
both master and slave must have compatible settings for
clock polarity (idle state can be high or low)
sampling edge (clock phase)
MSB or LSB transferred first
transmitter uses one edge of the clock to change output bit, receiver uses other edge to
sample input bit
XIV - 23
702
SPI (Master) Operation

After configuration, to send and/or receive data, the master:
1. selects the slave
2. writes a byte to the data register SPDR
3. waits for its serial peripheral data transfer flag to be set (using interrupts or polling)
4. reads byte from data register SPDR (if required)
5. repeats steps 2-4 until block complete
6. deselects the slave
XIV - 24
703
SPI (Slave) Operation

To send and/or receive data the slave:
1. writes a byte to the data register SPDR (if required)
2. waits for its serial peripheral data transfer flag to be set (using interrupts or polling)
3. reads a byte from data register SPDR (if required)
4. repeats steps 1-3 until block complete
XIV - 25
704
SPI Operation
SCK
SS
MOSI
MSB
LSB
MSB
MISO
MSB
LSB
MSB
Clock Idles High

Transmit Bit on Falling Edge
Sample Bit on Rising Edge
(One possible timing configuration)
spixfer.
XIV - 26
705
Aside: SPI in Lab 3
SS
MISO
SS n
Decoder
MOSI
SCK
slave 1
MISO
MOSI
master
SCK
slave 2
SCK
MOSI
MISO
SS
XIV - 27
706
Avalon Bus
Question: When is a bus not really a bus? or Can you build a bus with neither tri-state nor
passive pull-up drivers?
The
The
resources that cover this material can be found in the Altera distribution material.
following manuals are available:
Avalon Interface Specifications
QSys Interconnect
An example of a non-traditional bus:

tri-state and passive pull-up are geared to an expandable system with decentralized
control structures and a (relatively) unrestricted implementation size.
use of a Megawizard generated design: leads to a completely closed design - after
the design is complete (and generated) no devices will be added without re-running
the design tool
It uses unidirectional signals and multiplexers rather than shared signals
Excalibur Avalon Bus
XIV - 28
707
Avalon Bus - Structure

AvalonStructure.
Multiplexer
Master
M1
Request
Logic
Multiplexer
Request
Logic
Master
M2
Master Ports
Multiplexer
Arbiter
Logic
Arbitration
to select
Mux control
Multiplexer
Arbiter
Logic
Slave Ports
Slave S1
Slave S2
Slave S3
XIV - 29
708
Avalon Bus Arbitration

Arbitration occurs, at the slave rather than at the shared signal point in the circuit
Every master port must be able to delay its transaction until it wins the arbitration step.
The arbitration seeks to be fair and selects the next user based on a round-robin or
weighted round-robin structure. The weighted round-robin structure permits a weight to
be allocated to each master-slave pair. These weights can be used to let (for example)
the processor to have 66% of the accesses to memory and a DMA controller to have 33%
of the accesses.
XIV - 30
709
VME Bus
The VME bus (IEEE-1014) is intended as a backplane bus
V&Z is quite clear on the various details, this year we will examine only two of its characteristics
bus termination
multiple interrupt sources and sinks
VME Bus
XIV - 31
710
Bus Termination
Since this is a backplane bus it may be longer, and driven by a wider variety of devices.
Each line is terminated as shown below (there is one termination on each end of the wire).
+5 V
+5 V
330 W
330 W
Bus Line
470 W
470 W
vme1.
When no-one is driving the bus, it rests at 2.94 V (I.e.
470
800
5 V) with a termination
impedance of 194 at each end. (I.e. 330 in parallel with 470 )
VME Bus
XIV - 32
711
Bus Termination
4.5 V
To get a zero on the bus (I.e. a voltage no larger than 0.5 V) there must be 165
= 27.2 mA
flowing through the two 330 resistors.

0.5 V
= 2.1 mA)
This would be composed of: some through the two 470 resistors ( 235
and the rest (25.1 mA) flowing into the driving gate ignoring any current into
the load!!!
VME Bus
XIV - 33
712
Multiple Interrupt Sources

Until now we have ignored the interrupt needs on a bus.
From ECE 222 you recall that interrupts are often structured as a daisy chain.
Interface
Computer
Interface
Memory
Computer
Computer
Computer
Memory
Interface
Memory
Computer
Computer
Interface
Interface
Computer
However when there is the possibility of having several possible recipients of a given
interrupt how can it be structured? (For example, two processors and 1 serial port, some
times the port may wish to interrupt processor 1 and at other times processor 2.)
vme2.
VME Bus
XIV - 34
713
Multiple Interrupt Sources

Signals on the VME bus to support multiple interrupt handlers.
there are 8 interrupt request lines (passive pull-up)
there is only one interrupt acknowledge signal (IACK)
there is a daisy chained signal (IACKIN and IACKOUT) attached to every device on
the bus. (Note that IACKIN0 = IACK the bus line)
each interface is capable of driving one or more IRQ lines
one interrupt handler is associated with each IRQ line (a given handler may serve
several lines)
vme982.
VME Bus
vme981.
XIV - 35
714
Multiple Interrupt Sources Basic Operation Sequence

Assume that the various possible handlers (processors) have divided the interrupt request
lines.
Interface asserts one of the IRQ lines
The handler associated with that line requests to become bus master.
Once it is bus master it asserts IACK, and at the same time indicates (by the low address
lines) which interrupt line is being acknowledged.
All interfaces, except those currently requesting an interrupt of the same level as specified
on the address lines, pass the IACKIN signal to the IACKOUT signal.
The first device in the daisy chain that is making a request at the level specified on the
address bus, places its ID on the data lines, and provides the slave signal necessary to
inform the bus master that the data can be read.
The bus master will use the ID to start to process the interrupt.
VME Bus
XIV - 36
715
SCSI (Small Computer System Interface) Bus

Characteristics:
SCSI X3.131 standard
Now SCSI-1. SCSI-2, and SCSI-3 etc. for an entire family, listed on the next note
page.
4 MBps
6m max. length (single ended)
25m (differential transmission)
Connection via a standard 50-pin connector
Three Controller Types:
Initiators
T argets
Combined (the operation (Initiator or T arget) can be selected in some programmable
manner).
XIV - 37
716
Note: SCSI Family Tree

Standard
Name
Peak
transfer
rate
(MBps)
Bus
Width
(bits)
Cable
Type
Maximum
Distance
(m)
Maximum
Devices
SCSI-1
SE
HVD
25
SCSI-2 (Fast SCSI)
10
SE
HVD
25
SCSI-2 (Fast-Wide SCSI)
20
16
SE
HVD
25
16
SCSI-3 (Ultra SCSI)
20
SE
HVD
1.5
25
SCSI-3 (Ultra Wide SCSI)
40
16
SE
HVD
25
Ultra 2 SCSI
40
LVD
HVD
12
25
Ultra 2 Wide SCSI
80
16
LVD
HVD
12
25
16
Ultra 3 SCSI
160
16
LVD
12
16
Ultra 320 SCSI
320
16
LVD
12
16
Ultra 640 SCSI
640
16
LVD
12
16
16
Derived from SCSI Trade Organization website: http://www.scsita.org/
XIV - 37.1
717
scsi1.
Micro
Processor
Initiator
SCSI
Controller
Target
Tape
Drive
Micro
Processor
Tape
Controller
SCSI
Controller
Initiator or
Target
Input link
output link
termination
resistors
Target
Disk
Controller
Disk
Drive
Target
Printer
Controller
Printer
Note: SCSI is called a bus,

and the signals are all bused
signals (the signals are all connected directly).
However, most devices that
interface to SCSI are connected in a daisy chain (as
shown to the left).
In this case there is nothing
connected in series between
the in and the out links. The
daisy chain approach simplifies:
cabling of external devices
attachment
of
the
matching resistors at the
last device.
XIV - 38
718

Communication occurs between an Initiator and a T arget in two (or more) steps.
The Initiator and T arget agree to communicate by setting up a logical connection
between them.
Then they exchange control information
Then data is transferred (if required)
Initiator:
Requests/gets control of the bus (referred to as Selection)
Establishes logical connection with the T arget.
Exchanges messages to specify the request (Under the control of the T arget)
(Optionally) suspends its use of the bus while the T arget responds to the request.
XIV - 39
719
T arget
Requests
the
bus (if suspended) (Referred to as
Re-selection)
Reactivates the
connection
Sends control
or data information to the
Initiator.
(Optionally)
suspends
the
use of the bus.
Signal
DATA
Phase
Information
Type
Direction
Handshake
(Async)
Other
SCSI-1 Bus Signals

Function
(8 Data +1 parity)
BSY (Busy) and
SEL (for selection and re-selection)
Control/Data (C/D) Asserted during control
info transfer.
MSG (Message) indicates that the information
is a message i.e. not data
I/O (relative to the Initiator)
REQ Asserted by the T arget to request a
data transfer cycle.
ACK Acknowledge: asserted by the Initiator
when it has completed a data transfer operation
ATN Attention asserted by the Initiator when
it wishes to send a message to the T arget
RST Reset
XIV - 40
720
Note: SCSI Signalling Stages

A SCSI transfer/communication cycle can take on the following sequence of events.
Event Name
Activity
Arbitration
Initiator arbitrates for ownership of the bus.
Selection
Initiator selects a T arget by transmitting Initiator and T arget IDs.
Message
T arget requests an Identif y message containing the logical unit number to be used and the
communication capabilities required. T arget rejects transfer if capabilities are not supported.
Command
T arget requests a command.
Data
T arget executes command and data is transferred.
Status
T arget reports status back to the Initiator.
Message
T arget informs Initiator that command execution is complete.
XIV - 40.1
721

Transfer Options:
Transfers (as controlled by C/D and MSG) may consist of:
data (C/D=0, MSG=0) or
control
command (C/D=1, MSG=0) (for example request for command)
status
messages (C/D = 1, MSG = 1) (for example transfer complete)
Timing is controlled by the T arget (I.e. the T arget asserts REQ and awaits ACK)
Synchronization
Note three levels of synchronization:
Arbitration (BSY, SEL signals)
Transfer timing (REQ, ACK)
Operation Control (C/D, MSG)
XIV - 41
722

Bus Cycle Sequence
1/1
Bus Idle
x/y = BSY/SEL Value
Any Request for

SCSI Bus
Arbitration
Selection
Information
Transfer
0/1
0/1
0/0
1/0
Select 1 device and it
then selects another
scsi2.
Note that the BSY/SEL values are reused during the sequence
Also note that it is the BSY/SEL signals that control when the next phase is entered
XIV - 42
723

Device Identification
Devices numbered 0 ... 7
Device 0 is assigned to Data bit 0 (for identification purposes) Often referred to as 1-hot
encoding
When a device must identify itself it asserts its associated data line (during arbitration)
When a device wishes to select another device, it asserts that devices line as well its own
(during selection)
note that when device i wishes to establish a link with device j, it asserts both data
lines i and j during the selection phase.
XIV - 43
724

Arbitration
Entered when the bus is idle (BSY=SEL=0)
Note BSY etc. are shown in the timing diagrams
Each device wishing service asserts its line on the data portion of the bus.
And also pulls BSY low.
If a higher priority device (using a higher numbered data line) is also requesting, then the
(lower numbered) device removes its signal.
XIV - 44
725
SCSI - Arbitration Timing Diagram

See Fig 11.45 in V&Z)
Target Examines ID
2
-DB2
<800
-DB5
>1200
6
-DB6
-BSY
>800
2,6
>2200
6 only
>80
>400
<200
6 (6 wins)
-SEL
Bus
Idle
Selection
Arbitration
Time Shown in ns
Numbers show the addresses
driving a line.
6 and 2 both want the bus and

6 want 5 to be the target.
scsi3.
XIV - 45
726
SCSI - Arbitration Timing Diagram Comments

Notes:
All requesting devices (requester ) drive the busy line (low in the figure) for some minimum
time (2200ns)
Then the winner (requester ) asserts SEL and the losers remove their request.
Also during this time the winner (requester ) asserts the requested s line.
The (requester ) then de-asserts BSY, and a period of time later the requested interface
detects that it has been selected.
XIV - 46
727
SCSI - Selection Phase (See previous Figure)

See previous timing diagram (starting on page 725) .
If the requester is also an Initiator, attempting to establish a connection, then this is a
selection.
If the requester is a T arget trying to re-connect to a previous Initiator, then this is a
re-selection.
Continuing with reference to the previous figure (Selection)
Initiator (requester ) de-asserts BSY, and a period of time later the requested
(T arget) detects that it has been selected.
T arget takes control of the bus by asserting BSY.
Once the Initiator detects that the T arget has asserted BSY, it releases SEL.
Data transfer starts (I.e. the T arget requests a command from the Initiator using
REQ/ACK to sequence transfers.).
XIV - 47
728
SCSI - Data Transfer

(Recall: data transfer is controlled by the T arget)
Assumption: BSY is always asserted and the T arget keeps the bus
Request a command I/O = 0, C/D = 1, MSG = 0 (a command to request a command)
Assuming that the command can be acted on immediately each byte is transferred
I/O = 1 (data to the Initiator), C/D = 0, MSG = 0
After the last data command complete I/O=1, C/D = 1, MSG = 1
Note: I/O is relative to the Initiator and for C/D, C/D=1 indicates a command
XIV - 48
729
SCSI - Reselection
Reselection: After some or none of the data that has been requested by the Initiator has been
transferred, the T arget releases the bus to await data to become available. Once the data is
available the T arget arbitrates for the bus and becomes a bus master (as the T arget). The
process is reselection.
-DB5
T 5
-DB6
-BSY
T5
I 6
T 5
I and T
5, 6
T5
T5
-SEL
Arbitration
Initiator Examines
ID
5 wants to re-establish connection with 6
scsi4.
XIV - 49
730
SCSI - Reselection
1. Start with bus idle (BSY and SEL idle)
2. The T arget that wishes to re-establish the connection (and others) go through arbitration
until one is selected (assume that it is the T arget in question)
3. The T arget asserts the Initiators address (which it has saved during the initial arbitration cycle)
4. Sometime later the T arget releases the BSY line
5. When the Initiator detects its address and observes the de-assertion of BSY, it asserts
BSY
note this is similar to previous case, except the Initiator is asserting BSY not the
T arget as required for data transfer
6. When the T arget detects that the Initiator has asserted BSY, it too asserts BSY, and
then releases SEL
7. Once SEL is released, the Initiator releases BSY and we are back to the same state as
at the end of selection
XIV - 50
731
SCSI - Reselection
Comments
The T arget is responsible for the transfers
The T arget is a complex interface
commands such as seek etc. can be included in complex commands such as READ
sector xxxx (No seek, Interrupt, read DMA)
XIV - 51
732
IEEE-488
IEEE-488 a standardized version of HPIB (Hewlett-Packard Instrumentation Bus). The
IEEE-488 bus is also referred to as the GPIB (or General Purpose Instrumentation Bus).
Intended for connecting instruments (smart instruments by 1980 standards)
Also useful for some peripherals, but not for disks
4MBytes/sec to 8MBytes/sec.
Bus oriented (not like serial point to point)
Byte-wide transfers
16 signals plus 8 grounds (24 pins)
IEEE-488
XIV - 52
733
IEEE-488 Signal Functions
IEEE-488 Bus Signals

Signal
DATA
ATTENTION
Ready for data
(RFD) and Data
Accept (DAC)
Data
Available
(DAV)
Service Request
Interface Clear
Remote Enable
End or Identify
Function
(8-bit Data)
Stop transfer and listen for commands
These signals JOINTLY perform the function of the Slave signal
in a master slave transfer oriented bus)
(similar to a master signal it indicates that there is data to be
read on the bus
Indicate to the controller that service is being requested
Force bus devices into a known state.
Disconnect device from panel and place under the control of the
instrument bus
Used for parallel polling
IEEE-488
XIV - 53
734
IEEE-488 Data Transfer

Between talker and listener (more later).
Unlike all other buses studied, this one permits/encourages broadcast messages.
Fully interlocked transfers.
Two wires required for SLAVE action.
ReadyForData (RFD) is an passive pull-up (open-collector) signal that is pulled down
by ANY current listener when it cannot accept data.
DataAccepted(DAC) is an passive pull-up (open collector) signal pulled down by ANY
current listener until the data has been accepted.
IEEE-488
XIV - 54
735
IEEE-488 Single Listener Transfer

(Note no address)
ieee4881.
Data (T)
DAV(T)
RFD(L)
DAC(L)
IEEE-488
XIV - 55
736
IEEE-488 Multiple Listener Transfer

ieee4882.
Data(T)
DAV(T)
RFD(All L)
All Ready
DAC(All L)
Some have not accepted
Some not ready
All have
accepted
IEEE-488
XIV - 56
737
IEEE-488 Structure
Controller
1
ieee4883.
There is one controller responsible for selecting

one Talker and
one or more Listeners
Once selected the talker sends data to the listener(s) until it is either interrupted by the
controller, or until the transfer is complete.
A new conversation is started by the controller as a result of an interrupt by a device, or
as the result of some internal action.
IEEE-488
XIV - 57
738
IEEE-488 Controller-Initiated Transfer

BUS ACTIONS
ATTENTION <SIGNAL>
TALK ADDRESS 3 <COMMAND>
LISTEN ADDRESS 6 <COMMAND>
<<other listen addresses>>
ATTENTION OFF <SIGNAL>
Commands are 8-bit values
5-bit addresses (i.e. 32 devices however 1 address is reserved as the no address
address) and
3-bit commands
IEEE-488
XIV - 58
739
IEEE-488 Talker/Listener Setup

The talker (or listener) may need to be set up. There are various alternatives.
the user runs around and sets up the various devices
controller becomes the talker and sets the device to be a listener and then sends
commands. (This only works if the device will accept commands via the IEEE-488
port.)
use secondary addresses for specific commands. (It is possible to use 5-bits to pick
a device, and then a further 5-bits as a sub-address.)
IEEE-488
XIV - 59
740
IEEE-488 Bus Requests

A device may wish to be able to request service (and perhaps interrupt some current
activity)
The SERVICE REQUEST signal is used for this purpose. When the controller detects
SERVICE REQUEST being asserted:
stops all action <ATTENTION>
issues an UNLISTEN command (to no address)
this causes the current talker to stop its transfer
sends a SERIAL-POLL ENABLE command so that when asked each device will provide a status byte
controller determines the address of the device making the request (See polling section)
controller can then determine which transfer should be enabled next
sends a SERIAL-POLL DISABLE
ATTENTION is set and reset between each device poll. (as the talker must be
reassigned each time.)
IEEE-488
XIV - 60
741
IEEE-488
Polling
Serial poll: Select each device in turn as a talker and the controller as the listener, release
ATTENTION and wait for a status byte from the talker. (Up to 31 devices to poll.)
Fast Poll: Each device is assigned one data line (at setup).
each requesting device asserts its line.
if the set up has more than one device assigned to a given line, then serial polling
can be used to differentiate between these devices (the maximum number of serial
polls is 4).
IEEE-488
XIV - 61
742
PCI
pci1a.
Processor
and
Cache(s)
Memory
Bus
System Bus
AGP
Bus
PCI developed, by
Intel, to replace local
bus architectures for
personal computers.
PCI extends the PC
hierarchy.
Additional reference:
T. Shanley and
D. Anderson PCI
System
Architecture, 4th Edition,
Mindshare, 1999.
Accelerated
Graphics
Port
North
Bridge
Video
Card
Memory
PCI Bus
USB
PCI
1
PCI
2
PCI
n
South
Bridge
ATA Bus
n<8
SCSI Bus
ISA or
EIA BUS
ISA
1
ISA
2
Peripheral Component Interconnect (PCI)
ISA
i
XIV - 62
743
PCI Introduction
A PCI bus interconnects relatively complex systems, in a relatively confined area.
Overview
Synchronous
Support for burst traffic. (split cycle-like, with one address phase and (potentially)
several data phases.
Expectation of many possible masters competing.
XIV - 63
744
Data Transfer (Burst)

Consider the timing diagram for a read transaction is shown below.
PCI CLK
FRAME#
C/BE#
6
H
G
Data 1
Addr
Da 2
Data 3
C
CMD Byte Enable Byte Enable Byte Enable
I
IRDY#
TRDY#
DEVSEL#
GNT#
7
J
AD
4
H
D
F
L
K
K
Bus Turnaround Cycle
pcitime.
XIV - 64
745
Data Transfer (Burst) - Bus Times

Time A: Initiator (Bus Master) starts transaction by asserting FRAME# (# indicates
active-low in PCI documentation). The address sent here is to be used as the starting
address if the operation is multiple words/bytes.
Time B: All targets latch and decode the address (and command C/BE)
Time C: Initiator stops the command and starts driving the byte enables Byte enables
specify which bytes on the bus are active during a given transfer.
Time D: if target keeps TRDY de-asserted indicating that the target (bus slave) is not
ready, then the master will have to wait (or give up the bus).
Time E: The driver for the lines changes (in this case the Initiator quits driving the AD
lines and the T arget starts to drive them).
Time F: The DEVSEL# signal is used for the T arget to indicate that it is responding
(Slave-like). If there is no DEVSEL# within 6 clock periods the Initiator aborts the
transfer.
XIV - 65
746
Data Transfer (Burst) - Bus Times

Time G: The T arget begins to provide data.
Time H: Data is read by the Initiator at these points.
Time I: Wait states caused by either the Initiator or the T arget not being ready.
Time J: Frame is de-asserted to indicate that the transfer is ready to complete the last
data phase.
Time K: The T arget terminates by de-asserting TRDY# and DEVSEL#.
Time L: Initiator gives up the bus.
XIV - 66
747
PCI Arbitration
Since PCI is very constrained, it can use a complex central arbiter and a star connection.
Daisy Chain
Bus Oriented
Star (PCI)
pciintr1.
XIV - 67
748
PCI Arbitration (continued)
pciarb2.
In the case shown,

the lower priority
unit (A) gets the
bus and starts to
use it, and then
the higher priority
unit (B) requests,
gets the bus and
when finished it is
returned to A.
XIV - 68
749
PCI Arbitration (continued)

Time A: Device interface A requesting bus.
Time B: Arbiter grants bus to A
Time C: Device interface B requests bus on rising edge of clock cycle #2, arbiter detects
device interface B also wants bus.
Time D: A starts a transaction (asserts FRAME#).
Time E: Despite grant to A, arbiter removes grant to A and gives it to B. (Preemption
between cycles.)
Time F: B has the grant, and turns off request once the address phase has started. In this
case there is only 1 transfer from device interface B.
Time G: FRAME asserted by B.
Time H: Arbiter removes grant from B and returns bus to A.
Time I: A resumes mastership of the bus.
XIV - 69
750
Questions of Interest: Questions?
Verify your understanding of the terms listed on the next page.
Assume that you have been asked to interface an opto-isolator to a 20 mA current source. The course has a power supply of
15 V and a source resistance (RS ) of 50. Assume that the opto-isolator that you are to you requires between 6 and 15 ma
to produce a reliable output (i.e., to turn the photo transistor on in saturation). Select components and draw the circuit
required for your receiver.
Consider the use of a standard RS-232 driver and 20 mA current loop to drive a transmission line with a characteristic
impedance of 93. How would you implement termination in each case (justify choice). In each case estimate (for your
assumptions) the power consumed by the termination resistor(s).
What is the peak data throughput for a 32-bit, 33 MHz PCI bus?
What is the peak data throughput for a 64-bit, 66 MHz PCI bus?
Why are bus turnaround cycles necessary?
XIV - 69.1
751
Note: Terms used in Examples

Terms:
Reselection (page 729)
XIV - 69.1
Section XV:
List of Contents
f2014-1.0
List of Contents
753
Note: Topics in this part of the notes

Course Introduction (page 5)
Section Contents: Course Introduction (page 6)
ECE224/MTE325 Course Goals (page 7)
Overview (page 12)
Embedded Systems (page 20)
Section Contents: Embedded Systems (page 21)
Introduction (page 22)
Terminology (page 26)
Interfacing Software, Introduction to Synchronization, and Device Drivers (page 33)
Section Contents: Interfacing Software and an Introduction to Synchronization (page 34)
A comparison of the abstraction layers for software development. (page 35)
Software Synchronization (page 36)
Device Drivers (page 48)
Synchronization, Data Generation and Data Transfer (page 50)
Section Contents: Synchronization and Data Transfer (page 51)
Synchronous vs Asynchronous Systems (page 67)
Generalized I/O Operations (page 70)
Section Titles
XV - 0.2
List of Contents
754
Note: Topics in this part of the notes (cont.)

Computer Structure (page 80)
Section Contents: Computer Structure (page 81)
Background (page 82)
CPU-Memory Interface (CPU Version) (page 91)
CPU-Memory Interface (Memory Version) (page 95)
Multiple Drivers (page 101)
Device Selection (page 121)
Overview of Device Selection with Synchronous Bus (page 124)
Reality Check (page 130)
Synchronous Bus Introduction (page 131)
Bus Terminology (page 136)
Synchronous Bus Transfer (page 141)
Questions (page 148)
Parallel Interfacing (page 150)
Section Contents: Parallel Interfacing (page 151)
Function of Parallel Interfaces (page 152)
System Bus Side (page 158)
Device-Side Alternatives (page 160)
Data Characteristics (page 171)
Event Characteristics (page 179)
Questions - Short Answer (page 191)
Section Titles
XV - 0.3
List of Contents
755

Error Detection and Correction (page 196)
Section Contents: Error Detection and Correction (page 197)
Resources (page 198)
Error Handling Introduction (page 199)
Parity (page 206)
EC, ED and Distance (page 208)
Hamming Code (page 210)
Hamming Code Implementation (page 220)
Serial Interfacing (page 229)
Section Contents: Serial Interfacing (page 230)
Serial Interfacing Introduction (page 231)
Terminology (page 234)
Character-Oriented Serial Interfaces (page 242)
Protocols and Standards (page 252)
Asynchronous Protocols (page 255)
Synchronous Protocols (page 270)
Synchronous Serial Communication (page 273)
Universal Serial Bus (USB) (page 295)
Using RS 232 Communications Standard (page 309)
Section Titles
XV - 0.4
List of Contents
756

Analog Interfaces (page 321)
Section Contents: Analog Interfacing (page 322)
Op-Amp Review (page 325)
Analog Signal Conversion Issues (page 338)
Digital-to-Analog Converters (page 342)
Analog-to-Digital Converters (page 374)
A/D Converter Specifications and Errors (page 412)
Time Varying Signals (page 413)
Sample and Hold Circuits (page 421)
Buses - Data Transfer (page 433)
Section Contents: Buses - Data Transfer (page 434)
Synchronous Bus Transfer (page 440)
Asynchronous Bus Transfer (page 453)
Partially Interlocked Asynchronous Buses (page 464)
Semi-Synchronous Bus Transfer (page 467)
Split Cycle Protocols (page 471)
Section Titles
XV - 0.5
List of Contents
757

Buses - Arbitration (page 476)
Section Contents: Buses - Arbitration (page 477)
2-Wire Daisy Chain (page 484)
Summary of the Operational Characteristics of Daisy-Chained Bus Arbitration (page 529)
Non-Daisy-Chained Bus Arbitration (page 541)
Direct Memory Access(DMA) (page 545)
Section Contents: Buses - DMA (page 546)
Block Oriented Program Controlled I/O (page 548)
DMA Example (page 558)
Complete DMA Cycle (page 567)
DMA Controller Architecture (page 572)
A Intimacy Between DMAC and Interface - Detached vs Integrated (page 574)
B Addressing Structure Implicit Addresses vs Dual Addresses (page 575)
C Bus Structure (page 584)
Specialized Topics (page 587)
Performance Summary (page 591)
Section Titles
XV - 0.6
List of Contents
758

Grounding, Shielding and Transmission Line Issues (page 601)
Section Contents: Grounding Shielding and Transmissions Lines (page 602)
Introduction and Resources (page 603)
Grounding (page 605)
Shielding (page 613)
Transmission Lines (page 627)
Reflections in a Linear System (page 650)
Reflections in a Non-Linear System (page 662)
Examples (Signalling and Buses) (page 674)
Section Contents: Examples (page 675)
20 mA Current Loop (page 681)
RS-232 Electrical Signalling Properties (page 685)
RS-422 and RS-423 Electrical Signalling Properties (page 689)
RS-485 Bidirectional Drivers (page 692)
Serial Peripheral Interface (SPI) (page 698)
Excalibur Avalon Bus (page 706)
VME Bus (page 709)
SCSI (Small Computer System Interface) Bus (page 715)
IEEE-488 (page 732)
Peripheral Component Interconnect (PCI) (page 742)
Section Titles
XV - 0.7
List of Contents
759

List of Contents (page 752)
Section Titles (page 753)
Section Titles
XV - 0.8
Section XVI:
Summary of Contents
f2014-1.0
Summary of Contents
761
Note: Summary for Review

Course Introduction (starting on page 5) including people, marking scheme, course outline, and an introduction to interfacing ideas.
ECE224/MTE325 Course Goals (starting on page 7)
Overview (starting on page 12)

Brief overview of the course theme.
Embedded Systems (starting on page 20) The ideas associated with embedded systems, although not fundamental to the course
content, are always present in the system examples. As a result a small amount of time is spent introducing some of the general
terms associated with embedded systems.
Introduction (starting on page 22)
Importance and characteristics of general embedded systems. Introduces the ideas and significance of embedded
systems.
Terminology (starting on page 26)
Compares and contrasts terms such as: microprocessor, microcontroller, System on a Chip, Programmable System
on a chip, Programmable logic devices.
Interfacing Software, Introduction to Synchronization, and Device Drivers (starting on page 33) (the actual order of the content is
different from this list). This section of the notes provides some new and some review material to provide a common framework to
discuss the material later in the course.
Section Titles and Summary
XVI - 0.9
Summary of Contents
762
A comparison of the abstraction layers for software development. (starting on page 35)
Software Synchronization (starting on page 36)

An examination of synchronization from the software perspective. Examines types of synchronization, the coding
for some examples, latency is introduced, interrupt processing software and sequencing is described.
Device Drivers (starting on page 48)
Definition of device drivers and their needs.
Synchronization, Data Generation and Data Transfer (starting on page 50) Synchronization is a key component of most, if not all,
sections of this course. This section, in combination with the next one, introduces synchronization requirements in a fairly general
model.
Communicating finite state machines are introduced as a common thread for various parts of the course. Peer-to-peer
synchronization, types of synchronization and the elements (events and data) of data transfer are also introduced.
Persistent and transient events and data are compared.
Synchronous vs Asynchronous Systems (starting on page 67)
Communication examples for synchronous and asynchronous systems are described.
Generalized I/O Operations (starting on page 70)
A view of IO in general terms. The software techniques described earlier are considered. Three types of data sources
XVI - 0.9
Summary of Contents
763
(spontaneous, consumer responsive and consumer sensitive) are described. These models permit a more complete
discussion of latency.
Computer Structure (starting on page 80) Processor Structure. A summary of how the processor executes an instruction and how
external interfaces can detect requests by the processor.
CPU-Memory Interface (CPU Version) (starting on page 91)
The single bus CPU model is used to motivate the needs for the system bus from the CPUs perspective.
CPU-Memory Interface (Memory Version) (starting on page 95)
The needs for communication from the memorys perspective are described. This includes the potential for synchronous and asynchronous communication alternatives.
Multiple Drivers (starting on page 101)
How to attach more than one device that can drive a value onto a line. This discussion centers around the electrical
alternatives for these connections. Tri-state, passive pull-up and passive pull-down alternatives are described and
compared.
Device Selection (starting on page 121)
Explicit and passive selection techniques are examined.
Overview of Device Selection with Synchronous Bus (starting on page 124)
Requirements for attaching to a basic synchronous bus described. Both read and write operations are shown.
Reality Check (starting on page 130)
XVI - 0.9
Summary of Contents
764
Although most previous courses have assumed that the timing of signals was appropriate. Metastability may occur
if the setup or hold time is violated.
Synchronous Bus Introduction (starting on page 131)
Definitions of the terms and times used in this section of the notes including skew time, propagation delay, select
time and access time. There is also a discussion of the features common to all bus structures. This material is
covered in more detail later in the course.
Synchronous Bus Transfer (starting on page 141)
The synchronous bus is used as the basis for the discussion of bus data transfer structures. The timing and
interconnections required to support a basic synchronous bus are described here with the more complex discussions
left for detailed coverage later in the term.
Questions (starting on page 148)
Parallel Interfacing (starting on page 150) Examines the role of the interface to match the bus timing and signalling characteristics
with a devices timing and signalling characteristics.
Function of Parallel Interfaces (starting on page 152)
The main function of the parallel interface is to provide a method to permit the processor, or other bus master,
to read (or write) data from(to) the interface in the time scale of the bus. The interface may also provide signal
conditioning and other features described in later in this section of the notes.
System Bus Side (starting on page 158)
Introduces basic synchronous bus communication structure to motivate how to attach a parallel interface to a
processor.
XVI - 0.9
Summary of Contents
765
Device-Side Alternatives (starting on page 160)

Considers both unidirectional and bidirectional port alternatives however, focuses on bidirectional issues including: control (implicit and explicit direction control), drivers (tri-state, passive pull-up (open collector), and pseudo
bidirectional), and the differences between static and dynamic applications of bidirectional ports.
Data Characteristics (starting on page 171)
Characteristics of parallel data examined include: in-band and out-of-band signalling, transient and persistent data,
signalling alternatives to indicate that data is present, and de-bouncing data. Several examples of parallel ports to
support these characteristics are provided.
Event Characteristics (starting on page 179)
Characteristics of events in parallel data examined include: transient vs persistent events, how events can be stored
and cleared
Questions - Short Answer (starting on page 191)
Error Detection and Correction (starting on page 196) Error Detection and Correction including an introduction to error types,
differences in detection and correction and one example of an error correcting code (the Hamming code). The error environment, the
general methods for dealing with some errors (detection and/or correction), the limitations to error handling, and an introduction to
data words and code words.
Error Handling Introduction (starting on page 199)
The error environment, the general methods for dealing with some errors (detection and/or correction), the limitations
to error handling new, and an introduction to data words and code words.
Parity (starting on page 206)
XVI - 0.9
Summary of Contents
766
The most basic (and common) of the error detection techniques parity sends one additional bit per data word to
permit single bit errors to be detected.
EC, ED and Distance (starting on page 208)
The relationship between error detection (ED) and error correction (EC) is examined. The distance between words
is defined and used as a measure to compare error correction and detection needs.
Hamming Code (starting on page 210)
One of the standard single bit error correction techniques, Hamming code, is introduced through a small example.
The constraints and costs associated with Hamming code is examined and the effects on efficiency when longer code
words are used is also considered.
Hamming Code Implementation (starting on page 220)
The issues associated with implementation for larger words is also examined.
Serial Interfacing (starting on page 229) Introduction to serial communication interfacing; asynchronous communication techniques,
synchronous techniques; and serial device interfacing techniques.
Serial Interfacing Introduction (starting on page 231)
The issues associated with serial interfacing such as the types of synchronization, are introduced.
Terminology (starting on page 234)
Link types (simplex, half-duplex and full duplex), types of synchronization (bit, byte and clock) are described, bit-rate
and baud-rate, and types of coding schemes.
XVI - 0.9
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767
Character-Oriented Serial Interfaces (starting on page 242)

Examines the structure of character-oriented serial interfaces. The material focuses on: the transmit and receive
register structure, the interface with the system bus, The issues associated with clocking (for example when to clock
the data into the shift register), and the register structure in the interface.
Protocols and Standards (starting on page 252)
The scope of a protocol and a communication standard are examined. There is also a brief summary of the types of
standards.
Asynchronous Protocols (starting on page 255)
Asynchronous character-oriented serial communication is described in detail. Topic emphasized: clocking issues,
phase detection, clocking errors, other errors (framing, parity, overrun) and special characters such as a break
Synchronous Protocols (starting on page 270)
Introduces synchronous, block-oriented, protocol structures.
Synchronous Serial Communication (starting on page 273)
Describes synchronous, block-oriented, serial port structures. Examines two synchronous communication protocols
(HDLC and BISYNC).
Universal Serial Bus (USB) (starting on page 295)
The USB (Universal Serial Bus) structure is examined. Signalling issues such as bit-stuffing, NRZI signalling, and
packet-oriented transfers are also discussed.
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Using RS 232 Communications Standard (starting on page 309)

The RS-232 standard connections are introduced and the need (and functionality) of a null-modem is examined.
Analog Interfaces (starting on page 321) Digital-to-analog interfacing, Analog-to-digital interfacing, Sample-and-hold circuitry.
Includes a discussion of static and dynamic errors.
Op-Amp Review (starting on page 325)
Review of the aspects of Op-Amp operation required for the analog section of the notes.
Analog Signal Conversion Issues (starting on page 338)
Issues associated with conversion between discrete and continuous systems and representation of analog values in
various binary number representations.
Digital-to-Analog Converters (starting on page 342)
Operation characteristics associated with digital-to-analog converters; binary weighted ladder and R-2R ladder used
as examples; commercial examples; and errors and performance issues are considered.
Analog-to-Digital Converters (starting on page 374)
Operation characteristics associated with analog-to-digital converters; hardware and software (assisted) implementations for binary ramp and successive approximation converters as well as hardware only implementations for flash,
single-slope and dual slope converters used as examples; and commercial examples are considered.
A/D Converter Specifications and Errors (starting on page 412)
Linear and Non-linear errors as well as performance limitations are examined.
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Time Varying Signals (starting on page 413)

The earlier discussions of errors assumed that the signals applied to the analog-to-digital converter were constant
with respect to time. The limitations imposed by time varying signals are examined.
Sample and Hold Circuits (starting on page 421)
Examines the operational characteristics and limitations of sample and hold circuits as an alternative to manage
time-varying signals.
Buses - Data Transfer (starting on page 433) Examination of operation and timing requirements for synchronous, asynchronous,
partially interlocked asynchronous, semi-synchronous, and split cycle bus systems. This section of the notes deals exclusively with
the transfer of data. Issues associated with selecting the next bus master are presented elsewhere in the notes.
Definitions of the terms and times used in this section of the notes including skew time, propagation delay, select
time and access time. There is also a discussion of the features common to all bus structures.
Synchronous Bus Transfer (starting on page 440)
The synchronous bus is used as the basis for the other bus data transfer structures in subsequent subsections. The
single most important assumption/requirement for a synchronous bus design is that during every transfer there are
fixed, known points in time during in the transfer cycle where events occur. The design must be such that at these
event times all interfaces attached to the bus observe the same signal values on all bus lines. All transfers on a
synchronous bus require the same length of time. Ladder and timing diagrams are used to convey the information.
Asynchronous Bus Transfer (starting on page 453)
An asynchronous bus transfer technique uses handshaking to allow synchronization at times compatible with the
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master and the slave. The asynchronous bus is the first situation that considers, in detail, the fact that signals have
different values at different places on the bus at the same instant.
Partially Interlocked Asynchronous Buses (starting on page 464)
The fully-interlocked asynchronous bus of the previous section is extended to reduce the number of bus interactions
required to synchronize a transfer.
Semi-Synchronous Bus Transfer (starting on page 467)
Buses based on a semi-synchronous bus data transfer technique are very common in microprocessor systems. The
semi-synchronous bus provides a technique to permit interaction with slower interfaces. This technique has only
limited impact on the faster transfers.
Split Cycle Protocols (starting on page 471)
The split cycle protocol provides improved performance in environments where there are multiple bus masters. Each
bus master can make a request of the slave, release the bus, and then receive the response from the slave at some
later time. This leaves the bus available for use by other interfaces during the slave access time.
Buses - Arbitration (starting on page 476) Examination of operation and characteristics of daisy chained and non-daisy chained bus
arbitration techniques.
The general needs of arbitration are examined. The terminology for devices and interfaces and arbitration is defined.
2-Wire Daisy Chain (starting on page 484)
The first of the daisy-chained arbitration techniques is examined in more detail than the other techniques. This sub-
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section includes the detailed consideration of distributed digital systems. Of particular note is the limited information
that is available at each part of the distributed arbitration system to make the arbitration decisions. This section
considers a design example translating the needs of the arbitration system to the specification of a fundamental
mode (asynchronous) circuit.
The 3-wire arbiter structure presentation does not provide design details to the same level as the 2-wire material.
The material describes a system that permits global knowledge of the state of the shared resource (the bus), while
permitting a distributed arbitration system design. The coverage includes several detailed timing examples.
The 4-wire distributed arbitration technique is a modification of the 3-wire technique. It permits the bus arbitration
and the bus usage to be overlapped. The presentation emphasizes the differences between the 3-wire and 4-wire
and examines a small number of cases.
Summary of the Operational Characteristics of Daisy-Chained Bus Arbitration (starting on page 529)
The characteristics of the various daisy-chained arbitration techniques are summarized. In addition there is a more
formal examination of the priority provided by the various schemes. One of the key points is that there exists a
window of time in which the arbiter with requests pending from two devices will select the one furthest from the
central arbiter to be the next bus master. The size of this window can be used to compare the techniques.
Non-Daisy-Chained Bus Arbitration (starting on page 541)
The non-daisy-chained arbiter is presented to illustrate that it is not a requirement to have daisy-chained wiring to
make a unique arbitration decision.
Direct Memory Access(DMA) (starting on page 545) Examination of DMA operation (software, hardware and bus needs), DMA
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characteristics.
Block Oriented Program Controlled I/O (starting on page 548)
Block oriented program controlled I/O operation and requirements including sample hardware, C-interface software,
assembly language interface software and special purpose instruction software (and hardware) alternatives.
DMA Example (starting on page 558)
Examines the fundamental needs of DMA without considering all of the background and interacting issues. It
presents a complete DMA example which, as will be seen later, is based on one set of alternatives.
Complete DMA Cycle (starting on page 567)
Considers the DMA cycle from the perspectives of the controller, the interface, and the device. Provides significantly
more structure to the needs of a block oriented transfer using DMA. It also provides ladder diagrams to compare
the timing for program controlled I/O and DMA.
DMA Controller Architecture (starting on page 572)
The next three subsections examine DMA controller related issues that are, to a large extent, independent design
alternatives.
A Intimacy Between DMAC and Interface - Detached vs Integrated (starting on page 574)
Compares DMA controllers that are general in nature, designed for use with different and varied interfaces, with
those that are part of the interface for which they are providing service.
B Addressing Structure Implicit Addresses vs Dual Addresses (starting on page 575)
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Implicit addressing provides a bus cycle that transfers data directly between interface and memory. This subsection
examines the cost in using interfaces that are not designed for DMA in a DMA environment.
C Bus Structure (starting on page 584)
Considers the impact of one and two bus structures on the connectivity of the DMA controller.
Specialized Topics (starting on page 587)
Multiple channel controllers are examined. The specialized needs for transferring data in long blocks are examined.
Performance Summary (starting on page 591)
Comparison of performance of DMA and non-DMA systems. General discussion of the meaning of performance with
respect to I/O systems.
Grounding, Shielding and Transmission Line Issues (starting on page 601) Examination of some of the real-world considerations at
the wiring level for digital circuits.
Introduction and Resources (starting on page 603)
This section of the notes covers a number of realities in digital circuit design. This subsection provides some structure
to the remaining notes in the section.
Grounding (starting on page 605)
Considers issues associated with grounding. Of particular note is the impact of different paths to ground on the
interpretation of the resulting signal levels.
Shielding (starting on page 613)
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Considers the needs to shield some circuits from outside influences. Various shielding requirements are examined.
Techniques to transfer signals from one shielded environment to another are also examined. The techniques considered are optical fibre, balanced, single-ended, opto isolators.
Transmission Lines (starting on page 627)
Transmission lines could be a complete course. The differences between lumped and distributed circuit models are
introduced and situations when transmission line effects are significant to the digital designer are presented. The
characteristic impedance expression (Z0 ) is derived and its meaning examined.
Reflections in a Linear System (starting on page 650)
Reflections in linear systems, source and load matching, and the linear reflection coefficient (Labelled as in some
literature.). Analytical and graphical solution techniques are shown.
Reflections in a Non-Linear System (starting on page 662)
Although analytical solutions to non-linear load and source impedances are beyond the scope of this course, a
graphical technique is described that can be used to estimate the amount of time required for a given transition to
settle to a final value.
Examples (Signalling and Buses) (starting on page 674) Aspects of existing systems that demonstrate some of the course concepts.
The examples can be thought of as in two groups: signalling examples, showing variations and extensions to the
electrical signalling examples used earlier in the notes; and bus examples, illustrating and extending the earlier
material in the course. These examples also show systems that combine various sections of the course into a single
structure.
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20 mA Current Loop (starting on page 681)

The 20 mA current-loop is an example of passing digital information using current rather than an absolute voltage
value or a relative voltage value. This section also shows a sample circuit design that uses an opto-isolator. It is
another example of dealing with grounding realities.
RS-232 Electrical Signalling Properties (starting on page 685)
Describes the RS-232 signalling levels and how cross-talk is handled RS-232.
RS-422 and RS-423 Electrical Signalling Properties (starting on page 689)
RS-422 and RS-423 provide improved signalling characteristics. Some of the differences are examined. Of particular
note is the use of balanced transmitters and receivers as well as the mixed mode of operation (RS-423). RS449 provides one example of connecting grounds where there may be a different potential at each end of the
communication channel.
RS-485 Bidirectional Drivers (starting on page 692)
RS-485 is a logical extension to RS-422. It provides the noise protection of RS-422 and the flexibility of bidirectional
communication. In fact, RS-485 provides for multiple drivers on a given pair of wires, however only one driver can
be enabled at a given instant.
Serial Peripheral Interface (SPI) (starting on page 698)
A description of the operation of the SPI interfacing technique. SPI provides an inexpensive, somewhat standardized
technique for connecting peripheral devices to processing elements.
Excalibur Avalon Bus (starting on page 706)
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The Avalon Bus is an unconventional bus structure. It is based on non-shared communication paths with multiplexers
to select interconnections between masters and slaves.
VME Bus (starting on page 709)
The VME bus example is used to show the use of termination resistors to provide load balancing. It also shows the
use of a daisy-chain wiring technique to facilitate multiple interrupt service providers.
SCSI (Small Computer System Interface) Bus (starting on page 715)
The SCSI bus is used to interconnect relatively complex devices. The coverage emphasizes: the unique scheduling
and data transfer structures (there are no address lines used during normal transfers, and the T arget (somewhat
like the slave) controls the transfer), and the use of one-hot addressing.
IEEE-488 (starting on page 732)
The IEEE-488 bus structure is intended to be used to interconnect lab instruments. The structure provides for
multicast transfers (where one source can send to multiple receivers in a single transfer) that are fully-interlocked.
In this case there are also no address lines used during the transfer.
Peripheral Component Interconnect (PCI) (starting on page 742)
PCI is used in many PC systems to connect complex device interfaces. It is a bus structured for block transfers.
The arbitration is based on a star connection.
Section Titles (starting on page 753)
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Note: Glossary
I:Course Introduction
II:Embedded Systems
embedded system: a special-purpose computer system designed to perform a task without the users knowledge of its existence.
The user may provide input to the embedded system via controls and sensors but the user need not be aware of the presence of the
embedded system. ( 22 )
Hardware: 3. the mechanical or electronic components of a computer etc. ( 26 )
Software: 1. the programs or other operating information used by a computer. 2. storage media such as video cassettes, audio
tapes, etc. requiring playback on electronic equipment ( 26 )
Microprocessors: A microprocessor consists of a processor only (no main memory and no I/O devices). ( 27 )
Microcontroller : A complete computer including a processor, memory and some input/output devices. These devices are usually
specified in a fairly general manner to permit reuse of the same microcontroller component in many applications. ( 28 )
System-On-a-Chip(SOC): A complete fully-functional system is implemented on a single integrated circuit. This may include processing, memory, input and output interfaces as well as any other digital logic. ( 29 )
Programmable Logic Device: A digital logic IC that permits configuration and interconnection of internal logic blocks. Often this
term refers to a computer chip that can be rewired to implement a custom digital circuit using primitive building blocks. ( 30 )
System-On-a-Programmable-Chip (SOPC): An SOC implemented using a high-density, reconfigurable PLD it is considered to be a
system on a programmable chip. ( 31 )
III:Interfacing Software, Introduction to Synchronization, and Device Drivers
CPU Latency and Device Latency : is the time between a service request and when the service is initiated. Latency can involve both
hardware and software delays. ( 36 )
Glossary of terms from the term
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Real-Time System: is one that guarantees a worst-case latency for critical events. ( 36 )
Latency : The delay between the arrival of the request and the completion of service. One could also consider the average latency or
the maximum latency by considering more results. (Note: on the surface this appears to be slightly different than the definition of
CPU Latency defined earlier. However, this difference can be resolved by noting that the system is viewed as completing the request
once the ISR has started.) ( 37 )
Throughput: is a measure of how many items can be processed per unit of time. For example, a system could have a very high
latency (5 years for UW Engineering) but still have a throughput of 900 graduates per year. ( 37 )
Blind Cycle: software waits a fixed amount of time and then acts on the data whether or not the device is ready ( 38 )
Periodic Polling : device status is checked after a pre-determined amount of time and this repeats until the device is done. This is
usually implemented with a timer interrupt. ( 38 )
Occasional Polling : device status is checked at the convenience of the designer. ( 38 )
Polling Loop (Gadfly or Busy Waiting): software continuously checks the I/O status, waiting for the device to be done. Although
this is often implemented as a very tight loop (one status register test and then loop if not yet ready), it could be implemented as a
series of tests (say test 5 I/O status registers and service any that are requesting service). ( 38 )
IV:Synchronization, Data Generation and Data Transfer
Producer : Either a software or a hardware component responsible for producing data (or events) for the consumer. ( 54 )
Consumer : Either a software or a hardware component responsible for consuming data (or using events) that have been produced
by the producer. ( 54 )
Data: The value (or values) that are transferred from the producer to the consumer. ( 54 )
Event: represents the occurrence of some activity that is communicated to the consumer. ( 54 )
Data Generation: How is the data creation controlled (if it is controlled). How is it started? stopped? Is this done by the Producer
or the Consumer? ( 56 )
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Data Notification/Initiation of transfer : Once the producer has the data, how does the producer notify the consumer that it is ready
for the data to be consumed? Or, alternatively how does the consumer request the data? ( 56 )
Data Transfer : Once the producer has the data and the Consumer is ready for the Data, how it the timing (synchronization) of the
transfer handled? ( 56 )
Synchronization: For our purposes this refers to the interaction required to make two entities (with different views of time) interact.
For example, when do the two applications interact? ( 58 )
Active Synchronization: One of the entities is capable of forcing a change in the operational characteristics of the other. For
example, setting an interrupt signal can force the processor to execute the interrupt service routine. ( 58 )
Passive Synchronization: One of the communicating entities signals a request for service, however the entity receiving the request is
not forced to respond. ( 58 )
Spontaneous Sources: Data is produced in the device independent of the actions of the consumer accepting the data. ( 62 )
Consumer Sensitive Sources: Data is produced by the device only after the previous data has been consumed by the consumer. (more
implicit.) ( 62 )
Consumer Responsive Sources: Data is produced by the device only after requested by the consumer. (more explicit.) ( 62 )
Data Transfer : Refers to all aspects of a transfer between two entities that have (potentially) different views of time. For example,
how do the two systems interact. ( 65 )
Data Persistence: How long data is valid for transfer between the communicating entities. ( 65 )
Time Synchronization and Clocking : How signals, representing any data, are specified and enabled to make the transfer happen. (
65 )
Control Signalling : How any control information is exchanged between the communicating entities. ( 65 )
Persistent: Information remains valid until consumer signals that the data has been collected (processed). ( 66 )
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Transient: Information is made available to the consumer and remains valid for a period of time and then may change. In most cases
the minimum period of time is known by the designer. ( 66 )
Global Initialization: setting processor and I/O interface parameters necessary for the overall operation on the system. (Eg., set
interrupt tables, specify unchanging bidirectional ports to input/output) Executed once. ( 70 )
Transfer Initialization: setting processor and I/O interface to facilitate a specific process. (Eg., set the memory location to accept
(provide) the data for the transfer, set the block and track number for a disk transfer.) Executed once per transfer. Later in these
notes, in the specific case of multiple transfers this step is referred to as Block Initialization ( 70 )
ttransf er producer : is the time for the device and interface combination to transfer one data unit. This determines the maximum rate
at which data could be available to the processor. ( 74 )
ttransf er
consumer :
the time the processor needs to transfer one data unit. This may be longer or shorter than ttransf er
but ( 74 )
tsynch : is the execution time of the processor to synchronize with the availability of the data. (I.e., the time that the processor is not
available for other activity.) ( 74 )
tsynchpoll : Polling synchronization uses processor time until just after the data is ready. ( 74 )
tsynchintr : Interrupt synchronization only starts to use CPU time after the data has become available. ( 74 )
tinterdata : is the time between consecutive data blocks. Although this time could vary between blocks, for these purposes it has been
assumed to be a constant. ( 74 )
V:Computer Structure
Address propagation delay (tP A ): The time for the address to propagate from the bus master to all of the potential slaves. ( 136 )
Data propagation delay (tP D ):
136 )
The time for the data to propagate from the data source to all of the potential data receivers. (
Bus Propagation delay : The maximum of the separate (Data and Address) propagation delays. ( 136 )
Setup Time (tSetup ): The minimum time that a signal has to be available at the input to the buffer before the active clock signal
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(edge) arrives. (At the slave for a write and at the master for a read.) ( 136 )
Hold Time (tHold ): The minimum time that data has to be held stable after the clock edge that triggers the transfer. (At the slave
during a write and at the master during a read.) ( 136 )
Select Time (tS or tSelect ): The time required for a device (or interface) attached to a shared communication media (a bus) to detect
that the current transfer involves the device (or interface). This time does not include any of the time required by the device (or
interface) to perform any internal address decoding. ( 137 )
Access Time (tAccess ): The time required for the interface to access the information for the bus after the device or interface has
been selected and the address is correct. The exact order that the select is correct and the address is correct may vary depending on
implementation details. The access time is the time following the last of these two events. ( 138 )
Store Time (tStore ): The time required for the interface to enable the correct location and to write the appropriate value into that
location after the device (or interface) has been selected and the address is correct. ( 138 )
Skew Time (tSkew ) (partial): For our purposes here the skew time is the difference (largest or worst case) in signal propagation
times. Although various sets of signals could have different values of skew time (E.g., the address lines or the data lines), one value,
the largest, is used in this presentation. A more general definition would be the magnitude of the difference between two events that
ideally would occur simultaneously. (This definition was taken from the JEDEC dictionary.) Of course this definition does allow for
skew on a single signal (discuss this with your instructor.) ( 138 )
Margin Time: In the figures in this section tM 1 (or tmargin1 ) and tM 2 (or tmargin2 ) are the times where there may be some design
flexibility. More generally, the margin time is the overdesign that a designer includes for safety to assure successful operation. ( 138
)
VI:Parallel Interfacing
Totem-Pole Driver : Both switches are active. A logic-1 is applied to the shared signal line by closing the pull-up switch and opening
the pull-up switch. In this driver one of the two switches is always closed and as a result it is not useful on a shared signal line. (
161 )
Passive Pull-up Driver : (often implemented and called open collector) Replaces the pull-up switch with a resistor (a passive component
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with no control input). In this way the line can be pulled low (for a logic-0) but a logic-1 results if no driver pulls it low. ( 161 )
Passive Pull-down Driver : The passive pull-down driver (open emitter) is the dual to the passive pull-down where the Pull-down
switch is replaced with a resistor. ( 161 )
Tri-state Driver : Both switches are active, however the logic driving the control inputs has been modified to permit both switches to
be off at the same time. When both are off the output floats and this driver is in the hi-impedance state (sometimes called Hi-Z).
( 161 )
In-Band: Some (or all) of the control information is passed in the same way that the data is transferred. For example, a control-C
in a text string looks like data, but in some cases may be interpreted as a control character with a special operation characteristic. (
172 )
Out-of-Band: The control signalling is done using techniques that cannot be confused with data. For example, there may be signals
at a frequency not found in the data, or there may be values on the data lines that cannot ever be data, or there may be extra signal
lines to indicate some control information. ( 172 )
VII:Error Detection and Correction
Hard Errors: permanent error (Eg. a memory bit stuck at some value) ( 199 )
Soft Errors: transient errors (Eg. the 4th bit of a transmission failed ... the error may not repeat) ( 199 )
Error Detection(ED): Given information to be transferred, sufficient (redundant) information is added (at the data source) to make
it possible to determine (at the data destination) that the received data is not the same as the original information. ( 200 )
Error Correction(EC): Given information to be transferred, sufficient (redundant) information is added (at the data source) to make
it possible to recover (at the data destination) the original information. ( 200 )
Error Rate: The rate of errors on the channel. This may be specified as a probability. For example, 106 indicates that, on average,
one bit in a million is in error. The errors may (or may not) be correlated. (I.e., the occurrence of an error may increase the likelihood
that the next bit will be in error.) ( 201 )
Overhead: For our purposes we define overhead as the number of non-data bits divided by the total number of bits transferred. (
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201 )
Data Word: The information bits that are to be transferred over a channel. In this case the data word has B bits of data. The data
word is the smallest unit for error correction or detection. ( 202 )
Code Word: The combination of the B bits of data and the C bits of error handling bits. ( 202 )
Distance: The minimum number of bits that must change to go from one code word to another code word ( 206 )
Syndrome: Combine the values of C Calc and C Rec to indicate the presence of and the location of an error in a received code word (
221 )
VIII:Serial Interfacing
Simplex: unidirectional as shown below ( 234 )
Half Duplex: bidirectional, one-way at a time, as shown below ( 234 )
Full Duplex: simultaneous bidirectional, as shown below ( 234 )
Bit Synchronization: How long is each bit? and Where do bits start (or stop)? ( 235 )
Bit Rate Synchronization: The time that elapses between the start of one bit and the start of the next bit. ( 235 )
Phase Synchronization: Given that the rate is known, how is the mid-point (or start) of each (or any) bit found. This amounts to
determining the phase relationship between the local clock and the clock used to transmit the data originally. ( 235 )
Byte Synchronization: Where do bytes start and stop? ( 235 )
Block Synchronization: Where do blocks start and stop? ( 235 )
Bit Rate: The number of bits that can be transferred per second over a channel. ( 240 )
Baud Rate: The maximum number of symbols that can be transferred per second over a channel. ( 240 )
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Communication Protocol: A set of rules for making connections and transferring information. ( 252 )
Overhead: (to be consistent with the previous definition) is
N umber of non data bits in a f rame

T otal number bits in a f rame
( 264 )
Framing Error : An incorrect frame has been detected. In the case of one-byte asynchronous transfers, the indication of a framing
problem is that the stop bit is incorrect (possible baud rate error) ( 265 )
Overrun Error : In a serial communication system, the data at the transmitter and receiver is transferred at a time convenient to the
controlling processor. As a result it may be that the serial data will arrive too quickly for the receiver to process the data. It is also
possible that the transmitter will be sending data faster than the serial channel can transfer the data. In either case, some data may
be overrun by the data following it in the channel. This is an overrun error. ( 265 )
Receive Overrun Error : At the receiver, incoming data has overwritten data in SRin or RCV register. ( 265 )
Transmit Overrun Error : Resulting from the CPU or the device writing to the transmit buffer before the current content of the
transmit buffer has been transmitted. ( 265 )
Parity Error : The parity of the received data and the value of the parity bit do not match ( 265 )
Start Bit Error : when the line is sampled one half of a bit time after the edge of the start bit is detected, the value is not zero. This
probably indicates that a false start bit has been detected, alternatively there may be some error in the assumed bit rate. ( 265 )
BISYNC Protocol: Modify the sequence of characters using hardware or software to provide block synchronization. (Byte synchronization is used to derive block synchronization.) ( 276 )
HDLC Protocol: Modify the sequence of bits so that synchronization can be maintained. (Bit synchronization is used to derived
block synchronization.) ( 276 )
USB Token Packet: Selects the slave for the communication. The slave includes: T arget device (7-bits), endpoint number (the I/O
register in the device (4-bits)), and the direction of transfer (in or out). ( 303 )
USB Data Packet: Payload information for the transfer up to 1023 bytes in isochronous case, and 64 bytes for other (full-speed)
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transfers. ( 303 )
USB Handshake Packet: When required, this is used to confirm to the data source that the data has been received (and accepted)
by the data destination. This is not required for isochronous transfers. ( 303 )
USB PID: There are 16 PID values. Each value is specified as 4-bits followed by the same four bits, complemented. For example:
ID 0101 (Start of Frame) is a PID of A5. ( 304 )
USB SOF Token Packet: In USB, a frame is used to provide some synchronization and to facilitate data transfer. In most cases,
the SOF packet will be sent once per millisecond to indicate a new cycle has started. The SOF token packet provides a number to
indicate that this is the start of the nth frame. Please note, the concept of frame used in USB (a sequence of activities that repeat
every 1 ms) is quite different from the concept used in the serial communication section of the notes. ( 305 )
USB IN Token Packet: The IN packet can be used for Interrupt, Bulk, Control and Isosynchronous transfers (more later). The IN
packet provides the address of the device and the I/O register (endpoint) to provide the data for the IN transfer. ( 305 )
USB OUT Token Packet: The same as IN except the communication channel being established is in the opposite direction. ( 305 )
USB SETUP Token Packet: Used to setup the remote device or hub. ( 305 )
USB ACK Packet: Error free receipt of data packet. ( 306 )
USB NACK Packet: Unable to accept or return data. Also used during polling to indicate that no new data is available. ( 306 )
USB STALL Packet: T arget unable to complete transfer and software intervention is required. ( 306 )
USB Interrupt Transfer : Traditional small volume transfers. There is no interrupt facility on the USB, so each device must be polled
at a regular interval to see if a new value has been entered for action. During the interval between polling, a device could lose data,
but every piece of data must be delivered, therefore there is a time critical component. ( 307 )
USB Bulk Transfer : Used by block transfer devices. Once the transfer has been started, there is no particular time constraint. Every
piece of data must be delivered. ( 307 )
USB Isochronous Transfer : Typically real-time data. The data must be read/written with a given rate. If one item is missed it can
XVII - 0.10
Glossary
787
be ignored and processing continues. Every piece of data need not be delivered. ( 307 )
USB Control Transfer : Used to setup devices. ( 307 )
IX:Analog Interfaces
Comparator : An op-amp connected without feedback can be configured to be a comparator. In this case the output values are close
to either VS or V+S ( 327 )
Inverting Amplifier : An op-amp configured with a resistor feedback element such that an increase in the input voltage results in a
decrease in the output voltage ( 330 )
Non-Inverting Amplifier : An op-amp configured with a resistor feedback element such that an increase in the input voltage results
in an increase in the output voltage ( 336 )
Non-Inverting Buffer : A special case non-inverting amplifier Rf = 0; Rin = ( 337 )
settling time: the time for the output to settle within a specified range of the final value for a given input. ( 338 )
slew rate: the rate at which signals change from one value to another. ( 338 )
Quantization: When an analog signal is reduced from a continuous signal to a set of digital values, a range of analog signals must
be assigned a single digital value (quantity). The act of this transformation is quantization. ( 339 )
LSB: On the analog side, one LSB is the change in the analog signal that corresponds to a change of one digital LSB (one bit). A
more mathematical specification is that 1LSB =
F SAR
2n 1 ,
where F SAR is the full-scale analog range and n is the number of bits used
by the digital representation. ( 339 )

Multiplying DAC (M-DAC): A digital-analog-converter configured so that the analog input (voltage) signal (previously referred to as
Vref ) is a varying signal. Such a system would have an output analog voltage of: Vout = k B Vin as shown below. ( 353 )
Resolution (DAC and ADC): The number of bits in the digital value used for the input to the DAC (or the output from the ADC).
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Glossary
788
Eg., 12-bits ( 354 )

Precision (DAC and ADC): The smallest distinguishable change in output. Ideally 1 LSB. (Eg. for a 12-bit D/A 1 in 212 or
0.024% of full scale.) ( 354 )
Accuracy : Comparison of the actual output to the expected output. ( 354 )
Range: The maximum output value minus the minimum output value. ( 355 )
Dynamic Range: The New Penguin Dictionary of Electronics defines dynamic range as: The range over which an active electronic
device can produce a suitable output signal in response to an input signal. It is often quoted as the difference in decibels between
the noise level of the system and the level at which the output is saturated (the overload level). ( 355 )
Offset Error : An analog shift in the output of a DAC that is constant over the full range of digital input values. ( 356 )
Gain Error : An error in the analog output of the DAC that varies (linearly) with the digital value applied. Errors in gain can often
be attributed to errors (or drift) in resistor values. May also be caused by changes in the reference voltage. ( 357 )
Differential Non-Linearity (DNL): The differences between the analog values corresponding to consecutive (input) digital values. (
359 )
Monotonicity Error : If, for any two consecutive digital values, increasing from i to i + 1 results in a decrease in output (analog)
values, there is a monotonicity error. This can occur if DNL > 1LSB. ( 360 )
Integral Linearity : The maximum deviation between the true output and a straight line representing the ideal output. This calculation/measurement is based on the assumption that all of the linear errors have been eliminated (compensated). ( 361 )
Power supply rejection ratio: A measure of how sensitive is the converter to changes in the power supply voltage. ( 363 )
Glitch Impulse: At the time that the digital value changes from one value to another, the analog output may not change directly
from one value to the other. For example not all of the internal switches will change at the same rate and thus some erroneous
values may appear at the output. This is also referred to as Glitch impulse area ... it is the area in the glitch caused by the different
switching times. ( 365 )
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Glossary
789
Missing Code: It may be that some digital values can never be generated due to some errors in the ADC. If this is the case, the
missing values are referred to as missing codes. ( 412 )
Converter Aperture Time: The (maximum) time that the converter output (result) is sensitive to changes in the analog signal. (
413 )
Nyquist Sampling Rate: If a time varying signal contains components of significant amplitude only below f Hz, then a sample
frequency of greater than ( 414 )
Sample and Hold Aperture Time: the time required for Q to turn off once the hold signal is asserted. (Tof f ). ( 426 )
(Sample and Hold) Aperture Uncertainty : the change in time between the command to turn Q off and the actual time Q turns off.
(Jitter in the figure) Changes in Tof f ( 427 )
Droop: A drop in the signal out of the sample and hold circuit. It is caused by discharge of C due to: ( 429 )
Acquisition Time: The time required before the capacitor voltage is within a specified percentage of the final value (as distinct from
the settling time which worries about the voltage into the A/D converter, as opposed to the voltage across the capacitor.) ( 430 )
X:Buses - Data Transfer
Synchronous Data Transfer : The transfer of data between communicating entities with a common view of time. In this case there
is a global clock and data is transferred at a specific point in the clock period. Also all transfers are of fixed duration (one clock
period. There is no feedback from the consumer to the producer of the data to alter the rate of transfer or to alter the duration that
the data is valid. ( 437 )
Asynchronous Data Transfer : The transfer of data between communicating entities with different views of time. In this case there
is no global clock, and there is a mechanism to permit variable transfer times. This mechanism may be either fully or partially
interlocked. ( 437 )
Semi-synchronous Data Transfer : The transfer of data between communicating entities which have a common view of time (a
global clock), however permit variable transfer times. The transfer times are an integral number of clock cycles in length where The
actual number of clock cycles is somewhat under the control of the slave. ( 437 )
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Glossary
790
Split-cycle Data Transfer : The transfer of data between communicating entities which only permits a transfer from the producer to
the consumer. As a result, read transfers are accomplished in two cycles each of fixed duration, one in each direction. Write transfers
are accomplished in a single transfer. ( 437 )
XI:Buses - Arbitration
Bus Arbitration: A process that seeks to select exactly 1 Master from one or more devices requesting to be the bus master. ( 479 )
Non-pre-emptive arbitration: Once a master has started using the bus it will continue to use the bus until completion. Specific bus
structures may place limits on the maximum number of cycles or the maximum time that a master may keep control of the bus. (
481 )
Central Arbiter (CA): The portion of the arbitration system responsible for detecting that there is a bus request and causing a grant
to be issued, if appropriate. ( 482 )
Distributed Arbiter (DA): The portion of the arbitration system that is repeated in each device interface that has a requirement to
become a bus master at some time. ( 482 )
Fundamental Mode Assumptions:
(1) inputs only change one at a time. That is, the probability of two signals changing simultaneously is 0 and
(2) the output (state) signals stabilize before the next input change is received. ( 507 )
XII:Direct Memory Access(DMA)
Cycle Stealing : Transfer only 1 byte (word) per bus mastership ( 561 )
Transparent: If the processor makes idle cycles known, then it is possible to structure the system so that DMA controllers only claim
the bus when the processor does not need it. ( 561 )
Burst: Multiple transfers are permitted per bus mastership. This would permit the transfer of (up to) the entire block in one bus
mastership. ( 561 )
Integrated DMA Controller : The DMA control functions (Byte Count Register, MAR, Control Register and Status register functions)
XVII - 0.10
Glossary
791
are part of the device interface that is using the DMA functionality. ( 572 )
Detached DMA Controller : The DMA control functions are implemented as an interface separate from both the processor and the
interface(s) that use the DMA functionality. ( 572 )
Dual Address Protocol: In this DMA protocol two address cycles are used per transfer, one to read the data from the source and
one to write the data to the destination. ( 572 )
Implicit Address Protocol: In this DMA protocol only one address cycle is used per transfer. The controller causes the source to
place the data on the bus and the destination to copy the data from the bus at the appropriate time. ( 572 )
Continuation Registers: are registers, within the DMAC that contain an image of the next values for MAR, BCR and Control
Registers. When the current transfer is complete, these values are copied in to the active channel. Often the continuation registers
are implemented using an unused channels control registers. ( 589 )
Data Chaining : In this model, two channels registers are used. One, the data channel, points to the data that is being read or written.
The second channel, the chaining channel, points to a list of future DMA transfers (setup in memory by the processor). When the
byte count register of the data channel reaches 0, the next values pointed to by the chaining channel registers are transferred from
memory to the data channel registers. ( 590 )
XIII:Grounding, Shielding and Transmission Line Issues
Signal Ground: A point in a circuit used to reference all signal values. This point is often considered the zero voltage point. ( 605 )
DC Ground: The reference point for all DC signals in a given circuit block. ( 605 )
AC Ground: The reference point for all AC signals in a given circuit block. ( 605 )
Digital Ground: The reference point for all digital signals in a given circuit block. ( 605 )
Analog Ground: The reference point for all analog signals in a given circuit block. ( 605 )
Shield Ground: It is often important to shield a circuit (or a cable). As described later, one requirement for this is a shield ground.
( 605 )
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Glossary
792
Building Ground: The point in a building where the power lines are attached to earth ground. ( 605 )
Earth Ground: The common point used to reference building grounds. ( 605 )
Ground Loop: The current flow in the ground circuit. (As distinct from the current flow in the neutral signal.) ( 610 )
Common Mode Rejection Ratio: The ability of the receiver to ignore the changes common to both input lines is indicated by the
receivers common mode rejection ratio. ( 622 )
Characteristic Impedance (Z0 ): The ratio of the propagated voltage to the propagated current at every point on the line. Z0 is the
characteristic impedance of the line. ( 639 )
Reflection Coefficient : The reflection coefficient specifies the ratio of the reflected voltage (current) to the incident voltage
(current). It is useful as an abstraction only in systems where the various loads and sources can be modelled as linear components.
In some literature the reflection coefficient is referred to as . ( 650 )
XIV:Examples (Signalling and Buses)
Reselection: After some or none of the data that has been requested by the Initiator has been transferred, the T arget releases the
bus to await data to become available. Once the data is available the T arget arbitrates for the bus and becomes a bus master (as
the T arget). The process is reselection. ( 729 )
XV:List of Contents
XVI:Summary of Contents
XVII - 0.10

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ECE 224 and MTE 325

Embedded Microprocessor Systems

Course Introduction: Section Contents

Section Contents: Course Introduction

Introduction ECE 224/MTE 325

ECE224/MTE325 Course Goals

Computer Interfacing Analogy

ECE224/MTE325 Course Goals

ECE224/MTE325 Course Goals

Course Resources: Summary from Syllabus

Information and discussion

ECE224/MTE325 Course Goals

ECE224/MTE325 Course Goals

When the Temp is over 80 degrees shut the damper

View A: System-Centric View

View B: Computer-Centric View

Overview of Course Material

Note: Sensors and Actuators

Mechanical:Electrical switches, strain gauges

Optical:Electrical light meter

Thermal:Electrical temperature sensor

Electrical:Mechanical motors, speakers, solenoids

Electrical:Chemical electrodes for electroplating

Electrical:Optical electronic displays. fibre-optic drivers

Electrical:Thermal resistive heaters, Pelletier devices

Electrical:Magnetic electro-magnets (or magnetic coils)

Data Flow Issues

Embedded Systems: Section Contents

Section Contents: Embedded Systems

Introduction to Embedded Systems

Introduction to Embedded Systems Evolution

Embedded System Design

What is embedded system design?

Microprocessors vs. Microcontrollers

Microprocessors vs. Microcontrollers Cont.

Programmable Logic Device (PLD)

Note: Terms used in Embedded Systems

embedded system (page 22)

Interfacing Software, Introduction to Synchronization, and Device Drivers

General Synchronization Introduction: Section Contents

Section Contents: Interfacing Software and an Introduction to Synchronization

Interfacing Software, Introduction to Synchronization, and Device Drivers

level functions interact directly with the systems hardware.

A comparison of the abstraction layers for software development.

Interfacing Software, Introduction to Synchronization, and Device Drivers

When a device completes its

Interfacing Software, Introduction to Synchronization, and Device Drivers

Performance, Latency and Throughput

Some unit that

Latency for the ith request is Tpi-Tri

Interfacing Software, Introduction to Synchronization, and Device Drivers

Interfacing Software, Introduction to Synchronization, and Device Drivers

Synchronization Mechanisms Cont.

Interfacing Software, Introduction to Synchronization, and Device Drivers

Polling Loop Synchronization Input

poll device and wait until data is available

Interfacing Software, Introduction to Synchronization, and Device Drivers

Polling Loop Synchronization Output

Interfacing Software, Introduction to Synchronization, and Device Drivers

Interfacing Software, Introduction to Synchronization, and Device Drivers

Multiple interrupt request lines

Interfacing Software, Introduction to Synchronization, and Device Drivers