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Liberty Syntax for

Power and Ground (PG) Pin


Standard Cells
Application Note
Version 1.0
A-2007.12, December 2007

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Copyright Notice and Proprietary Information


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1 Liberty Power and Ground (PG) Pin Syntax


1.1 Introduction
The following sections provide information about power and ground (PG) pin syntax.
Library Compiler version Y-2006.06 or later is required to compile a library based on
power and ground pin syntax. All future Liberty syntax updates will be based on the
power and ground pin Liberty syntax.
In order to overcome the limitations in the solution based on the rail_connection
attribute and single ground pin, and to satisfy new Synopsys tool requirements, the
syntax needs to be applied on all cells, including standard cells. The following section
provides the general syntax for power and ground pin libraries in standard cells. The
same syntax is also applicable to all other categories of special cells.

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1.2 Liberty Syntax for Power and Ground Pins


The power and ground pin syntax for standard cells has been changed as follows:
library(<library_name>) {
...
voltage_map(<voltage_name>, <voltage_value>); /* See section 1.3.1 */
voltage_map(<voltage_name>, <voltage_value>); /* See section 1.3.1 */
...
operating_conditions(<oc_name>) {
...
voltage : <value>;
...
}
...
default_operating_conditions : <oc_name>;/* See section 1.3.2*/
cell(<cell_name>) {
pg_pin (<pg_pin_name_p>) {
voltage_name : <voltage_name_p>;
pg_type : <type _value>;
}
pg_pin (<pg_pin_name_g>) {
voltage_name : <voltage_name_g>;
pg_type : <type _value>;
}

/* See section 1.4.1*/


/* See section 1.4.2*/
/* See section 1.4.3*/
/* See section 1.4.1*/
/* See section 1.4.2*/
/* See section 1.4.3*/

...
leakage_power() {
related_pg_pin : <pg_pin_name_p>;/* See section 1.5.3*/
...
}
...
pin (<pin_namem0>) {
direction : input/inout;
related_power_pin : <pg_pin_name_p>; /* See section 1.5.1*/
related_ground_pin : <pg_pin_name_g>;/* See section 1.5.1*/
...
}
...
pin (<pin_namen0>) {
direction : inout/output;
power_down_function : ( !pg_pin_name_p + pg_pin_namem_g ) ; /* See
section 1.5.2*/
related_power_pin : <pg_pin_name_p>; /* See section 1.5.1*/
related_ground_pin : <pg_pin_name_g>;/* See section 1.5.1*/
internal_power() {
related_pg_pin : <pg_pin_name_p>; /* See section 1.5.3*/
...
} /* end internal_power group */
...
}/* end pin group*/
...
}/* end cell group*/
...
}/* end library group*/

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1.3 Library-Level Attributes


1.3.1 voltage_map Complex Attribute
The library level voltage_map attribute associates the voltage name with the
relative voltage values. These specified voltage names are referenced by the pg_pin
groups defined at the cell level. If specified in a library, this syntax identifies the
library as a power and ground pin library.
1.3.2 default_operating_conditions Simple Attribute
The default_operating_conditions attribute is required to explicitly specify
the default operating_conditions group in the library, which helps to identify
the operating condition process, voltage, and temperature (PVT) points that are used
during library characterization. There should be at least one voltage_map attribute
defined in the library with a logic value of 0 because there is always a ground
reference voltage with a logic value of 0 during library characterization.

1.4 Cell-Level Attributes


1.4.1 pg_pin Group
The cell-level pg_pin groups are used to represent the cells power and ground pins.
Library cells can have multiple pg_pin groups. The pg_pin groups are mandatory
for each cell using the power and ground pin syntax, and a cell must have at least one
primary_power power pin, and at least one primary_ground ground pin.
1.4.2 voltage_name Simple Attribute
The voltage_name string attribute is mandatory in all pg_pin groups. The
voltage_name attribute specifies the associated voltage name of the power and
ground pin defined using the voltage_map complex attribute at the library level.
1.4.3 pg_type Simple Attribute
The pg_type attribute specifies the type of power and ground pin and is optional in
pg_pin groups. The pg_type attribute can have the following values:
primary_power, primary_ground, backup_power, backup_ground,
internal_power, and internal_ground. Table 1 describes the pg_type values.

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Table 1: pg_type Values


Value

Description

primary_power

Specifies that pg_pin is a primary power


source (the default). If the pg_type attribute
is not specified, primary_power is the
pg_type value.

primary_ground

Specifies that pg_pin is a primary ground


pin.

backup_power

Specifies that pg_pin is a backup


(secondary) power source (for retention
registers, always-on logic, and so on).

backup_ground

Specifies that pg_pin is a backup


(secondary) ground source (for retention
registers, always-on logic, and so on).

internal_power

Specifies that pg_pin is an internal power


source (for switch cells).

internal_ground

Specifies that pg_pin is an internal ground


(for switch cells).

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1.5 Pin-Level Attributes


1.5.1 related_power_pin and related_ground_pin Attributes
The related_power_pin and related_ground_pin attributes are defined at the
pin level for output, input, and inout pins. The attributes are used to associate a
predefined power and ground pin to the corresponding signal pins.
If you do not specify the related_power_pin and related_ground_pin
attributes, the primary power and primary ground pins are related to the signal pins by
default. This behavior only applies to standard cells. For special cells, you must
explicitly specify this relationship.
1.5.2 power_down_function Attribute
The power_down_function string attribute identifies the Boolean condition under
which the cells signal output pin is switched off (when the cell is in off mode due to
the external power pin states). If power_down_function is set to 1, then X is
assumed on the pin.
1.5.3 related_pg_pin Attribute
The related_pg_pin simple attribute associates the power data (both leakage and
internal) to a specific power pin, and it is not the same as the related_power_pin
and related_ground_pin attribute pairs. These attributes assume a single ground
pin that is set at 0.0 volts (which is an ideal ground) by using that ground as the
reference for all other non-zero power and ground pins. As a result, the tool knows the
amount of power consumed by the cell when connected to multiple power supplies.

1.6 Library Compiler Checks


Library Compiler issues a warning or error message if the following conditions occur
when you are modeling a standard cell using the power and ground pin syntax:

Library Compiler issues an error message if the voltage_map complex


attribute is defined at the library level and all cells in the library do not have
the pg_pin groups defined for all cells.
Library Compiler issues an error message if the voltage_map complex
attribute is specified inside the operating conditions group.
Library Compiler issues an error message if you do not have at least one
power pin and at least one ground pin in a cell modeled using the power and
ground pin syntax.
If a cells signal pins are not associated to the power pins using the
related_power_pin and related_ground_pin attribute pairs, Library
Compiler issues a warning message and, by default, makes the association of
the signal pins to the primary power and the primary ground pins.

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1.7 Naming Conventions for Power and Ground Pins in Logic


Libraries
The pg_pin names must match the names of the power and ground pins in the
physical library exactly in order to correctly link the physical and logical views. For
example, if the name of your power and ground pin in the physical view is VDD for
power and VSS for ground, the same names should be specified in your logical library,
as shown in the following example:
pg_pin(VDD) {

}
and
pg_pin(VSS) {

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2 Examples
2.1 Standard Cell with One Power and Ground Pin
The figure below shows a buffer cell modeled using Liberty power and ground pin
syntax.

Figure 1. Sample schematic of a standard cell buffer


library(Standard_cell_library_example) {
voltage_map(VDD, 1.0);
voltage_map(VSS, 0.0);
operating_conditions(XYZ) {
voltage : 1.0;
...
}
default_operating_conditions : XYZ;
cell(BUF) {
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
leakage_power() {
value : 1.5;
}
pin(A) {
related_power_pin : VDD;
related_ground_pin : VSS;

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}
pin(Y) {
direction : output;
power_down_function : "!VDD + VSS";
related_power_pin : VDD;
related_ground_pin : VSS;
timing() {
related_pin : A;
cell_rise(template) {
...
}
cell_fall(template) {
...
}
rise_transition(template) {
...
}
fall_transition(template) {
...
}
}
internal_power() {
related_pin : A;
...
}
}/* end pin group*/
...
}/*end cell group*/
...
}/*end library group*/

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2.2 Multiple-Rail Standard Cell with Two Power Pins and One
Ground Pin
The figure below shows a multiple-rail cell modeled in Liberty using power and
ground pin syntax. The blue arrows highlight the signal pin that is associated to the
power and ground pins.

Figure 2. Sample schematic of a standard cell buffer


library(Standard_cell_library_example) {
voltage_map(VDD, 1.0);
voltage_map(VDD2, 1.5);
voltage_map(VSS, 0.0);
operating_conditions(XYZ) {
voltage : 1.0;
...
}
default_operating_conditions : XYZ;
cell(Multi_rail) {
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(VDD2) {
voltage_name : VDD2;
pg_type : primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;

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}
leakage_power()
related_pg_pin
value : 1.5;
}
leakage_power()
related_pg_pin
value : 2.0;
}

{
: VDD;

{
: VDD2;

pin(A) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
pin(A) {
related_power_pin : VDD;
related_ground_pin : VSS;
}

pin(Y) {
direction : output;
power_down_function : "!VDD + !VDD2 + VSS";
related_power_pin : VDD2;
related_ground_pin : VSS;
timing() {
related_pin : "A B";
cell_rise(template) {
...
}
cell_fall(template) {
...
}
rise_transition(template) {
...
}
fall_transition(template) {
...
}
}
internal_power() {
related_pin : "A B";
related_pg_pin : VDD;
...
}
internal_power() {
related_pin : "A B";
related_pg_pin : VDD2;
...
}
}/* end pin group*/
...
}/*end cell group*/
...
}/*end library group*/

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3 References
[1] Liberty Syntax for Level-Shifter and Isolation Cell Modeling Application Note,
A-2007.12 (Version 1.0)
[2] Liberty Syntax for Switch Cell Modeling Application Note, A-2007.12
(Version 1.0)
[3] Liberty Syntax for Retention Cell Modeling Application Note, A-2007.12
(Version 1.0)
[4] Liberty Syntax for Always-On Cells Application Note, A-2007.12 (Version 1.0)

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