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Semester: 6 th
2.
(b)
Step I: Address decoding table:
Hex Address
Memory
2114
SRAM-3
0
0
0
0
00800
00FFE
0
0
00000
007FE
0
0
0
0
0
0
A8
A7
A6
A5
A4
A3
A2 Al
0
1
0
1
0
1
A0
00 00
2114
SRAM
Binary address
10 A9
A l 9 A 18 A17 A16 A15 A14 A 13 Al2 All A
IC
A19
A 14
&
cs i Oez
74LS138
3 to 8 Decoder
Step Ill: Connection of memory IC 2114 with microprocessor 8086 in minimum mode
"NB<
1.1
CLOCK
aioncRALoK
8284
luEsEr
RES
x110
CL
71/773
RD
MUliff
RD
PEADV,
f81 X
ft 74214
(04710 71.)
RDY
ORD
ALE
ERE/ S7
WAIT STAIR
GIIIIRATOR
Alp f
Axis
ADO
r-
OP771:671411
Alp
16 MD
DTtli
46B2/ X4/1,604i--If ROTC
D3 D0 A9
MICROPROCESSOR
8386
1R:4 SRAM
Even -
- AO
IR 4 SRA]
Odd -
eS 0
IL:4 SRAM
Ere: -
1K x
4 SRA
oad -
EVEN HANK
ODD BANE
(c)
ax DBDC
WEI
8284 CLOCK
CONERATOR
v1 Bas
CLE
..1137771
lAnC
eXt11
SO
I1!
To
RES
pwc
READY
Di
RDY
ALE
1111K
Ae
Al
LATCH
80e2
AD, APp
WAILS/ME
cat31
0111KiLeSOF
r- fr
De D7
Do
WA RS INSA
MICROPROCMS01
DO D7
RAH
BC
uni
RE di
it D,
1331/
DO DAIS
Wl
PER7PRERAZ
LW MK
as IR7
(d)
Result=
+ x1002
LODSB
IMUL AL
ADD DX, AX
LOOP L1
RFT
3.
(b)
MOV AX, 4000h
MOV ES, AX
MOV DI, 3000h
MOV CX, 0080h
L1:
MOV AL, 00
CLD
L2:
STOSB
ADD AL, 11
.IC L1
LOOP L2
HLT
(c)
(d)
MOV BX, AX
SAL AX, 1
ADD BX, AX
ADD BX, DX
MOV CL, 02h
SAL DX, CL
ADD BX, DX
SAL BP, 1
ADD BX, BP
MOV CX, BX
HLT
4.
(a)
There is no direct instruction to set or reset the trap flag. Trap flag can be set or
reset by using tack instruction.
To set the trap flag
> 4,
8 hiSB'S
8 LSB'S
1.:
015
AX
D8 D7
PUSH AX
DO
1
D15
POPF
SS: SP
D8 D7
DO
D15
FLAG REG.
D8 D7
DO
8 LSB'S
0
AX
D15
D8
07
DO
D15
D8
D7
DO
D15
D8 D7
TF
DO
PUSH AX
SS: SP
POPF
FLAG REG.
(b)
16 15
31
EAX
Ali
AL
AX
EBX
BH
BL
BX
ECX
CH
CL
CX
EDX
DH
DL
DX
ESP
BP
ESI
SI
EN
DI
ESP
SP
16 15
31
EIP
IP
EFLAGS
FLAGS
0
15
CS
SS
DS
SEGMENT
REGISTERS
ES
FS
GS
(c)
The given value in DS is 1007h
Expressing this value in the binary form, we get
13:P=01301000000000111
By comparing this value with the format of segment register in the protected mode, we
get
15
TI I
1
RPL
Since the last two significant bits are used to define the RPL and are both 1, so
RPL = 11 (3)
The next bit i.e. bit 2 is indicates table index, TI = 1 so the segment descriptor is in the
local descriptor table (LDT)
5
The most significant 13 bits are used to select any one descriptor from the total 8192
(8K) descriptors
(0001000000000) 2 =
x 2 12 + 0 x 2 11 + 0 x 2 1 + 1 x 2 9 + 0 x 2 8 +
0 x 2
= (512) 10
Sothedscripnumb512elctd.
Each descriptor is of 8 bytes; therefore the address of the 512 th descriptor is
Address of the segment descriptor = Base address + (512 x 8)
512 x 8 = 4096
=1000h
Therefore,
Address of the segment descriptor = 10000000h + 1000h
= 10001000h
(d)
Restricted access
41
Applications
(User software)
Application
Services
(OS extensions)
System
Services
Task C
Task A
Unre tricted
Loc access
PL= 0
111.
110
Task I3
PL (Privilege level)
5.
(b)
CONTROL UNIT
BUS
CONTROL WORD
PROGRABLMABL
SNIFFER
EXPONENT
MODULE
STATUS WORD
FUNCTION
BUS
INTERFACE
-"I
NEC INSTRUCTION
DATA
16
wARITRMAT1C
MICROCODE
CONTROL UNIT
14..40 DATA
MODULE
68,
16
BUFFER
OPERANDS
QUEUE
64,
TEMPORARY
REGISTERS
16
T
A
G
--REGISTER STACK ---
R
E
S
ADDRESSING &
BUS TRACKING
STATUS
T
E
R
EXCEPTION
POINTERS
ADDRESS
MI
80 BITS
(c)
0
15
IC
RC
PC
IEM
PM
UM
OM
714
DM
IM
PRECISION CONTROL
ROUNDING CONTROL
INFINITY CONTROL
RESERVED
(d)
Area of a circle is A= fl * R 2
Program:
MOV AX, 3000h
REPEAT:
MOV DS, AX
FLD [SI]
FST ST (1)
FMUL
FLDPI
; Load
FMUL
FST [DI]
INC SI
n to ST
INC DI
LOOP REPEAT
HLT / INT 3
6.
(b)
(
RESET
V
Transfer ICWI to Master and
all Slave (Port 0)
I
8259 is Initialize and Ready
to Receive Interrupts
(d)
D7
D6
Sc I
SCO
D5 D4 D3
RL1
M2
RL0
D2 DI
MI
MO
Do
BCD
SC-SELECT COUNTER
BCD
SCI
SCO
SELECT COUNTER 0
SELECT COUNTER 1
SELECT COUNTER 2
OPERATION
ILLEGAL
( 8254 READ BACK
COMMAND )
OPERATION
HEXADECIMAL COUNT
BCD COUNT
IPP M - MODE
M2
Ml
MO
MODE 0
OPERATION
RL - READ / LOAD
MODE
RL1
RLO
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
7.
(b)
!
CLK
(8284)
T2
BHE / S7 &
T4
S7* S to S3
Al et s
A191S6
T3
D15 D
ALE
i2
SO
Sp Active
2
S2 $U
inactive
DIRDC /IORC
DT /II 7\
DT /R =0
DEN
READY = I
(8284)
10
(c)
Total memory = 32K word = 64K bytes
IC available = 16K bytes
Hence number of RAM IC required = 64K x 8/16K x 8 = 4 IC's
So,
Even bank = 2 IC's of 16K x 8 RAM
Odd bank = 2 IC's of 16K x 8 RAM
Step I: Address decoding table for even bank:
Mown'
IC
Binary address
Hex Addles
Ag
A7
A6
A5
A4
A3
A2 A l
AO
16Kx8
RAM -- C.
00000
07FFE
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
16Kx8
RAM--@
08000
OFFFE
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
1
00
To Decoder
1<
To 16K IC
In the above address decoding table 16K x 8 RAM -1 and 16K x 8 RAM -3 is shown
because 16K x 8 RAM -2 and 16K x 8 RAM 4 is connected as odd memory bank.
Step II: Generation of CS using decoder:
A18 A19 M
0
To cso
A17
To
A16
A15
11
8284 CLOCK
GEN11283011
RES
wro
BIS=
/3
RD
17 74244
BEADY
(OPTIONAL)
EDT
ALE
eza2
LATCH
BRE/
WAIT STAIR
G12112144701
A19/86 4 16 (5 3
(2 013)
Arts 4D0
1-2
06pti2n4F
.4 14
16
AT,/
ta
DI/24
re
11141438111111
8284
(21
14/CROPROCESS OR
8085
MK BANE
16K x 8 RAM- 2
Odd
16R
8 RAM-- 4
Odd
ODD BANK
(d)
Solution:
I/O ports
Address
CHO AR
70h
CHO TCR
71h
CH1 AR
72h
CH1 TCR
73h
CH2 AR
74h
CH2 TCR
75h
CH3 AR
76h
CH3 TCR
77h
CWR/SWR
78h
Program:
IN AL, 78H
RRC
JC 1000h
RRC
; TC1 -> CF
JC 2000h
JMP 3000h
12