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Low Voltage Full Bridge Brushless DC Motor Driver with Hall Commutation and
Soft Switching, and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
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A1442
Low Voltage Full Bridge Brushless DC Motor Driver with Hall Commutation and
Soft Switching, and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
Features and Benefits
Description
The A1442 is a full-bridge motor driver designed to drive lowvoltage, brushless DC motors. Commutation of the motor is
achieved by use of a single Hall element to detect the rotational
position of an alternating-pole ring magnet. A high-density
CMOS semiconductor process allows the integration of all
the necessary electronics. This includes the Hall element, the
motor control circuitry, and the full output bridge. Low-voltage
design techniques have been employed to achieve full device
functionality down to low VDD values. This fully integrated
single chip solution provides enhanced reliability (including
reverse battery protection and output short circuit protection)
and eliminates the need for any external support components.
The small package outline and low profile make this device
ideally suited for use in applications where printed circuit board
area and component headroom are at a premium. It is available
in a lead (Pb) free, 6 pin MLP/DFN microleadframe package,
with an exposed pad for enhanced thermal dissipation.
Approximate scale
Output
Full Bridge
Reverse Battery
SLEEP
0.1 F
Active Braking
Control
Stall Detection
Hall
Element
Q1
Q3
Drive Logic
and
Soft Switching
Control
VOUT1
VOUT2
Q2
Amp
Q4
Thermal Shutdown
Protection
GND
A1442-DSW, Rev. 2
A1442
Selection Guide
Package1
Packing
Part Number
A1442EEWLT-P2
1Contact Allegro
Symbol
VDD
Notes
VRDD
Output Voltage
VOUT
VDD > 0 V
VROUT
VDD > 0 V
VIN
IOUTpk
Units
5.0
5.0
0 to VDD + 0.3
0.3
0 to VDD + 0.3
400
mA
< 1 ms
TA
Rating
40 to 85
Junction Temperature
TJ(max)
165
StorageTemperature
Tstg
65 to 165
Pin-out Diagram
Range E
VDD 1
SLEEP 2
NC 3
6 VOUT2
PAD
5 VOUT1
4 GND
Name
VDD
SLEEP
Function
Supply voltage
Toggle sleep/enabled modes
NC
GND
No connection
VOUT1
First output
VOUT2
Second output
Ground
A1442
OPERATING CHARACTERISTICS valid over the full VDD and TA range unless otherwise noted
Characteristic
Symbol
Supply Voltage1
VDD
Supply Current
IDD(ON)
RDS(on)
IRDD
Test Conditions
Min.
Typ.
Max.
Units
2.0
4.2
mA
10
3.9
2.6
2.2
VRDD = 4.2 V
10
mA
VINHI
0.7VDD
VINLO
V
0.2VDD
IIN
VIN = 3.0 V
1.0
IRIN
VRIN = 4.2 V
10
mA
tRS
120
ms
tS(CHOP)
80
Restart Delay4
Hall Chopping Settling Time
Magnetic Switchpoints2
BOP
35
75
BRP
75
-35
BHYS
70
B < BRP
LOW
B > BOP
HIGH
B < BRP
HIGH
B > BOP
LOW
1 A bypass capacitor of 0.1 F is required between VDD and GND for proper device operation through the full specified voltage range.
VOUT1
Output Polarity
VOUT2
2 Extended V
DS(on)
DS(on)Q4 or RDS(on)Q2 + RDS(on)Q3.
4 The Restart Delay is the time the outputs are on or off when the device is attempting a restart.
A1442
Characteristic Performance
RDS(on) ()
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
Functional Description
Soft Switching The A1442 device includes a soft-switching algorithm that controls the output switching slew rate for
both output pins. As a result the A1442 device is ideal for use in
applications requiring low audible switching noise and low EMI
interference.
L
E
E
P pin accepts an external signal that
Sleep Mode The S
enables sleep mode. In sleep mode, the current consumption is
A1442
Application Information
Note that:
No external diode is required for reverse battery protection
because the protection is fully integrated into the IC.
Thermal shutdown is integrated also.
VBATT
+
VDD
System Logic
Control
CBYP
VOUT1
A1442
SLEEP
I/O
VOUT2
M
NC
GND
VBATT
VDD
System Logic
Control
VOUT1
A1442
SLEEP
I/O
VOUT2
CBYP
NC
GND
Figure 4. Application circuit showing simultaneous user control of power supply and
sleep mode.
A1442
Power Derating
The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.) The package thermal resistance,
RJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die),
through all paths to the ambient air. Its primary component is the
effective thermal conductivity, K, of the printed circuit board,
including adjacent devices and traces. Radiation from the die
through the device case, RJC, is relatively small component of
RJA. Ambient air temperature, TA, and air motion are significant
external factors, damped by overmolding. The effect of varying
power levels (power dissipation, PD) can be estimated. The following formulas represent the fundamental relationships used to
estimate TJ at given levels of PD.
Given:
PD = VIN IIN ,
(1)
T = PD RJA , and
(2)
TJ = TA + T
(3)
VBATT
+
IDD
IL
VDD
System Logic
Control
CBYP
0.1 F
I/O
VOUT1
A1442
SLEEP
VOUT2
M
NC
GND
A1442
6
F
0.50
0.30
0.99 F
2.00 0.15
0.70
1.575
0.325
1.10
7X
SEATING
PLANE
0.08 C
C
C
0.38 0.02
0.50 BSC
+0.055
0.325 0.045
0.70 0.10
NN
YWW
0.25 0.05
1.25 0.05
G
6
1.10 0.10
For Reference Only, not for tooling use (refernce DWG-2856; similar to
JEDEC Type 1, MO-229X2BCD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
SON50P200X200X100-9M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
A1442
Revision History
Revision
Revision Date
Rev. 2
Description of Revision
Update Selection Guide