CCM Turn-on

Ebers Moll Model

Lecture 17: Bipolar Transistors

Lecture 19: Deviations from

Ideal
Punch Through
Base Width Modulation extreme
W=WB-XEB-XCB, WB=0
Avalanche Multiplication

Early Voltage and Forward

Transit Time

Accumulation

Depletion

Cut-off Frequency (fT = T/2)

BJT Performance Parameters:
Replace LE with the width of the
quasineutral emitter region
(WE) for narrow emitter
Emitter Efficiency:

Base Transport Factor:

Non-Ideal effects at low VEB

Non-Ideal effects at High VEB

High level injection

To maximize fT: Increase IC,

minimize CJ,BE and CJ,BC, minimize
re and rc, minimize F.
Switching Charactristics

Series Resistance
Current Crowding
High I, small A, higher resistivity
Gummel Numbers

Threshold Condition
When VG is increased to the
point where S reaches 2F, the
surface is said to be strongly
inverted

Common Base DC Current Gain:

Common Emitter DC I Gain:

Lecture 18: Ideal BJT Analysis

Carrier Diffusion Currents

Emitter Region Formulation

Base Transit Time

Time for minority carriers to
diffuse across the base

Emitter Band Gap Narrowing

Threshold Voltage

Emitter Region Solution:

Square Law Theory:

Linear: VD < VDSAT = VG - VTH

Bulk Charge Theory:

Linear: VD < VDSAT = (VG - VTH)/m
Saturation: VD VDSAT = (VG VTH)/m

Inversion Layer
Lecture 22: MOS Capacitor
MOS Cap Band Diagram
The barrier height for
conduction band electron flow is
3.1 eV.
The barrier height for valence
band hole flow is 4.8 eV
Applied Gate Voltage
Flat Band Condition

Where m = CD-m/Cox =1+ 3xo/WT

Body Effect
Total Charge Density
Channel Length Modulation
If L has an effect

Ideal MOS C Curve

Bulk Semiconductor Potential

Collector Region Formulation

Base Region Formulation

Threshold Voltage

Saturation: VD VDSAT = VG - VTH

High gain (DC>>1)

One-sided emitter junction
1, NE>>NB
Narrow Base
1, W<<LB
IC determined only by IB
W will not change drastically
with VCE(VCB) and NB>NC
Lecture 20: BJT CCM
Charge Control Model

Minority carrier concentrations

VGS > VTH: Source to channel

potential barrier to electron flow
is lowered
VDS > 0: Source to drain electron
flow via drift (IDS > 0).
VDS > VG - VTH: L increases, the
voltage applied across the
inversion layer is always
VDSAT = VGS VTH.
If L is comparable to L, then IDS
will increase slightly with
increasing VDS >VDSAT (channel
length modulation).
NMOSFET IV Characteristics
Channel Inversion Charge Density

C = QS/VG Qs = Qacc + Qdep + Qinv

Narrow Band Gap Base
Allows large DC even with
large NB for reducing base
resistance and increasing early
General Equations
voltage.
Lecture 21: Smallsignal Transient
Transconductance

Extrinsic Debye Length

Where (VDS-VDSAT) = L/L

PMOSFET
Holes flow from source to drain
Lower drain bias compared to
source
Note: VDS < 0 and IDS < 0
|IDS| increases with |VGS VTH|
and |VDS| (in the linear region)
VTH, NMOS = VTH, PMOS (VTH
symmetry)
PMOSFET IV Characteristics
Same Square Law and Bulk
Charge Theory equations as in
NMOSFET, but currents are
negative (IDS). Voltage conditions
become magnitude.
Small Signal Model

Lecture 24: MOS Transistor

Base Region Solution:

Input Resistance

N-type then P-type

Input Capacitance

Pinch-off
Cut-off frequency
Lecture 23: MOS C-V