Name : Sudarshan Mankad

Date of Birth : 15 Nov 1989

Contact Information
Phone : +91-9538850427
E-mail: sudarshan06@gmail.com
Objective
To become a key technical resource for an organisation, where I am able to explore my full potential, add to my
learning curve, as well as contribute effectively and efficiently to achieve organisational goals.
Education
B. Tech. (Bachelor of Technology) Electrical & Electronics (2007-2011), Dr.Ambedkar Institute of Technology,
Bangalore, India, a 4 year degree course.
M. Tech. (Master of Technology) VLSI Design and Embedded Systems (2011-2013),RNS Institute of
Technology, Bangalore, India, a 2 year degree course.
Advanced Diploma in ASIC Design ( RTL Verification) (2014-present), RV VLSI Design Center, Bangalore,
India.
About Me
I developed mobile applications for a year to acquire the knowledge and skills of a object oriented programmer.
I am perusing advanced diploma in ASIC design(RTL Verification) at RV VLSI, Bangalore. My main activities
and interest lies in Digital Design (RTL), Verification(SV/Verilog) with constrained random methodology
(eRM/UVM/OVM) and Synthesis.
My professional Career till date:
PROJECTS (VLSI Diploma): RTL Verification of the following using System Verilog & Verilog.
UART, Single port RAM, FIFO, SPI:
Design specification to Verification plan and architecture was extracted and a completely automated
testbench with constrained randomization methodology was developed using Verilog initially and later using
System Verilog. Maximum functional coverage and code coverage was achieved with the latter one (as Verilog
doesn't support functional coverage). Protocols were to be studied thoroughly and understood, which makes the
verification process efficient and easy.
PREVIOUS WORK EXPERIENCE:
Job: Mobile Application Design and Development Engineer.
Organization: Webrelational Media LLP, Bangalore, India.
Duration: 1 year.
ACADEMIC PROJECTS:
Vocal signal manipulation in mixed music environment using the concept of fundamental
freque1ncy(MATLAB) (Paper on the same was accepted by SARC-International Conference on Industrial
Electronics and Computer Science (SARC-ICIECS-2013)). 4-Channel Audio Mixer, Automatic Train Gate
System using HCS12 microcontroller, Design and Implementation of 8 Bit ALU Using Verilog(FPGA), Inter

Microcontroller communication using SPI protocol(HCS 12), Centralized control of lighting (PIC), Line
Follower(8051).
Skills
Specs to RTL coding, including VHDL and Verilog. Very efficient in converting specs to RTL,
supported by strong background in digital logic design, and extensive experience in producing high
quality RTLs
Verification: SoC verification using Verilog and System Verilog, writing testbenches, behavioural
models, automation of verification by self-testing test-benches

SOC verification with constrained random methodology (eRM/UVM/OVM).

Synthesis. Logic synthesis using Synopsys tools

STA : Using Synopsys PrimeTime.
C, C++ programming , Embedded C programming.
Unix shell scripting, Perl scripting: Some of my scripts save considerable manual work, thereby
reducing cycle time for development
Familiar with Back-End design flow, including PnR, layout, DRC, LVS using Cadences Diva and
Mentor Graphics Caliber
Knowledge of Microprocessor Architecture
CMOS circuit design
Tools:

Synopsys Design Analyzer, dc_shell for synthesis

Questasim for Simulation and verification
Xilinx for verilog simulation
Cadences Virtuso Editor for Layout
Nanosim: for Spice, and Verilog-spice co-simulation.
Mentor Graphics Model-Sim for VHDL/Verilog simulation
PrimeTime: for STA
Cadences Diva for DRC/LVS
Philips tools for DFT
Matlab for DSP (not proficient)
Xilinx tools for FPGA(not proficient)

Strengths
Highly innovative, Self-motivated, Continuous learning quest, Ability to work under pressure, Efficient.
References
Available on Request