User manual

Digital
Note: To perform all the operations in digital cadence design tool suite, please check that root
directory must contain folder named NCO containing rclabs followed by rtl and work. If
NCO folder is not present, copy it from another PC to the working PC.
Step1: To write Code

Open terminal and write gedit filename.vhd (for vhdl) and filename.v (for verilog).
New window will open, write code here and save it.
Copy this filename.vhd file in the rtl folder from path NCO/rclabs/rtl.

Note: If one has already written code in Xilinx, then copy the .vhd file from the
respective folder or one can copy the code in text file and change the extension from .txt
to .vhd. Copy this .vhd file to rtl folder.
Step2: To perform simulations

Type in terminal window

1. csh (enter)
2. source cshrc1 (enter)
3. nclaunch
New window will open named nclaunch

In the left hand side of the window, select the design by giving the desired path in
diroctory e.g. in /root/NCO/rclabs/rtl.
After selecting the filename.vhd
Go to Tools VHDL compiler ok
After compiling, open the worklib folder in the right side of the window, there
is filename like halfadder, select the file.
After selecting filename:
Go to Tools Elaboratorok
After compiling, open the snapshots folder in the right side of the window,
there is file named worklib.filename:behavioral like
worklib.halfadder:behavioral, select the file.
After selecting filename:
Go to Tools Simulatorok
A new window will open named Design Browser 1 SimVision
In the left hand side of the window named Design Browser under simulator select
the (WORKLIB:FILENAME(BEH)).
After selecting filename select the icon on the toolbar named send selected objects
to target waveform window.
A new window will open names Waveform 1 SimVision.

To force clock
1. Select the signal or input
2. Go to simulation deposit value.
3. Under deposit this value force value to 0 and set time to 0fs.
4. Then add a new row into the table of deposited value by clicking the
icon just right to the time window.
5. Under deposit this value force value to 0 and set time to 10fs.
6. Then again add a new row into the table of deposited value.
7. Under deposit this value force value to 1 and set time to 10fs.
Above mentioned clock is for clock of period 20fs, 10fs for 0 and 10fs for 1, one
can adjust the period here according to its requirement. After this select the Repeat
every and put value equal to the period of the clock like in above case set to 20fs and
then click ok.

Now, one can run the simulations by clicking the run icon on the toolbar.

Step3: To synthesize the code

To perform synthesize first one have to create two files i.e. constraint_filename.g
and rc_setup_filename.g in the work folder under /root/NCO/rclabs/work path.
e.g constraint_halfadder.g and rc_setup_halfadder e.g for halfadder.
These two files are already present in the work folder by some other name, the only
thing one has to do is to save as with its filename and make some changes within the
file according to ones code, as explained:
In constraint_filename.g:
Write the name of inputs and outputs as in the entity of the code, e.g for half
adder inputs are a,b and outputs are sum, carry, so write as
1. set_input_delay -max 1.0 [get_ports "a"] -clock [get_clocks "clk"]
2. set_input_delay -max 1.0 [get_ports "b"] -clock [get_clocks "clk"]
3. set_output_delay -max 1.0 [get_ports "sum"] -clock [get_clocks "clk"]
4. set_output_delay -max 1.0 [get_ports "carry"] -clock [get_clocks
"clk"]
Edit only the inputs and outputs as shown above, dont edit anything else.
In rc_setup_filename.g:
Edit at the following lines:
1. In line containing set DESIGN filename, write filename as set Design
halfadder.
2. In line containing set RTL_LIST filename.vhd, write filename as set
RTL_LIST halfadder.vhd.

3. In read_sdc ./constraints_filename.g, write filename as read_sdc

./constraints_halfadder.g as one has saved constraint _filename.g for the
same code as explained above.
4. In write_hdl > filename.vhd, write filename as write_hdl > halfadder.vhd.
5. In write_sdc > filename.sdc, write filename as write_sdc > halfadder.sdc.
Note: In case of structural style of modeling one has to copy all the files i.e. top module along
with components in the rtl folder in /root/NCO/rclabs/rtl. For example in half adder the top
module is halfadder.vhd and components are xorgate.vhd and andgate.vhd. In order to
synthesize structural code one has to save all the three codes in rtl folder.
Remaining all process is same except one point i.e. in rc_setup_filename.g there is
change in point no.2 as:
2.

In line containing set RTL_LIST filename.vhd, write filename as

set RTL_LIST [list \
xorgate.vhd\
andgate.vhd \
halfadder.vhd \
]

As shown above the RTL list contains all the .vhd files which are declared in the top module
as components. Hence list should include the top module along with components as shown
above.

After creating these two files namely constraint_filename.g and

rc_setup_filename.g successfully, go to terminal and type the following commands:
1. csh (enter)
2. source cshrc1 (enter)
3. cd NCO/rclabs/work (enter)
4. rc f rc_setup_filename.g (enter)

After that code will be synthesized successfully and if there is any error than it will be shown
in the window.
If the code is synthesized successfully then terminal window will appear as:
rc : />
one can write here the various types of report like:
rc : /> report power (enter) for power analysis
rc: / > report area (enter) for area analysis

rc: / > report timing (enter) for timing analysis

rc: / > report gates (enter) for gates analysis
rc: / > report qor (enter) for power, area and fanout, net analysis
After getting reports one should write exit (enter) to exit from rc command to the working
directory i.e NCO/rclabs/work. Further exit will take user to the root local host.

Step4: To make layout

Type in terminal window

csh (enter)
source cshrc1 (enter)
encounter
New window will open named encounter RTL-to-GDSII System

Import design as
1. Go to File Import design
New window will open
2. Insert file from the path /root/NCO/rclabs/work as filename.vhd
3. Assign top cell as auto assign
4. In LEF files select file all.lef from path /root/NCO/rclabs/lef
5. In max timing libraries select file fast.lib from path /root/NCO/rclabs/lib
6. In min timing libraries select file slow.lib from path /root/NCO/rclabs/lib
7. In timing constraint file select file as filename.sdc from path
/root/NCO/rclabs/work.
8. In same window go to advanced from basic and select power, add power nets
as Vdd and Ground nets as Vss.
9. Click ok
Go to floorplan Specify floorplan
New window will open
1. Set --core size by-- aspect ratioRatio (H/W): as 1
2. Set core to left, core to top, core to right and core to bottom all as 30
3. Set floorplan origin at center.
4. Click ok
Go to power power planningadd ring
New window will open
1. In ring configuration select layer as
Top- Metal5 H
Bottom- Metal5 H

Left- Metal6 V
Right- Metal6 V
2. Select offset as center in channel

Go to placement place standard cell

Select the physical view from the icon at the right side of screen just above the layer
control and floorplan view option.
Go to timing report timing
1. Select design stage as pre-CTS
2. Analysis type as setup
Go to clock synthesize clock tree
1. In clock specification file click Gen Spec
2. In cells list window select all files like BUF and click add to add
them in selected cells window and click apply and ok.
Go to timing report timing
3. Select design stage as post-CTS
4. Analysis type as setup
Go to timing report timing
5. Select design stage as post-CTS
6. Analysis type as hold
Go to route Nanorouteroute
New window will open click ok

Step5: To save file in GDSII format

Go to filesave GDS/OASIS
New window will open
Select output format as GDSII/stream and give the output file name and click ok.