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(Emitter-Coupled Pair)
I C1= I S evBE1 / vT
I C 2 = I S evBE 2 / vT
Case I:
If both VX and VY are less than
the reference voltage VR( at
least 120 mV), then Q1 and Q2
are cut off and QR is in active
mode.
This implies that;
VO1>VO2
An advantage of
ECL is its
complementary
outputs.
Case II:
If either Vx or Vy become greater
than VR then VO2>VO1
The OR logic is
at the V02 output
and NOR logic
is at the VO1
output
Three variations of
a 3-input ECL ORNOR Gate
For example:
In the ECL circuit shown in the Figure, If
either VX or VY=V+
then Q1 and Q2 would turn on and the
collector voltage Vo1 would decrease
below V+.
At this condition the base collector would then
become forward biased and transistor
switch into saturation region.
Emitter followers ECL circuit has been design
to overcome this problem.
7
on
Case I
ECL circuit
analysis
Case I
Case II
VE
10
Case II
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12
Example 17.4
1. Power Dissipation
The power dissipation of
standard ECL logic
circuit is given by,
PD=(iCxy+iCR+i5+i1+i3+i4)(0 V-)
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Noise Margin
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18
In some
applications, both
complementary
outputs may not be
required.
If for example OR
output is required,
then we can
eliminate resister
RC1.
IE =
VR VBE (on)
iCR
RE
19
Problem:The
Thelogic
logic00isisnot
notwell
welldefine
definebecause
becauseRREand
andRRC2may
mayvary
varyfrom
from
Problem:
E
C2
20
Onecircuit
circuitto
toanother
anotherduring
duringfabrication
fabricationprocess.
process.
One
1. Power Dissipation
PD=(iCxy+iCR+i5+i1+i3+i4)(0 V-)
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Example 17.4
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Noise Margin
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Case I:
If VX=VY=logic 1>VR
Under this condition Q1 and Q2 are
turn on and QR is off and logic 1
output voltage is: VOR=VCC
Case II: If VX=Vy=logic 0<VR
Under this condition, transistors Q1
and Q2 are off and QR is on, then,
IE =
VR VBE (on)
iCR
RE
Problem:The
Thelogic
logic00isisnot
notwell
welldefine
definebecause
becauseRREand
andRRC2may
mayvary
varyfrom
from
Problem:
E
C2
29
Onecircuit
circuitto
toanother
anotherduring
duringfabrication
fabricationprocess.
process.
One
30
The ECL circuits have very low noise margin (i. e. 0.23V). In order to
overcome this problem, TTL circuits have been introduced.
If VR is the average of
logic 1 and logic 0, then
output is compatible with
in input.
Power dissipation
when output is logic 0
Power dissipation
when output is logic 1
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VX
VY
NAND gate : 0
1
0
1
0
0
1
1
Vo
1
1
1
0
VO
Edge of conduction
QO(off)
VOH
Edge of saturation
VOL=
VCE(sat
34
VIL=1.4V
VIH= 1.5V
NAND gate : 0
1
0
1
VY
0
0
1
1
Vo
1
1
1
0
VO
Edge of conduction
QO(off)
VOH
Edge of saturation
VOL=
VCE(sat
35
VIL=1.4V
36
VIH= 1.5V
Problem 17.10:
Vx
NAND gate : 0
1
1
0
1
vy
0
vo
0
1
1
1
1
0
0.1)/4 = 1.23 mA
P=(i1 + iRC)VCC = (0.7V + 1.23)(5) = 9.65 mW
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TTL
DTL
Pull down resister RB is no longer necessary, since The 39
excess minority carrier in the baser of Qo use Q1 as a path
to ground
10
VB1 = VX + VBE(sat)
And the base current of Q1 is
NAND gate : 0
1
0
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
1
1
1
0
VO(sat)=Logic 0=0.1V
VO=VCC=Logic 1
NAND gate : 0
1
0
1
43
0
0
1
1
1
1
1
0
44
11
45
NAND gate : 0
1
0
1
0
0
1
1
46
1
1
1
0
47
Determine the currents i1, i2, i3, i4, iB2 and iB3 for the
following input conditions:
(i) Vx=Vy=0.1V
(ii) VX=Vy=5V
Sol:
Given that Vx=Vy=0.1V Q1 in saturation
VB1= Vx+VBE(sat)= 0.1+0.8=0.9V
i1= (VCC-VB1)/R1 = ( 5-0.9)/6 = 0.683 mA
Since Q2 and QO are in cutoff mode,
iB2 = i2 = i4 = iB 3= I 3= 0
ii) Given that VX=Vy=5V, which implies that Q1 is inverse
active mode and Q2 and Q3 would switch into
saturation mode.
VB1= VBE(sat)Qo+VBE(sat)Q2+VBC(on)Q1
VB1= 0.8+0.8+0.7=2.3V
i1+(VCC-VB1)/R1= (5-2.3)/6=0. 45mA=iB2
I2=(VCC-VC2)/R2={5-(0.8+0.1)]/6=2.05mA
I4=VBE(sat)/RB=0.8/1.5=0.533mA
iB3=(iB2+i2)-i4=0.45+2.05-0.533=1.97mA
i3=(VCC-Vo)/RC= (5.0.1)/2.2= 2.23mA
i3/iB3=2.23/1.97=1.13<
(b) For Q3:
For Q2:
i2/iB3=2.05/0.45=4.56<
This implies that Q3 and Q2 are in saturation.
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12
Totem pole
VC2
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50
Fanout
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Problem 17.21a
Given that F=50, R=0.1, VBE(on)=0.7V,
VBE(sat)=0.8V, and VCE(sat)=0.1V
Determine the power dissipation in the
circuits for (a) Vin=0.1V and (b) Vin=5V
VB1
i1
Solution: Vin=0.1V
Q1 must be conduct and in saturation mode
QS and QO remains in cutoff mode.
Under this condition,
VE
VC2
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58
Problem 17.21b
io
i1
i1=(Vcc-VB1)/RB=(5-2.3)/4=0.7mA
iE1=i1=(0.1)(0.7)=0.07mA
iE1
VB1
Vout
i1
io=(Vcc-Vout)/1=4.2mA
P=(i1+IEI+iO)(5) = 24.9mW
Problem
17.24 (a)
Vout= 0.8+0.1=O.9V
VB1=0.7+0.8+0.8=2.3V
Reverse current
VB1=VBC(on)Q1+VBE(sat)QS+VBE(sat)Qo
VB1
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Problem
17.24 (a)
iB1=iB3+(2-VB1)/RB1
Where iB3 = [Vcc - VEB(on)Q3] - VB1/RB2
iB3=[{2 - 0.7} - 0.9]/1 = 0.4mA
iB1=1.1 + 0.4 = 1.4mA
i)
ii)
Q3 is cutoff!!
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16
iC =
iB + iC
1
1+
iC =
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Problem
17.16
iB + iC
1
1+
+VCC
iC =
iB + iC
1
1+
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17
1)
2)
VCE3=VCE4+VBE3=0.4 + 0.7=1.1V
ii) All the resisters have been reduced
almost half the values used in the
standard circuit.
The above two new feature result in a
much shorter gate delay., which is the
order of 2 to 5ns, compared to 10 to 15
ns for standard TTL circuits.
3)
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70
In ALSTTL the
propagation delay time
was reduced down to
1.5ns, while still
maintaining the low
power dissipation. The
dimension of the
standard IC was also
reduced from 5m to
3m
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18
2) Input section:
The input diodes of the ALSTTL circuit
are replaced with emitter follower pnp
transistor.
The emitter follower configuration
reduces load current by a factor ,
and thus increases the fanout. In
addition, the emitter base junction of
the Q1 compensates for additional
base emitter drop of Q2.
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Problem 17.29a
Problem 17.29b
IR2=(VCC-VC2)/R2=(5.1.8)/R2 =0.065mA
VC3= VCE(Q3)+VBE(Q5)=0.4+0.7=1.1V
IR3= (VCC-VC3)/R3=(5-1.1)/1.5=0.26mA
P=VCC(IR1+iR2+iR3)=1.98mW
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VO(min)=VBE2(on)Q2,
because Q2 turn off at this value. Thus
low voltage is greater than 0, a
disadvantage.
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