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Overview
This document discusses a state machine implementation of the SPI (Serial Peripheral Interface) digital communication protocol using LabVIEW and the LabVIEW FPGA Module. This
implementation has two components: the SPI protocol implemented in LabVIEW FPGA and a LabVIEW host interface to communicate with the FPGA from a host PC or real-time controller. The
architecture allows for multiple SPI ports to be controlled from a single host program while still allowing customization of FPGA VI for other data acquisition and processing. The implementation
does not use any DMA (Direct Memory Access) channels, allowing use of the NI Scan Engine and RIO Scan Interface and other high speed/high volume data transfer between the FPGA and host
Table of Contents
1. Download SPI IP
2. SPI Digital Communication
3. FPGA Implementation
4. Bus Implementation
5. FPGA Multiplexer
6. Host Interface
7. Adding Multiple SPI Ports
8. Changing FPGA Targets
9. Conclusion
1. Download SPI IP
spi_example.zip
3. FPGA Implementation
The SPI bus in this document is implemented using LabVIEW FPGA to perform the bus mastering and clocking signals. A single-cycle timed loop (SCTL) is used to perform each step of
communication between the SPI master (LabVIEW FPGA VI) and up to 8 slave devices per port. Multiple ports can be created using the same FPGA VI and interface to a host program.
The bus is encapsulated in a higher level LabVIEW FPGA VI, which utilizes a state machine to perform intermediate communication between each SPI port and a host interface. This VI
synchronizes the host interface and SPI ports and multiplexes data sent from the host to a specified port.
4. Bus Implementation
State machines are used to execute a particular action and then determine which state to transition to. Because SPI has a specific order in which bus transitions happen, a state machine is a
good choice for implementing the protocol. Each state completes one portion of the communication then transitions to the next step in order.
When a command has been received by the SPI engine on the FPGA, one cycle of communication begins. Each byte is read from a VI-Scoped FIFO with data passed from the multiplexer and
stored as a boolean array on the FPGA.
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5. FPGA Multiplexer
To allow instantiation of multiple ports with minimal configuration, an intermediate FPGA VI is used to communicate between the SPI port VI and the host VI. This VI consists of a state machine
managing host/FPGA handshaking and multiplexing of data to the correct port.
The host is responsible for communicating which state the multiplexer should execute. The multiplexer sits in an idle state waiting for a start command from the host. When that start command is
received, the multiplexer writes the port the data is meant for to a global variable accessible by each port. Before beginning execution, each port VI checks if it is the designated port.
After setting the port information, the multiplexer checks the command sent from the host. If the command is Configure, CPOL, CPHA, CS, and the total number of bytes are written to global
variables to prepare for the next data transfer. If the command is Read/Write SPI, data received from the host is passed to a target-scoped FIFO accessible by each port. This data is transferred
from the target-scoped FIFO to the VI-Scoped FIFO of the intended port to be passed to the SPI bus in the Write and Read states.
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6. Host Interface
A LabVIEW interface to the SPI communication state machine has been created to facilitate simple transfer of data between a host PC or real-time controller and the FPGA multiplexer. With this
high-level API, multiple SPI ports can be instantiated alongside any other LabVIEW FPGA code needed for an application.
The API consists of two VIs: FPGA SPI_Configure and FPGA SPI_Read Write. FPGA SPI_Configure sets SCLK rate, CPOL, CPHA, CS, and the port to be used. This information is passed to
the FPGA multiplexer with the Configure command and stored in the FPGA global variable.
FPGA SPI_Read Write takes a total number of bits to be transferred and the port for which that data is designated. An array of U8 bytes is passed to the VI and an array of the same size is
returned. All of the handshaking and data transfer between the host and the FPGA is encapsulated in these VIs.
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9. Conclusion
The state machine implementation of the SPI protocol has been discussed, including the bus implementation, multiplexer behavior and usage of a host API. The attached code includes the FPGA
SPI bus and host API.
For more examples of using SPI with LabVIEW FPGA see SPI Bus communication Example Using LabVIEW FPGA.
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