STC11F02xx Application Note - V1.0

STC Technology Co., Ltd.

STC11F(L)02xx Family
Application Note
Edited By Peter Lin., 2008/09/05
V1.00
This document information is the intellectual property of STC Technology Co.,Ltd..
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STC Technology Co., Ltd. 1999 All right reserved.
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Contents
Selection Table ...................................................................................................................... 4
1 General .............................................................................................................................. 5
1.1 Pin Assignment ...................................................................................................................... 5
1.2 Special Function Registers (SFRs) ........................................................................................ 6
1.3 Flash Memory Configuration ................................................................................................ 10
2 I/O Ports ........................................................................................................................... 11
2.1 Port Configurations .............................................................................................................. 11
2.1.1 Quasi-bidirectional..................................................................................................... 11
2.1.2 Open-Drain Output .................................................................................................... 13
2.1.3 Input-Only (Hi-Z)........................................................................................................ 13
2.1.4 Push-Pull Output ....................................................................................................... 13
2.2 Maximum Ratings for Port Outputs ...................................................................................... 14
3 On-chip expanded RAM (XRAM).................................................................................... 15
4 Timer 0 and Timer 1 ........................................................................................................ 16
4.1 Mode 0 ................................................................................................................................. 16
4.2 Mode 1 ................................................................................................................................. 16
4.3 Mode 2 ................................................................................................................................. 17
4.4 Mode 3 ................................................................................................................................. 17
5 Serial Port ........................................................................................................................ 18
5.1 Baudrate Setting .................................................................................................................. 18
5.2 Enhanced Feature: Frame Error Detection .......................................................................... 19
5.3 Enhanced Feature: Automatic Address Recognition ........................................................... 20
8 Wake-Up Timer (WKT) .................................................................................................... 22
9 Interrupt ........................................................................................................................... 23
9.1 Interrupt Priority.................................................................................................................... 25
9.2 Note on Interrupt during ISP/IAP.......................................................................................... 26
11 In System Programming (ISP) ..................................................................................... 30
11.1 Boot from ISP-memory to run ISP code .......................................................................... 31
11.2 Operation Flow of IAP ........................................................................................................ 32
11.3 Demo of the ISP code...................................................................................................... 35
11.4 Note on In-System-Programming....................................................................................... 36
12 In Application Programming (IAP)............................................................................... 37
12.1 IAP-memory Address Range ............................................................................................. 37
12.2 How to update the non-volatile data by IAP ....................................................................... 37
12.3 IAP-memory Start Address ................................................................................................ 38
12.3.1 STC11C(L)xx IAP-memory...................................................................................... 38
13 Programmable CPU Clock ........................................................................................... 40
14 Wake-up from Power-down by External Interrupt ...................................................... 41
15 Power-On Reset and Low Voltage Detection ............................................................. 42
15.1 Power-ON Reset ................................................................................................................ 42
15.2 Low Voltage Detection ....................................................................................................... 42
16 Built-in Oscillator .......................................................................................................... 43
17 XTAL Oscillating and Reset Circuitry ......................................................................... 44
17.1 XTAL Oscillating................................................................................................................. 44
17.2 Reset Circuitry.................................................................................................................... 44
18 Install ISP Tooling ......................................................................................................... 45
19 Instruction Set ............................................................................................................... 49
19.1 Arithmetic Operations......................................................................................................... 50
19.2 Logic Operations ................................................................................................................ 51
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19.3 Data Transfer ..................................................................................................................... 52
19.4 Boolean Variable Manipulation .......................................................................................... 53
19.5 Program and Machine Control ........................................................................................... 54
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Selection Table
STC11XFaaE
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
RTC
Internal RC **
(6Mhzs+/15%)
Low Voltage
Detector(LVD)
EEPROM
KBytes
WDT
15bits
Wake-Up from
WKT Timer
Independently
Configured I/O
1
1
1
1
1
1
1
1
1
1
ISP/IAP
Function
2
2
2
2
2
2
2
2
2
2
UART
256
256
256
256
256
256
256
256
256
256
Timer/Counter
T0/T1
1
2
3
4
5
1
2
3
4
5
SRAM
Bytes
5.0
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
3.3
AP ROM
KBytes
Operating
Voltage(V)
P art No
11F/Laa.
F01E
F02E
F03E
F04E
F05E
L01E
L02E
L03E
L04E
L05E
note: x F : 3.5V ~ 5.5V L 2.6V ~ 3.6V
Na
Na
Na
Na
Na
Na
Na
Na
Na
Na
** for test only
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1 General
1.1 Pin Assignment
STC11F(L)xx
RST/P3.6
/INT/RXD/P3.0
16
TXD/P3.1
STC11Fxx
PDIP/SOP-16
XTAL2
XTAL1
/INT1/P3.3
P1.1
P1.0
/INT/CLKOUT/T0/P3.4
GND
RST/P3.6
/INT/RXD/P3.0
VCC
P1.7/TXD
P1.6/RXD/INT
P1.5
P1.2
P3.7
18
TXD/P3.1
XTAL2
STC11Fxx
PDIP/SOP-18
XTAL1
/INT1/P3.3
VCC
P1.7/TXD
P1.6/RXD/INT
P1.5
P1.4
P1.2
P1.1
/INT/CLKOUT0/T0/P3.4
P1.0
GND
RST/P3.6
/INT/RXD/P3.0
P3.7
20
TXD/P3.1
XTAL2
STC11Fxx
PDIP/SOP-20
XTAL1
VCC
P1.7/TXD
P1.6/RXD/INT
P1.5
P1.4
/INT0/P3.2
P1.3
/INT1/P3.3
P1.2
GND
P1.0
P3.7
P1.1
10
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1.2 Special Function Registers (SFRs)
STC11F(L)xx SFRs
SYMBOL
ACC*
B*
PSW*
DESCRIPTION
ADDRESS
Accumulator
E0H
B Register
F0H
BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION
MSB
LSB
RESET
VALUE
00H
00H
D7H
CY
D6H
AC
D5H
F0
D4H
RS1
D3H
RS0
D2H
OV
D1H
-
D0H
P
Program Status Word
D0H
Stack Pointer
81H
07H
DPH
Data Pointer High
83H
00H
DPL
Data Pointer Low
82H
SP
000000x0B
00H
97H
P1.7
96H
P1.6
95H
P1.5
94H
P1.4
93H
P1.3
92H
P1.2
91H
P1.1
90H
P1.0
B7H
P3.7
BFH
AFH
EA
B6H
BEH
B5H
P3.5
BDH
AEH
ADH
B4H
P3.4
BCH
PS
ACH
ES
B3H
P3.3
BBH
PT1
ABH
ET1
B2H
P3.2
BAH
PX1
AAH
EX1
B1H
P3.1
B9H
PT0
A9H
ET0
B0H
P3.0
B8H
PX0
A8H
EX0
P1*
Port 1
90H
P3*
Port 3
B0H
IP*
Interrupt Priority
B8H
IE*
Interrupt Enable
A8H
Timer Mode
89H
GATE
C/-T
M1
M0
GATE
C/-T
M1
M0
00H
Timer Control
88H
8FH
TF1
8EH
TR1
8DH
TF0
8CH
TR0
8BH
IE1
8AH
IT1
89H
IE0
88H
IT0
00H
TH0
Timer 1 High
8CH
00H
TL0
Timer 0 Low
8AH
00H
TH1
Timer 1 High
8DH
00H
TL1
Timer 0 Low
8BH
TMOD
TCON*
SCON*
Serial Port Control
98H
SBUF
Serial Data Buffer
99H
PCON
Power Control
87H
FFH
1x111111B
x0000000B
00H
00H
9FH
SM0/FE
9EH
SM1
9DH
SM2
9CH
REN
9BH
TB8
9AH
RB8
99H
TI
98H
RI
00H
xxH
SMOD
SMOD0
LVDF
8EH
T0X12
T1X12
UARTM0
X6
C7H
POF
GF1
GF0
PD
IDL
00xx0000B
000000xxB
CKS1
CKS0
xxxxx000B
The following SFRs are new added.

AUXR
Auxiliary Register
CLK_DIV System Clock Divider

SADEN
Slave Address Mask
B9H
SADDR
Slave Address
A9H
WDT_
CONTR
WKTCL
WKTCH
Watch-dog Timer
Wake-Up Control
Register Low
Wake-Up Timer
Control Register High
E1H
CKS2
00H
00H
WDT_
FLAG
EN_
WDT
CLR_
WDT
IDL_
WDT
PS2
PS1
PS0
AAH
0x000000B
0x000000B
ABH
WKTEN
0xxx0000B
P1M0
Port1 Mode Register 0
92H
P1M0.7
P1M0.6
P1M0.5
P1M0.4
P1M0.3
P1M0.2
P1M0.1
P1M0.0
00H
P1M1
91H
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
00H
P3M0
B2H
P3M0.7
P3M0.5
P3M0.4
P3M0.3
P3M0.2
P3M0.1
P3M0.0
00H
P3M1
B1H
P3M1.7
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
00H
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(Continued)
SYMBOL
CCON*
CMOD
ISP_
CONTR
DESCRIPTION
PCA Counter
Control Register
PCA Counter
Mode Register
ISP Control Register
ISP_CMD ISP Flash Mode Table

ISP_
ADDRH
ISP_
ADDRL
ISP Flash Address

High
ISP Flash Address
Low
ADDRESS
MSB
LSB
RESET
VALUE
D8H
DFH
CF
DEH
CR
DDH
-
DCH
-
DBH
-
DAH
-
D9H
CCF1
D8H
CCF0
00xxxx00B
D9H
CIDL
CPS2
CPS1
ECF
0xxxx000B
E7H
ISPEN
SWBS
SWRST
CFAIL
ICK2
ICK1
ICK0
0000x000B
E5H
MS1
MS0
xxxxx000B
E3H
00H
E4H
00H
ISP_DATA ISP Flash Data
E2H
00H
ISP Sequential
ISP_TRIG
Command
E6H
xxH
Notes:
*: bit addressable
-: reserved bit
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STC11F/Lxx SFRs
SYMBOL
ACC*
DESCRIPTION
ADDRESS
MSB
LSB
RESET
VALUE
Accumulator
E0H
00H
B Register
F0H
00H
Program Status Word
D0H
Stack Pointer
81H
07H
DPH
Data Pointer High
83H
00H
DPL
Data Pointer Low
82H
00H
P0*
Port 0
80H
P1*
Port 1
90H
P3*
Port 3
B0H
IP*
Interrupt Priority
B8H
IE*
Interrupt Enable
A8H
TMOD
Timer Mode
TCON*
B*
PSW*
SP
D7H
CY
D6H
AC
D5H
F0
87H
P0.7
97H
P1.7
B7H
P3.7
86H
P0.6
96H
P1.6
B6H
-
BFH
AFH
BEH
85H
P0.5
95H
P1.5
B5H
P3.5
T1
BDH
AEH
ADH
89H
GATE
C/-T
Timer Control
88H
8FH
TF1
8EH
TR1
TH0
Timer 1 High
8CH
D4H
RS1
D3H
RS0
D2H
OV
D1H
-
D0H
P
000000x0B
84H
P0.4
94H
P1.4
B4H
P3.4
T0
BCH
PS
ACH
ES
83H
P0.3
93H
P1.3
B3H
P3.3
/INT1
BBH
PT1
ABH
ET1
82H
P0.2
92H
P1.2
B2H
P3.2
/INT0
BAH
PX1
AAH
EX1
81H
P0.1
91H
P1.1
B1H
P3.1
TXD
B9H
PT0
A9H
ET0
80H
P0.0
90H
P1.0
B0H
P3.0
RXD
B8H
PX0
A8H
EX0
1x111111B
M1
M0
GATE
C/-T
M1
M0
00H
8DH
TF0
8CH
TR0
8BH
IE1
8AH
IT1
89H
IE0
88H
IT0
00H
FFH
FFH
x0000000B
00H
00H
TL0
Timer 0 Low
8AH
00H
TH1
Timer 1 High
8DH
00H
TL1
Timer 0 Low
8BH
SCON*
Serial Port Control
98H
SBUF
Serial Data Buffer
99H
PCON
Power Control
87H
00H
9FH
SM0/FE
9EH
SM1
9DH
SM2
9CH
REN
9BH
TB8
9AH
RB8
99H
TI
98H
RI
00H
SMOD
SMOD0
LVF
POF
GF1
GF0
PD
IDL
00xx0000B
T1X12
ESPI
ELVD
000000xxB
xxH
The following SFRs are new added.

AUXR
Auxiliary Register
8EH
T0X12
AUXR1
Auxiliary Register-1
A2H
UART_P1
C7H
CLK_DIV System Clock Divider
URM0X6 EADCI
000000xxB
-
CKS2
CKS1
CKS0
xxxxx000B
SADEN
Slave Address Mask
B9H
00H
SADDR
Slave Address
A9H
00H
WDT_
CONTR
Watch-dog Timer
E1H
WDT_FL
AG
EN_
WDT
CLR_
WDT
IDL_
WDT
PS2
PS1
PS0
0x000000B
P1M0
91H
P1M0.7
P1M0.6
P1M0.5
P1M0.4
P1M0.3
P1M0.2
P1M0.1
P1M0.0
00H
P1M1
92H
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
00H
P3M0
B1H
P3M0.7
P3M0.5
P3M0.4
P3M0.3
P3M0.2
P3M0.1
P3M0.0
00H
P3M1
B2H
P3M1.7
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
00H
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(Continued)
ISP_
CONTR
ISP Control Register
ISP Flash Mode

ISP_CMD
Table
ISP_
ISP Flash Address
ADDRH High
ISP_
ISP Flash Address
ADDRL Low
E7H
ISPEN
SWBS
SWRST
CFAIL
ICK2
ICK1
ICK0
0000x000B
E5H
MS1
MS0
xxxxx000B
E3H
00H
E4H
00H
ISP_DATA ISP Flash Data
E2H
00H
ISP Sequential
ISP_TRIG
Command
E6H
xxH
Notes:
*: bit addressable
-: reserved bit
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1.3 Flash Memory Configuration
STC11F/Lxx
0000 xxxx: =
Users Application
xxxx yyyy :=
Memory for In-ApplicationProgramming data
yyyy zzzz :=
Memory for In-SystemProgramming code
AP
Memory
ISP
IAP
Memory
Memor
y
zzzz
yyyy
xxxx
0000
Address Space for STC11F/Lxx embedded Flash memory
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2 I/O Ports
The STC11F/Lxx has four I/O ports: P1,and P3. The exact number of I/O pins available depends on their
package type .
2.1 Port Configurations

All these port pins can be individually and independently configured to one of four modes: quasi-bidirectional
(standard 8051 I/O port), push-pull output, open-drain output or input-only (high-impedance). All port pins are in
the quasi-bidirectional mode after power-up or reset. Each port pin has a Schmitt-triggered input to improve
input noise rejection. Each port has two configuration registers to configure the I/O type for each port pin (see
the following Table).
Table : Port Configuration Settings
PxM1.y
PxM0.y
Port Mode
Quasi-bidirectional
Push-Pull Output
Input-Only (High Impedance, Hi-Z)
Open-Drain Output
Where x=0, 1, 2, or 3, and y=0~7. Registers PxM0 and PxM1 are described as follows.
P1M0 (Port1 Mode Register 0)
7
6
5
4
P1M0.7 P1M0.6 P1M0.5 P1M0.4
3
P1M0.3
2
P1M0.2
1
P1M0.1
0
P1M0.0

7
6
5
4
P1M1.7 P1M1.6 P1M1.5 P1M1.4
3
P1M1.3
2
P1M1.2
1
P1M1.1
0
P1M1.0

7
6
5
4
P3M0.7
P3M0.5 P3M0.4
3
P3M0.3
2
P3M0.2
1
P3M0.1
0
P3M0.0

7
6
5
4
P3M1.7
P3M1.5 P3M1.4
3
P3M1.3
2
P3M1.2
1
P3M1.1
0
P3M1.0
2.1.1 Quasi-bidirectional
Port pins in quasi-bidirectional mode are similar to the standard 8051 port pins. A quasi-bidirectional port can be
used as an input and output without the need to reconfigure the port. This is possible because when the port
outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin outputs low,
it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional
output that serve different purposes.
One of these pull-ups, called the very weak pull-up, is turned on whenever the port register for the pin contains
a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.
A second pull-up, called the weak pull-up, is turned on when the port register for the pin contains a logic 1
and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-
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bidirectional pin that is outputting a 1. If this pin is pulled low by the external device, this weak pull-up turns off,
and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external
device has to sink enough current to over-power the weak pull-up and pull the port pin below its input threshold
voltage.
The third pull-up is referred to as the strong pull-up. This pull-up is used to speed up low-to-high transitions on
a quasi-bidirectional port pin when the port register changes from a logic 0 to a logic 1. When this occurs, the
strong pull-up turns on for two CPU clocks, quickly pulling the port pin high.
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2.1.2 Open-Drain Output
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin
when the port register contains a logic 0. To use this configuration in application, a port pin must have an
external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasibidirectional mode. In addition, the input path of the port pin in this configuration is also the same as quasibidirectional mode.
2.1.3 Input-Only (Hi-Z)

The input-only configuration is a Schmitt-triggered input without any pull-up resistors on the pin.
2.1.4 Push-Pull Output

The push-pull output configuration has the same pull-down structure as both the open-drain and the quasibidirectional output modes, but provides a continuous strong pull-up when the port register contains a logic 1.
The push-pull mode may be used when more source current is needed from a port output. In addition, the input
path of the port pin in this configuration is also the same as quasi-bidirection mode.
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2.2 Maximum Ratings for Port Outputs
While port pins function as outputs (which can source or sink a current), to prevent the device from being
permanently damaged, users should take care the total current not more than 40mA for sourcing or sinking
regardless of a 3.3V device or a 5V device. That means that the device can source total 40mA and sink total
40mA at the same time without causing any damage to itself.
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3 On-chip expanded RAM (XRAM)
In addition to the standard 256 bytes of internal RAM, the STC11F/Lxx has on-chip 256 bytes of expanded RAM
(XRAM). User can use MOVX @Ri or MOVX @DPTR to access them. Since these MOVX instructions are
modified for XRAM accessing, the I/O status of P0, P2 and P3.7 (/RD) are not changed while these instructions
are executed.
For KEIL-C51 compiler, to assign the variables to be located at XRAM, the pdata or xdata definition should
be used. After being compiled, the variables declared by pdata and xdata will become the memories
accessed by MOVX @Ri and MOVX @DPTR, respectively. Thus the STC11F/Lxx hardware can access
them correctly. See the following descriptions, which is obtained from Keil Software Cx51 Compiler Users
Guide.
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4 Timer 0 and Timer 1
After power-up or reset, the default function and operation of Timer 0 and Timer 1 is fully compatible with the
standard 8051 MCU. The only difference is that besides Fosc/12 the user can select an alternate clock source
direct from Fosc. The bit-7 and bit-6 in AUXR provide this selection.
AUXR (Auxiliary Register)
7
6
5
T0X12
T1X12 URM0X6
1
-
0
-
T0X12: Timer 0 clock source select. Set to select Fosc as the clock source, and clear to select Fosc/12.
Note:
Both these two bits are 0 after power-up or reset, and thus select Fosc/12 as the clock source by default, like the
standard 8051 does.
The following figures show the selection of alternate clock source for Timer 0 and Timer1.
4.1 Mode 0
4.2 Mode 1
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4.3 Mode 2
4.4 Mode 3
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5 Serial Port
5.1 Baudrate Setting
All the four operation modes of the serial port are the same as those of the standard 8051 except the baudrate
setting. The bit-6 and bit-5 in AUXR provide a new option for the baudrate setting, as listed below.
Table: Baudrate Setting
Serial Port Mode
Compatible to standard 8051

Baudrate = Fosc/12
Baudrate = Fosc/2
if AUXR.5 (URM0X6) is 0
if AUXR.5 (URM0X6) is 1
Baudrate = (2SMOD/32) x Fosc/[12x(256-TH1)]
Baudrate = (2SMOD/32) x Fosc/(256-TH1)
if AUXR.6 (T1X12) is 0
if AUXR.6 (T1X12) is 1
Baudrate = (2SMOD/64) x Fosc
Mode 0
Mode 1 & 3
Mode 2
New option

7
6
5
T0X12
T1X12 URM0X6
1
-
0
-
URM0X6: Serial Port mode 0 baudrate select.
Note:
The T0X12 and T1X12 bits are 0 after any reset, it is compatible to the standard 8051 by default.
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5.2 Enhanced Feature: Frame Error Detection
While the SMOD0 bit (in PCON, bit 6) is set, the hardware will set the FE bit (SCON.7) when an invalid stop bit
is detected. The FE bit is not cleared by valid frames but should be cleared by software.
SCON (Serial Port Control Register)
7
6
5
4
SM0/FE
SM1
SM2
REN
3
TB8
2
RB8
1
TI
0
RI
SM0/FE:
SM0: Serial Port Mode bit0 (while SMOD0=0).
FE: Frame Error bit (while SMOD0=1).
PCON (Power Control Register)
7
6
5
4
SMOD SMOD0
LVF
POF
3
GF1
2
GF0
1
PD
0
IDL
SMOD0: Cleared to let SCON.7 as SM0, and set to let SCON.7 as FE.
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5.3 Enhanced Feature: Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial
bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead
by eliminating the need for the software to examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive
Interrupt flag (RI) will be automatically set when the received byte contains either the Given address or the
Broadcast address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received
information is an address and not data. Automatic address recognition is shown in the following figure.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information
received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast
address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more
slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the
Broadcast address. Two special Function Registers are used to define the slaves address, SADDR, and the
address mask, SADEN.
SADEN is used to define which bits in the SADDR are to be used and which bits are dont care. The SADEN
mask can be logically ANDed with the SADDR to create the Given address which the master will use for
addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while
excluding others.
The following examples will help to show the versatility of this scheme:
Slave 0
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00X0
Slave 1
SADDR = 1100 0000
SADEN = 1111 1110
Given = 1100 000X
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves.
Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique
address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would
be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an
address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100
0000.
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
Slave 0
SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
Slave 1
SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
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Slave 2
SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that
bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely
addressed by 1110 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves
0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this
result are trended as dont-cares. In most cases, interpreting the dont-cares as ones, the broadcast address will
be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a
given address of all dont cares as well as a Broadcast address of all dont cares. This effectively disables the
Automatic Addressing mode and allows the micro-controller to use standard 80C51 type UART drivers which do
not make use of this feature.
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8 Wake-Up Timer (WKT)
STC11F/Lxx have a built-in Wake-Up Timer. The WKT is intended as a recovery method in situations where
the CPU may be subjected to software upset. The WKT consists of a 12-bit[4096 Count] free-running counter,
an internal 560us clock source and a control register (WKTCH). To enable the WKT, users must set WKTEN bit
(WKTCH.7). When the WKT is enabled, the counter will increment one by an interval of (12 x Prescaler / Fosc).
During power-down and WKTCH.7 is enabled( via a STC-ISP-Programmer/Writer).When the WKT counter is
overflows, the MCU will be wake up itself.
SFR: WKTCL
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
SFR: WKTCH
Bit-7
WKTEN
Bit-6
--
Bit-5
--
Bit-4
--
Bit-3
Bit-2
Bit-1
Bit-0
For example:
WKTCH[3:0],WKTCL[7:0] = 1
WKTCH[3:0],WKTCL[7:0] = 10
WKTCH[3:0],WKTCL[7:0] = 100
WKTCH[3:0],WKTCL[7:0] = 1000
WKTCH[3:0],WKTCL[7:0] = 4096
=> 560us X 1
= 560us
=> 560us X 10 = 5.60ms
=> 560us X 100 = 56.0ms
=> 560us X 1000 = 5.60ms
=> 560us X 4096 = 2.3S
WKT Block Diagram

Clock source:
Internal 560us
12-bit counter
Chip Wake-Up
when overflow
: in Power Down mode

WKTCH[3:0]
WKTCL[7:0]
WKTEN
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9 Interrupt
The STC11F/Lxx have 6 interrupt sources with 7 vectors used, as shown in the following table.
Table : Interrupt Table
Source
Request Bits
Polling Priority
Vector Address
INT0
IE0
(highest priority)
0003H
Timer 0
TF0
000BH
INT1
IE1
0013H
Timer1
TF1
001BH
Serial Port
RI+TI
0023H
Low Voltage Detect
LVDF
(lowest priority)
0033H
IE (Interrupt Enable Register)

7
6
5
EA
ELVD
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
EA: Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
ELVD: Enable Low Voltage Detector.
ES: Serial Port interrupt enable bit.
ET1: Timer 1 interrupt enable bit.
EX1: External interrupt 1 enable bit.
ET0: Timer 0 interrupt enable bit.
EX0: External interrupt 0 enable bit.
IP (Interrupt Priority Register)

7
6
5
PLVD
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
PS: Serial Port interrupt priority bit.

PT1: Timer 1 interrupt priority bit.
PX1: External interrupt 1 priority bit.
PT0: Timer 0 interrupt priority bit.
PX0: External interrupt 0 priority bit.
PLVD: Low Voltage Detector interrupt priority bit
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7
6
5
T0X12
T1X12 URM0X6
1
-
0
-
T0X12: = T0 clock source selector,

T1X12: =T1 clock source selector.
URM0X6: = Baud rate selector of UART while it is working under Mode-0.
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9.1 Interrupt Priority
There are 6 interrupt sources available in STC11Fxx. Each interrupt source can be
individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register
also contains a global disable bit (EA), which can be cleared to disable all interrupts at once.
One is located in SFR named IP register. Higher-priority interrupt will be interrupted by lowerpriority interrupt request, an internal polling sequence determine which request is serviced.
The following table shows the internal polling sequence in the same priority level and the
interrupt vector address.
Source
External interrupt 0
Timer 0
External interrupt 1
Timer1
Serial Port
Low Voltage interrupt
Vector address
03H
0BH
13H
1BH
23H
33H
Priority within level

0 (highest)
1
2
3
4
6
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9.2 Note on Interrupt during ISP/IAP
During ISP/IAP, the CPU halts for a while for internal ISP/IAP processing. At this time, the interrupt will queue
up for being serviced if the interrupt is enabled previously. Once the ISP/IAP is complete, the CPU continues
running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active. Users,
however, should be aware of the following:
(1) Any interrupt can not be serviced in time during the CPU halts for ISP/IAP processing.
(2) The low-level triggered external interrupts, /INT0 and /INT1, should keep active until the ISP/IAP is
complete, or they will be neglected.
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10 One-time Enabled Watchdog Timer (WDT)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset.
The WDT consists of a 15-bit free-running counter, an 8-bit prescaler and a control register (WDT_CONTR). To
enable the WDT, users must set ENW bit (WDTCR.5). When the WDT is enabled, the counter will increment
one by an interval of (12 x Prescaler / Fosc). When WDT is enabled, the user needs to clear it by writing 1 to
the CLR_WDT bit (WDT_CONTR.4) before WDT overflows. When WDT overflows, the MCU will reset itself and
re-start to run.
Why is the WDT called One-time Enabled? It is because: Once the WDT is enabled, there is no way to disable
it except power-on reset. The WDTCR register will keep the previous programmed value unchanged after
hardware (RST-pin) reset, software reset and WDT reset. For example, if the WDTCR is 0x2D, it still keeps at
0x2D rather than 0x00 after these resets. Only power-on reset can initialize it to 0x00.
WDT_CONTR (Watch-Dog-Timer Control Register)
7
6
5
4
3
WDT_FLAG
EN_WDT CLR_WDTW IDL_WDT
2
PS2
1
PS1
0
PS0
Note: This is a Write-only register.
WDT_FLAG: When WDT overflows, this bit is set by H/W. It should be cleared by software.
EN_WDT: Set to enable WDT. (Note: Once set, it can only be cleared by power-on reset.)
CLR_WDT: Writing 1 to this bit will clear WDT. (Note: It has no need to be cleared by writing 0.)
IDL_WDT: Set this bit to let WDT keep counting while the MCU is in the Idle mode.
PS2~PS1: Used to determine the prescaler value, as shown below.
PS2 PS1 PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Prescaler value
2
4
8
16
32
64
128
256
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1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
8-bit prescalar
15-bit timer
Fosc/12
IDLE
WDT_
FLAG
EN_W
DT
CLR_
WDT
IDL_
WDT
PS2 PS1
PS0
WDTCR Register
WDT overflow period

The WDT overflow period is determined by the formula:
215 x (12 x Prescaler / Fosc).
The following Table shows the WDT overflow period for MCU running at 6MHz and 12MHz. The period is the
maximum interval for the user to clear the WDT to prevent from chip reset.
Table: WDT Overflow Period at Fosc = 6MHz & 12MHz
PS2 PS1 PS0
Prescaler value
Fosc=6MHz
Fosc=12MHz
131.072 ms
65.536 ms
262.144 ms
131.072 ms
524.288 ms
262.144 ms
16
1.048 s
524.288 ms
32
2.097 s
1.048 s
64
4.194 s
2.097 s
128
8.389 s
4.194 s
256
16.778 s
8.389 s
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Sample code for WDT
Condition: MCU runs at 6MHz
Target: WDT Overflow Period = 1.048 seconds
WDTCR_buf DATA
30h
;declare a buffer for WDT_CONTR register

;(because WDT_CONTR is a Write-only register)
MOV
WDTCR_buf,#00h
;clear buffer for WDT_CONTR register
ANL
ORL
MOV
WDTCR_buf,#0F8h ;(PS2,PS1,PS0)=(0,1,1), prescaler=16

WDTCR_buf,#03h ;@Fosc=6MHz, WDT_Overflow_Period=1.048s
WDT_CONTR,WDTCR_buf ;
ORL
MOV
WDTCR_buf,#20h ;enable WDT

WDT_CONTR,WDTCR_buf ;write to WDTCR register
start:
;...
;...
main_loop:
ORL
MOV
;...
;...
JMP
ANL
MOV
WDTCR_buf,#10h ;clear WDT

WDT_CONTR,WDTCR_buf ;
main_loop
WDTCR_buf,#0DFh ;disable WDT
WDTCR,WDTCR_buf ;
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11 In System Programming (ISP)
(First, please refer to Section 1.3 for Flash Memory Configuration.)
The Flash program memory supports both parallel programming and serial In-System Programming (ISP).
Parallel programming mode offers high-speed programming. ISP allows a device to be reprogrammed in the
end product under software control. The capability to field update the application firmware makes a wide range
of applications possible. Several SFRs are related to ISP:
IAP_ADDRH: ISP Flash address high register
IAP_FADDRL: ISP Flash address low register
IAP_DATA: ISP Flash data register
IAP_TRIG: ISP sequential command register (filled sequentially with 0x46h then 0xB9h to trigger ISP operation)
IAP_CONTR (ISP Control Register)
7
6
5
4
ISPEN SWBS SWRST CFAIL
3
-
2
ICK2
1
ICK1
0
ICK0
ISPEN: Set to enable ISP function.

SWBS: Software boot select. Set/Clear to select ISP-/AP-memory to boot from after software reset.
SWRST: Write 1 to trigger software reset.
CFAIL: ISP fail flag. It is set by H/W if something error during ISP processing, and should be cleared by S/W.
ICK2-0: Select ISP timing. (Refer to the following table for their setting in several Fosc ranges.)
IAP Programming Time Setting
Fosc
ICK2 ICK1 ICK0
30 ~ 24 MHz
24 ~ 20 MHz
20 ~ 12 MHz
12 ~ 6 MHz
6 ~ 3MHz
3 ~ 2MHz
2 ~ 1MHz
< 1MHz
IAP_CMD (ISP Mode Register)

7
6
5
4
-
3
-
2
-
1
MS1
0
MS0
ISP Mode Select Table

MS1
MS0
ISP Mode
Standby
Read
Byte Program
Page Erase
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11.1 Boot from ISP-memory to run ISP code
To run the ISP code, the CPU should boot from the ISP-memory. By means of the following two methods, the
CPU can boot from the ISP-memory.
** Short P1.0 and P1.1 to ground, then power on. **
Method 1: Directly Boot from ISP-memory (while HWBS is enabled)

Start
Power on or H/W reset (RST-pin)

(while PIN_EN=1 and ISP-memory exists)
Now,
CPU will boot from AP-memory,
and run "Application code".
Check the user-defined

ISP condition, do ISP?
NO
YES
SWBS=1 (select boot from ISP-memory)

SWRST=1 (trigger S/W reset)
Run "Application code"

normally
...
...
Now,
CPU will re-boot from ISP-memory,
and run "ISP code".
ISPEN=1 (enable ISP function),

and initialize ISP_CONTR[2:0]
Do ISP programming
to update the "Application code"
...
...
End
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11.2 Operation Flow of IAP
The following figures show the flow chart for the various ISP modes used in the ISP code for ISP processing.
Flow Chart for Page Erase
IAP_CMD xxxxx011B
IAP_CONTR 100xx010B
IAP_ADDRH (page address high byte)
IAP_ADDRL (page address low byte)
IAP_TRIG 46h
IAP_TRIG B9h
(CPU progressing will be hold here )
(CPU continues)
/* choice page-erasing command */

/* set IAPEN=1 to enable flash change.
set WAIT=010, 10942 MC; assumed 10M Xs*/
/* specify the address of the page to be erased */
/* trig ISP activity */
Erase a specific flash page
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Flow Chart for Byte Program
IAP_CMD xxxxx010 B
IAP_CONTR 100xx010B
IAP_ADDRH (Address high byte)
IAP_ADDRL (Address low byte)
IAP_DATA (byte date to be written into flash)
IAP_TRIG 46h
IAP_TRIG B9h
(CPU progressing will be hold here)
(CPU continues)
/* choice byte-programming command */

/* specify the address to be programmed */
/* prepare data source */
Program a byte into flash
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Flow Chart for Verify using Byte Read
IAP_CMD xxxxx001 B
IAP_CONTR 100xx010B
/* choice byte-read command */

/* specify the address to be read */
IAP_ADDRH (Address high byte)

ISP_ADDRL (Address low byte)
IAP_TRIG 46h
IAP_TRIG B9h
(CPU progressing will be hold here)
(CPU continues and currently IAP_DATA contain the desired data byte )
Read a byte from flash
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11.3 Demo of the ISP code
;******************************************************************************************
; ISP modes
;******************************************************************************************
IAP_DATA
IAP_ADDRH
IAP_ADDRL
IAP_CMD
IAP_TRIG
IAP_CONTR
;
DATA
DATA
DATA
DATA
DATA
DATA
MOV
0E2h
0E3h
0E4h
0E5h
0E6h
0E7h
ISP_CONTR,#10000011b ;IAP_CONTR.7=1, enable ISP

;IAP_CONTR[2:0]=011, for Fosc=11.0592MHz
;=============================================================================
; 1. Page Erase Mode (512 bytes per page)
;=============================================================================
MOV
IAP_CMD,#03h
;select Page Erase Mode
MOV
MOV
IAP_ADDRH,??
IAP_ADDRL,??
;fill page address in IAP_ADDRH & IAP_ADDRL

;
MOV
MOV
IAP_TRIG,#46h ;trigger ISP processing

IAP_TRIG,#0B9h ;
;Now in processing...(MCU will halt here until complete)

;=============================================================================
; 2. Byte Program Mode
;=============================================================================
MOV
IAP_CMD,#02h
;select Byte Program Mode
MOV
MOV
MOV
IAP_ADDRH,??
IAP_ADDRL,??
IAP_DATA,??
;fill byte address in IFADRH & IAP_ADDRL

;
;fill the data to be programmed in IAP_DATA
MOV
MOV

IAP_TRIG,#0B9h ;
;Now in processing...(CPU will halt here until complete)

;=============================================================================
; 3. Verify using Read Mode
;=============================================================================
MOV
IAP_CMD,#01h
;select Byte Read Mode
MOV
MOV
IAP_ADDRH,??
IAP_ADDRL,??
;fill byte address in ISP_ADDRH & IAP_ADDRL

;
MOV
MOV

IAP_TRIG,#0B9h ;
;Now in processing...(CPU will halt here until complete)

MOV
A,IAP_DATA
;data will be in IFD
CJNE
A,wanted,IAP_error ;compare with the wanted value
...
...
ISP_error:; If IAP_CONTR.4 is 1 ,the ISP/IAP Command fail.
...
;
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11.4 Note on In-System-Programming
During In-System-Programming, the CPU halts for a while for internal ISP processing. At this time, the interrupt
will queue up for being serviced if the interrupt is enabled previously. Once the ISP is complete, the CPU
continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active.
Users, however, should be aware of the following:
(1) Any interrupt can not be serviced in time during the CPU halts for ISP processing.
(2) The low-level triggered external interrupts, /INT0 and /INT1, should keep active until the ISP is
completed.
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12 In Application Programming (IAP)
(First, please refer to Section 1.3 for Flash Memory Configuration.)
The STC11F/Lxx is In Application Programmable (IAP), which allows some region in the Flash memory to be
used as non-volatile data storage while the application program is running. This useful feature can be applied to
the application where the data must be kept after power off. Thus, there is no need to use an external serial
EEPROM (such as 93C46, 24C01, .., and so on) for saving the non-volatile data.
12.1 IAP-memory Address Range

In fact, the operating of IAP is the same as that of ISP except the range of the Flash memory address. The
range for ISP is within the configured ISP-memory, while the range for IAP is within the configured IAP-memory.
Prior to using the IAP feature, users should configure an IAP-memory by programming a proper value to the
option IAPLB[7:0] using a universal Writer or Programmer. The range of the IAP-memory depends on the
contents of IAPLB, as listed below.
IAP lower Address = IAPLB[7:0]x256, and
IAP higher Address = IAP start address 1.
Where, the IAPLB must be an even number.
Section 12.3 lists all the possible ranges for IAP-memory versus different ISP size and programmed IAPLB.
12.2 How to update the non-volatile data by IAP

Because the IAP-memory is a part of Flash memory, only Page Ease is provided for memory erasing. To update
one byte in the IAP-memory, users can not directly program the new datum into that byte. The following steps
show the correct procedure:
Step1)
Step2)
Step3)
Step4)
Save the whole page data (512 bytes) to a buffer (also with size of 512 bytes).
Erase this page (using IAPs Page Erase mode).
Update the wanted byte(s) in the buffer.
Program the updated data out of the buffer into this page (using ISPs Byte Program mode).
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12.3 IAP-memory Start Address
As we have known, the IAP-memory is fixed. See Table 12.3.
12.3.1 STC11C(L)xx IAP-memory

Table 12.3: IAP:2K
Item
Part No.
1
2
3
4
5
STC11F/L01E
STC11F/L02E
STC11F/L03E
STC11F/L04E
STC11F/L05E
block
512 bytes / 4 Page
512 bytes / 4 Page
512 bytes / 4 Page
512 bytes / 2 Page
512 bytes / 2 Page
IAP-memory
Range (Size)
0x0000 ~ 0x07FF (2.0KB)
0x0000 ~ 0x07FF (2.0KB)
0x0000 ~ 0x07FF (2.0KB)
0x0000 ~ 0x03FF (1.0KB)
0x0000 ~ 0x03FF (1.0KB)
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12.4 Note on In-Application-Programming
During In-Application-Programming, the CPU halts for a while for internal IAP processing. At this time, the
interrupt will queue up for being serviced if the interrupt is enabled previously. Once the IAP is complete, the
CPU continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still
active. Users, however, should be aware of the following:
(1) Any interrupt can not be serviced in time during the CPU halts for IAP processing.
(2) The low-level triggered external interrupts, /INT0 and /INT1, should keep active until the IAP is
completed.
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13 Programmable CPU Clock
Users can slow down the MCU by means of writing a non-zero value to the CKS[2:0] bits in the CLK_DIV
register. This feature is especially useful to save power consumption in idle mode as long as the user changes
the CKS[2:0] to a non-zero value before entering the idle mode.
By default (CLK_DIVs reset value is 0x00), the CPU clock is the same as that of the signal on the XTAL1-pin.
Users can change CLK_DIV in real-time and the new CPU clock is active just after the changing is completed.
CLK_DIV (Power Control Register)

7
6
5
4
CKS2 CKS1 CKS0
-----------------------------0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
3
-
2
CKS2
1
CKS1
0
CKS0
CPU Clock
---------------------------Fosc (default)
Fosc/2
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
Fosc/128
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14 Wake-up from Power-down by External Interrupt
For STC11F/Lxx, either hardware (RST-pin) reset or external interrupt (/INT0 and /INT1) can be used to exit
from power-down mode. Hardware reset initializes all the SFRs while external interrupt keeps the SFRs
unchanged. To properly exit from power-down mode, the external interrupt which is used for waking up CPU
must be enabled before entering power-down. During power-down, trigger this external interrupt to wake up the
CPU. Once the CPU is wakened up, the interrupt service routine is serviced till RETI is met, and the next
instruction to be executed will be the one following the instruction that invoked the power-down mode. Note, this
instruction must be a NOP.
Sample code for Wake-up-from-power-down (/INT0 is used in this example)
;******************************************************************************************
; Wake-up-from-power-down by /INT0 interrupt
;******************************************************************************************
INT0
EA
EX0
BIT
BIT
BIT
0B2H
0AFH
0A8H
CSEG
JMP
AT 0000h
start
CSEG
JMP
AT 0003h
IE0_isr
;P3.2
;IE.7
;IE.0
;
;INT0 interrupt vector, address=0003h
IE0_isr:
CLR
EX0
;... do something
;...
RETI
;
start:
;...
;...
SETB
INT0
;pull high P3.2
CLR
SETB
SETB
SETB
IE0
IT0
EA
EX0
;clear INT0 interrupt flag

;may select falling-edge/low-level triggered
ORL
PCON,#02h
;invoke power-down
;enable INT0 interrupt
;... Now, CPU is in power-down mode

;... Wait for an external falling-edge on INT0-pin
;...
NOP
;! Note: here must be a NOP
wake_up:
;If INT0(P3.2) is triggered by a falling-edge,
; the MCU will wake up, and enter "IE0_isr",
;then return here to run continuously !
;...
;...
;
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15 Power-On Reset and Low Voltage Detection
15.1 Power-ON Reset
The CPU will not start to work until the VCC power rises up to the Power-On Reset (POR) voltage: 1.9V and
3.3V for STC11F/Lxx, respectively.
The Power-On Flag, POF bit (PCON.4), is set by hardware to denote the VCC power has ever been less than
the POR voltage. And, it helps users to check if the start of running of the CPU is from power-on or from
hardware reset (RST-pin reset), software reset or Watchdog Timer reset. The POF bit should be cleared by
software.
PCON (Power Control Register)
7
6
5
4
SMOD SMOD0 LVDF
POF
3
GF1
2
GF0
1
PD
0
IDL
POF: Power-ON Flag.

When VCC power is lower than the POR voltage, it is set by hardware (and should be cleared by
software).
LVDF: Low Voltage Flag.
Once low voltage condition is detected (VCC power is lower than LVD voltage), it is set by hardware
(and should be cleared by software).
15.2 Low Voltage Detection

Besides the POR voltage, there is a higher threshold voltage: the Low Voltage Detection (LVD) voltage, 2.3V
and 3.7V for STC11Fxxand STC11Lxx, respectively. When the VCC power drops down to the LVD voltage, the
Low Voltage Flag, LVDF bit (PCON.5), will be set by hardware. (Note that during power-up, this flag will also be
set, and the user should clear it by software for the following Low Voltage detecting.) This flag can also generate
an interrupt if bits ELVD (IE.6) is set to 1. (Refer to Section 9, Interrupt)
Although the MCU can still work well between the ranges 1.9~2.3V (for STC11Fxx) and 3.3~3.7V (for
STC11Lxx), they are not safe enough for the IAP operation (especially writing Flash memory).
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16 Built-in Oscillator
The STC11F/Lxx have a built-in oscillator with the rough oscillating frequency of 6MHz. It can be used to
replace the external crystal oscillator in the application which doesnt need an exact oscillating frequency. To
enable the built-in oscillator, users should enable the option Internal Clock by a STC Writer/Programmer.
Typically, the oscillating frequency is about 6MHz at room temperature (25C). And, the variation may be up to
30% over the temperature of 40C to +85C (+30% at 40C, and 30% at +85C).
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17 XTAL Oscillating and Reset Circuitry
17.1 XTAL Oscillating
As shown in the XTAL Oscillating Circuit, to achieve successful and exact oscillating, the C1 and C2 (about
20pF~150pF) are necessary regardless of enabled or disabled OSCDN within the whole operation frequency
range.
XTAL Oscillating Circuit
17.2 Reset Circuitry

When power is turned on, the circuit holds the RST pin high for an amount of time that depends on the capacitor
value and the rate at which it charges. To ensure a valid reset, the RST pin must be held high long enough to
allow the oscillator to start up plus two machine cycles. The following Table shows the best (R,C) combinations
which are adequate to all different operating frequencies.
C
1uF
4.7uF
10uF
About 130K
About 27K
About 15K
Reset Circuit
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18 Install ISP Tooling
Setting Up the Hardware.
Connect the IBM PC to the RS-232 cable through one of
the system COM ports. Connect the STC isp-writer board to RS-232 line
and set the STC isp-writer board power switch is off
Setting Up the PC site AP.

I.
II.
Preparation the STC-ISP-V5.01-Setup-English or download form www.stcmcu.com. The quick setup

wizard in www.stcmcu.com. The step-by-step instructions that follow are shown in Windows XP .or
Vista. The steps and screen are similar for the other Windows operating systems.
Run setup.exe.
Using the STC-ISP.

I.
II.
Open the STC-ISP V5.01.

Selection an MCU type.
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III.
Selection an baud-rate to communication.
IV.
Open the users HEX file from open-code-file icon.
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V.
Selection external crystal or internal RC.(default: external crystal)
VI.
Press ISP Programming icon then waiting to programming MCU
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VII.
Power On your target board or STC-ISP target board.
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19 Instruction Set
The Instruction Set is fully compatible to that of the standard 8051 MCU except the execution time spent. The
fastest (or shortest) execution time is just one clock (if PCON2=0x00) and the longest time is 6 clocks. The
average performance can be up to 6~7 times that of the standard 8051 MCU. The MOVX instructions,
however, are omitted for STC11F/Lxx.
Prior to introducing the Instruction Set, users should take care the following notes:
Rn
Working register R0-R7 of the currently selected Register Bank.
direct 128 internal RAM locations, any I/O port, control or status register.
@Ri
#data
Indirect internal RAM location addressed by register R0 or R1.

8-bit constant included in instruction.
#data16 16-bit constant included in instruction.

addr16 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the
64K-byte program memory address space.
addr11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K-byte
page of program memory as the first byte of the following instruction.
rel
Signed 8-bit offset byte. Used by SJMP and all conditional jumps. Range is 128 to +127 bytes
relative to first byte of the following instruction.
bit
128 direct bit-addressable bits in internal RAM, any I/O pin, control or status bit.
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19.1 Arithmetic Operations
Mnemonic
Description
Byte
Execution
Clock Cycles
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
2
3
3
2
2
3
3
2
2
3
3
2
2
3
4
4
1
2
3
4
4
4
5
4
ARITHMETIC OPERATIONS
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
MUL
DIV
DA
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
DPTR
A
Rn
direct
@Ri
AB
AB
A
Add register to Acc

Add direct byte to Acc
Add indirect RAM to Acc
Add immediate data to Acc
Add register to Acc with Carry
Add direct byte to Acc with Carry
Add indirect RAM to Acc with Carry
Add immediate data to Acc with Carry
Subtract register from Acc with borrow
Subtract direct byte from Acc with borrow
Subtract indirect RAM from Acc with borrow
Subtract immediate data from Acc with borrow
Increment Acc
Increment register
Increment direct byte
Increment indirect RAM
Increment data pointer
Decrement Acc
Decrement register
Decrement direct byte
Decrement indirect RAM
Multiply A and B
Divide A by B
Decimal Adjust Acc
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19.2 Logic Operations
Mnemonic
Description
Byte
Execution
Clock Cycles
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
2
3
3
2
4
4
2
3
3
2
4
4
2
3
3
2
4
4
1
2
1
1
1
1
1
LOGIC OPERATIONS
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
RLC
RR
RRC
SWAP
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
A
A
A
A
A
A
AND register to Acc

AND direct byte to Acc
AND indirect RAM to Acc
AND immediate data to Acc
AND Acc to direct byte
AND immediate data to direct byte
OR register to Acc
OR direct byte to Acc
OR indirect RAM to Acc
OR immediate data to Acc
OR Acc to direct byte
OR immediate data to direct byte
Exclusive-OR register to Acc
Exclusive-OR direct byte to Acc
Exclusive-OR indirect RAM to Acc
Exclusive-OR immediate data to Acc
Exclusive-OR Acc to direct byte
Exclusive-OR immediate data to direct byte
Clear Acc
Complement Acc
Rotate Acc Left
Rotate Acc Left through the Carry
Rotate Acc Right
Rotate Acc Right through the Carry
Swap nibbles within the Acc
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19.3 Data Transfer
Mnemonic
Description
Byte
Execution
Clock Cycles
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
2
4
2
3
3
4
4
3
3
3
3
3
4
4
3
3
3
3
4
3
3
4
4
4
DATA TRANSFER
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
XCH
XCH
XCH
XCHD
A,Rn
A,direct
A,@Ri
A,#data
Rn,A
Rn,direct
Rn,#data
direct,A
direct,Rn
direct,direct
direct,@Ri
direct,#data
@Ri,A
@Ri,direct
@Ri,#data
DPTR,#data16
A,@A+DPTR
A,@A+PC
A,@Ri Note
A,@DPTR Note
@Ri,A Note
@DPTR,A Note
direct
direct
A,Rn
A,direct
A,@Ri
A,@Ri
Move register to Acc

Move direct byte o Acc
Move indirect RAM to Acc
Move immediate data to Acc
Move Acc to register
Move direct byte to register
Move immediate data to register
Move Acc to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move Acc to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load DPTR with a 16-bit constant
Move code byte relative to DPTR to Acc
Move code byte relative to PC to Acc
Move external RAM (8-bit address) to Acc
Move external RAM (16-bit address) to Acc
Move Acc to external RAM (8-bit address)
Move Acc to external RAM (16-bit address)
Push direct byte onto Stack
Pop direct byte from Stack
Exchange register with Acc
Exchange direct byte with Acc
Exchange indirect RAM with Acc
Exchange low-order digit indirect RAM with Acc
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19.4 Boolean Variable Manipulation
Mnemonic
Description
Byte
Execution
Clock Cycles
1
2
1
2
1
2
2
2
2
2
2
2
1
4
1
4
1
4
3
3
3
3
3
4
BOOLEAN VARIABLE MANIPULATION
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
bit
C
bit
C
bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to Carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
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19.5 Program and Machine Control
Description
Byte
Execution
Clock Cycles
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ
rel
JNZ rel
JC
rel
JNC rel
JB
bit,rel
JNB bit,rel
JBC bit,rel
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct,rel
Absolute subroutine call

Long subroutine call
Return from subroutine
Return from interrupt subroutine
Absolute jump
Long jump
Short jump
Jump indirect relative to DPTR
Jump if Acc is zero
Jump if Acc not zero
Jump if Carry is set
Jump if Carry not set
Jump if direct bit is set
Jump if direct bit not set
Jump if direct bit is set and then clear bit
Compare direct byte to Acc and jump if not equal
Compare immediate data to Acc and jump if not equal
Compare immediate data to register and jump if not equal
Compare immediate data to indirect RAM and jump if not
l
Decrement
register and jump if not equal
Decrement direct byte and jump if not equal
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
6
6
4
4
3
4
3
3
3
3
3
3
4
4
5
5
4
4
5
4
5
NOP
No operation
Mnemonic
PROAGRAM AND MACHINE CONTROL
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STC11F02xx Application Note - V1.0

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STC Technology Co., Ltd.

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This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

STC Technology Co., Ltd. 1999 All right reserved.

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

note: x F : 3.5V ~ 5.5V L 2.6V ~ 3.6V

** for test only

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION

Program Status Word

Data Pointer High

Data Pointer Low

Serial Port Control

Serial Data Buffer

The following SFRs are new added.

CLK_DIV System Clock Divider

Slave Address Mask

Port1 Mode Register 0

Port1 Mode Register 1

Port3 Mode Register 0

Port3 Mode Register 1

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

ISP_CMD ISP Flash Mode Table

ISP Flash Address

BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION

ISP_DATA ISP Flash Data

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION

Program Status Word

Data Pointer High

Data Pointer Low

Serial Port Control

Serial Data Buffer

The following SFRs are new added.

CLK_DIV System Clock Divider

Slave Address Mask

Port1 Mode Register 0

Port1 Mode Register 1

Port3 Mode Register 0

Port3 Mode Register 1

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

ISP Control Register

ISP Flash Mode

ISP_DATA ISP Flash Data

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

Address Space for STC11F/Lxx embedded Flash memory

This document information is the intellectual property of STC Technology Co.,Ltd..

STC Technology Co., Ltd. 1999 All right reserved.

2.1 Port Configurations

Input-Only (High Impedance, Hi-Z)

P1M1 (Port1 Mode Register 1)

P3M0 (Port3 Mode Register 0)

P3M1 (Port3 Mode Register 1)

This document information is the intellectual property of STC Technology Co.,Ltd..