A FPGA-based Software GPS Receiver

Implementation
Using Simulink and Xilinx System Generator
*Hun-Soo Cho, Sung-Hyuck Im, Gyu-In Jee
Dept. of Electronics Engineering, NiTRi
Konkuk University
Seoul 143-701,KOREA
*hunsoo98@hanmail.net

Simulink and Xilinx System Generator for the GPS

receiver baseband signal processing design. The signal
processing components that require massive computation,
for example, correlator, C/A code generator, DCO are
designed by the Xilinx FPGA block and implemented on
FPGA board. The other parts are implemented by
software PC. An interference mitigation technique using a
temporal adaptive filtering is developed and implemented
on this FPGA-based GPS receiver. The performance of
the designed receiver is presented.

BIOGRAPHY
Hun-Soo Cho is under the M. Sc course in the
Department of Electronics Engineering, Konkuk
University, Korea. He received the B.Sc. degree (2004) at
Konkuk University.
Sung-Hyuck IM is a Ph.D student in GPS system lab,
the Department of Electronics Engineering, Konkuk
University. He received the B.Sc. degree (2003) and M.Sc.
degree (2005) in Konkuk University. He is interested in
software GPS receiver, Anti-jamming, Navigation sensor
integration, and Indoor positioning.
Gyu-In Jee is a professor in the Department of
Electronics Engineering, Konkuk University. He received
the B.Sc degree(1982) and M.Sc degree(1984) at Seoul
National University and Ph.D degree in Systems
Engineering from Case Western Reserve University, OH,
United States(1989). His research interests include
GPS/INS integration, GPS receiver signal processing,
Wireless location, and GPS anti-jamming. He is a
committee of the Korea GNSS technical council.

INTRODUCTION
Recently, Software GPS receiver is developed on the
Window or Linux operating system. GPS receiver
development based on SDR has more advantages than the
conventional GPS receiver because the software GPS
receiver can process the future satellite signal such as
Galileo , GPS L5 and Glonass without extra hardware. In
order to the interference rejection or mitigation receiver
using the FFT or Adaptive filter, we can easily implement
this interference rejection block in front of the GPS
correlator. But the problem is computation burden. We
study the software based GPS receiver on PC and we can
implement the 6-7 channel real time software GPS
receiver without no approximation about the code
generation and carrier generation. If the code and carrier
approximation is used, we can implemented the above
twenty channels in real time on P4 3G processor. In this
case, we must submit the error in the code and carrier
tracking loop. As a result, we need the development
method which decreases the computation burden and is
easily implemented.
Xilinx introduce system generator software which can
implement the FPGA design using the matlab simulink. In
case of using this software, although we design simulink
block without the FPGA programming knowledge, the
system generator generate the VHDL code to download to

ABSTRACT
Recently, some software based GPS receivers have
been developed and they are often implemented on PC
under Windows and C language environments. Even
though it could successfully track GPS signals and
calculate user position in real time, the computational
time for the signal acquisition and tracking is still massive
for totally software only GPS receiver. If additional signal
processing is required for multipath mitigation,
interference cancellation, and weak signal detection etc,
more computational power must be provided FPGA/DSP
based approach is one promising solution for the
advanced SDR GPS receiver.
In this paper we develop a FPGA-based software GPS
receiver using a high level design tool. We use a

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FPGA. But in order to run with PC software in real time,

we need code interface part to VHDL directly. We use the
XtreamDSP board. This board support PCI or USB. We
use the PCI bus for the real time operating and
XtreamDSP interface format.
In this paper, we implement the baseband correlator and
interference mitigation receiver using the XtreamDSP
board and System Generator. And we show the method
which can easily implement advanced receiver. And we
compare the implemented receiver using matlab simulink
with conventional receiver.

Correlator Implementation And Verification

If the Xilinx System generator and XtremeDSP board is
used, we can more easily implement the FPGA program
and verification. And we test the algorithm in the
hardware FPGA using the co-simulation. FPGA
implementation Method using the Xilinx System
Generator is showed Figure 3. First, we design the
simulink model and simulink level simulation. and this
block is tested with FPGA using the Hardware cosimulation. Sometimes, user FPGA code is needed. In this
case user VHDL code and VHDL code made by system
generator must be merged. And the merged VHDL code
is tested, verified and run in real time.

SOFTWARE GPS RECEIVER IMPLEMENTATION

USING THE XTREMEDSP BOARD AND SYSTEM
GENERATOR
Generally, recent GPS receiver is composed of two
chip or three chip. The receiver is composed of RF chip
which converts RF signal to IF signal, correlator which
processes the baseband signal and DSP which calculates
the navigation solution and tracking loop.
In this paper, we implemented the correlator with
FPGA and tracking loop and navigation solution is
calculated PC processor. Figure 1 presents the
conventional GPS receiver configuration.

Fig 1. Conventional GPS receiver configuration

RF Configuration

Fig 3. FPGA implementation method using System

Generator

Because we cannot implement RF part, we use the

signal from the conventional GPS receiver RF chip. RF
chip which uses in this paper is the Zarlink GP2015 and
this chips Frequency plan is Figure 2. GP2015 chips
final IF frequency is about 4.309Mhz. Sampling
frequency is about 5.714Mhz and use the band pass
sampling (under sampling). As a result, the center
frequency (4.309Mhz) is downed 1.405Mhz by aliasing
and FPGA operating clock is sampling frequency.

The baseband processing part is designed with

Simulink block provided in the Xilinx System Generator
and implemented with FPGA. Before implementing the
entire GPS receiver, we implement one channel receiver
in order to verify code and carrier module and tracking
performance. One channel receiver is composed of Code
DCO, Code Generator, Carrier DCO, Carrier Generator,
Epoch Generator and Measurement Generator.
Measurements are half code phase, under half code
phase, carrier cycle, carrier phase. Generally, GPS
receiver is only use the CA code phase for navigation
solution. Figure 4 is showed GP2021 baseband chip
configuration. Figure 5 presents the one channel
correlator which we implement using the Simulink with
System Generator.

Fig 2. Frequency Plan

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Code generator and DCO

Code Generator which implemented in this paper is
different from conventional GPS receivers code
generator. Conventional GPS receivers code generator
has C/A code generation part. But we use the 1/2 chip
sample code table and index the table to generate code
value. This table is implemented in BRAM part on FPGA.
As a result, we can use more programming resource.
Code generator makes two codes, Prompt and Early-Late.
Code DCO accumulator has 26-bit accumulator. Every
time overflow is occurred, code index is increase. Half
code measurement is this index and under half code
measurement is Code DCO accumulators most
significant 10 bit. This block also makes dump signal.

Fig 4. GP2021 correlator configuration

Fig 7. Code Generator and DCO

FPGA GPS Receiver Design and Verification
To verify whether 1-channel receiver operates well or
not we set up an outer antenna in advance and saved
down-converted IF-data, which comes through GP2015,
as a file. After that, we used a post-process method in
matlab simulink. A carrier wave tracing loop and a code
tracing loop are built with a secondary FLL and help
information of a carrier wave. Following Figure 8 shows
the signal tracing result of the 1-channel receiver. GPS is
based on BPSK, so that if we use PLL, the signals gather
to the inphase side because the phase is fixed. In this
paper, however, we used FLL, so that the signals made a
circle. If this value is lower than the threshold value, it
means that the signal is lost. Now, we can develop a
multi-channel receiver with this design.

Fig 5. One channel receiver block.

Carrier generator and DCO
This part is composed of cosine, sine table and DCO to
generate carrier. These tables have the four value
1, 3 and eight phase value. But real phase value is
about 4 phase because of sampling frequency (5.714Mhz)
with respect to IF center frequency (4.309Mhz). Carrier
DCO has 27-bit Accumulator and most significant 3-bit
complies with cosine, sin table. Carrier cycle is made by
Accumulators
28bit
overflow.
Carrier
phase
measurement is made by accumulators most significant
10 bit.

Fig 6. Carrier Generator and DCO

Fig 8. I-Q plot

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different frequencies but different phases, so that there is

probability which mata-stablility problem happens. To
avoid this problem only one clock should be used in a
whole system, however we didn't because of the
difficulty: we have to re-design the hardware of RF-part.
We should add a synchronizing part at the end of
interface to resolve the problem which happens because
of the two different asynchronous clocks.

Fig 9. Code Lock Indicator

Interface Design Between FPGA And PC

For a real-time operation an interface with PC are
needed. To support this XtremeDSP board gives an API
which makes an interface through a PCI bus. We can
exchange data by this API, however the part actually
exchanging data is the interface FPGA. It is shown at Fig.
10 in detail. User has to make a connection between an
interface FPGA and a user FPGA in a system core. Of
course this work needs some understanding of a VHDL
code; however the new version of system generator even
supports this work and offers matlab simulik Xilinx block
set to generate a code.

Fig 11. Interface between User FPGA and PC

Fig 12. Interface VHDL State Diagram

Organizing Overall System
To develop
multi-channel receivers register
organization which shows status of channels and
interfaces connecting addresses and registers of channel
control and data reading are needed. The process of remapping input sin and mag bit and Tic generator and
interrupt generator which decide time for latching are also
needed. Interrupt signal period is about 500us. Following
system block diagram is an 8-channel receiver developed.
As we have seen, the processes which generate an 8channel receiver developed by matlab simulink to a
VHDL code by Xilinx system generator and merge a
handmade interface VHDL code. Handwork is necessary
because this work is not automatically advanced.

Fig 10. Interface between User FPGA and PC

There are various ways interfacing between the
interface FPGA and the user FPGA but these two ways,
memory mapping and DMA, are recommended. In this
research we use a memory mapping because DMA is
complicated and inefficient in a GPS receiver
development. After setting specific addresses for read and
write, data exchanges through them.
The most difficult part of using memory mapping
interface method is in asynchronous clock. The system
core (correlator part) uses 5.714Mhz and the interface
FPGA uses 40Mhz. These two clocks have not only

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Fig 13. Interface VHDL State Diagram

Verification Of Receiver Acting
We compared 8 channel receiver with current hardware
receiver based on GP2021. The test is for about one hour
with real outer signal. In result occasionally there were
some cases in which position roots of FPGA receiver are
a little bit bigger than expected. The reason is that the
phenomena losing data in a specific channel sometimes
happen. Also the number of satellites which can be
tracked is limited to 8 in FPGA. Figure 16 is implemented
receivers result and 2DRMS is about 5.0312m. Figure 17
is conventional GPS receivers result and 2DRMS is
about 4.397m.

Fig 16. Position Error of implemented receiver

(2DRMS 10.0312m)

Fig 17. Position Error of Hardware receiver

(2DRMS 8.3971m)

Fig 14. SV number

Fig 18. Real-time Running

Fig15. 2DRMS per epoch

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ADAPTIVE FILTER IMPLEMENTATION

Narrowband interference can seriously degrade the
performance of GPS systems. Several techniques exit for
reducing the interference, including adaptive filters,
overlapped FFTs. All these techniques attempt to filter
out the interference before the GPS receiver performs
correlation. In this paper, adaptive filter is implemented.
Adaptive filter block diagram is Figure 19. We use the
20-tap FIR filter. Estimator uses LSE(Least Square Error).
Delay
+
x
IF Signal

FIR Algorithm

e
-

Weight Update

Weight
Calculation

Fig 19. Adaptive filter block diagram

Fig 21. Power Spectrum Compare

Adaptive filter design and Verification

CW interference signal is generated by software and
simulated with matlab simulink block. The divider takes
lots of hardware resource and latency when you develop
weight vector update loop using VHDL. To resolve this
problem, we fixed variable Mu, which is needed to be
divided; as constant. The adaptive filter consists of delay
block, FIR algorithm block, weight calculation & update
block and sum block. Fig 21 is the result which mitigates
the CW interference.

Adaptive filter block integration

We added an adaptive filter and AGC at the input part
of the developed correlator. The input signal is quantized
by 10 bits. Even though the receiver has 8 channels, we
used 4 channels when verification of receiver acting
because the adaptive filter takes lots of hardware resource.

Fig 22. Adaptive filter block integration.

Verification of receiver acting
We inputted a 10 bit-quantized signal in twice. The first
was a GPSIF signal only and the next was a GPSIF signal
mixed with a CW interference signal. The power of the
interfering signal was 40dB. Compared with the former
case, the latter case removed the interfering signal, but
resulted signal loss at the notch part. Because of the signal
loss, SNR of the signal was lower case and PRerr was
bigger than the former.

Fig 20.Adaptive filter

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ACKNOWLEDGMENTS
This work was supported by NiTRi, IDEC, and IT-SoC.

REFERENCES

Fig 23. Channel state when GPSIF signal is inputted

[1]GP2021 Datasheet GPS 12-Channel correlator, Zarlink

[2]WINMON Users Guide for the GPS architect, GEC
Plessey
[3]Xilinx System Generator for DPS user guide, Xilinx
Development System
Fig 24. Channel state when GPSIF signal mixed with CW
interference signal is inputted

[4]Clifford E. cummings(2001) synthesis and scripting

techniques for designing multi-asynchronous clock
designs, snug 2001(san jose)
[5]R.Rifkin, J.J.Vaccaro(2000), Comparison of narrow
adaptive filter technologies for GPS, MITRE Technical
report
[6]S.Haykin(1996), Adaptive Filter Theory, 3rd Edition,
Prentice Hall, N.J. p437

Fig 25. Position error of GPSIF signal and GPSIF signal

mixed with CW interference signal

CONCLUSIONS
Recently with growing interest in SDR there are also
lots of experiments which use SDR to build GPS. Of
course there are other programming languages; however
they give much load on speed of computer. Therefore
building receiver by Xilinx system generator is a good
way for both flexibility like SDR and benefit on speed.
Also XtremeDSP board offers interface for users to
make it. So this paper will be a fundamental base for not
only L1 C/A code which is already designed but future
receiver development which can get L5 signal or Galileo
signal easily. Furthermore it will be efficient to develop a
receiving algorithm with special purpose like military
ones use adapting filter or FFT in the front part of
correlator to mitigate interference signals.

ION GNSS 18th International Technical Meeting of the

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