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OBJECTIVES
AHB2
(max 180MHz)
and
JTAG/SW Debug
ETM
Nested vect IT Ctrl
1 x Systic Timer
DMA
16 Channels
Clock Control
80/112/140 I/Os
AHB1
(max 180MHz)
Bridge
2x6x 16-bit PWM
4 x SPI
2 x USART/LIN
256KB SRAM
External Memory
Interface with SDRAM
Power Supply
LCD Controller
Chrom-ART
USB 2.0 OTG HS
Reg 1.2V
POR/PDR/PVD
XTAL oscillators
32KHz + 8~25MHz
Int. RC oscillators
(max 45MHz)
32KHz + 16MHz
PLL
RTC / AWU
5x 16-bit Timer
4KB backup RAM
2x 32-bit Timer
2x Watchdog
APB2
Up to 16 Ext. ITs
Camera Interface
2x DAC + 2 Timers
Synchronized AC Timer
3 x 16bit Timer
1.71V-3.6V Supply
2MB Flash
Memory Dual
Bank
Ethernet MAC
10/100, IEEE1588
APB1
Bridge
(max 90MHz)
256KB SRAM
Flash I/F
CORTEX M4
CPU+ MPU
+ FPU
180 MHz
Encryption
1x SDIO
2x CAN 2.0B
3x 12-bit ADC
2x SPI/I2S
24 channels / 2Msps
1xSAI
6x USART/LIN
Temp Sensor
3x I2C
Dual Port
DMA1
Master 2
Dual Port
DMA2
Master 3
Ethernet
10/100
LCD-TFT
DMA2D
Master 4
High Speed
USB2.0
Master 5
Master 6
Master 7
FIFO/DMA
FIFO/DMA
FIFO
FIFO
Dual Port
AHB1-APB2
AHB1
AHB2
Dual Port
AHB1-APB1
SRAM1
112KB
SRAM2
16KB
SRAM3
64KB
FMC
I-Code
Bank1
1Mbytes
2Mbytes
Flash
Bank2
1Mbytes
D-Code
ART
Accelerator
S-Bus
I-Bus
Master 1
System Architecture
D-Bus
CCM
data RAM
64KB
CORTEX-M4
180MHz
FPU & MPU
Graphics on STM32
Overview
Past / Today
Keyboard and/or Knob
Optional 7-segment display
Display needs
For home appliance
Display size and form factor will be very different from an equipment to another
In most of them we shall not be above 6~7 inches
iPad 2 display is 132PPI (pixels per inch) and can go up to 160 or even more
(retina display)
7 16:9 display represents 800x480 ~384kpix @130PPI (1024x576 @160PPI)
Perfect icons
State of the art animations (coverflowetc)
Font 1
Prev
Next
STM32F4x9 Architecture
Cortex-M4
Chrom-ART
Accelerator
(DMA2D)
TFT
Controller
Bus Matrix
Internal
Flash
Internal
SRAM
External
Memory
Controller
External
memory
10
11
11
Cortex-M4
Chrom-ART
Accelerator
TFT
Controller
Bus Matrix
Cost saving +
Graphic Acceleration
Internal
Flash
Internal
SRAM
STM32F4x9
External
Memory
Controller
12
Cortex-M4
Chrom-ART
Accelerator
TFT
Controller
Bus Matrix
Internal
Flash
Internal
SRAM
STM32F4x9
External
Memory
Controller
SDRAM
13
TFT Controller
STM32F4x9 package
High-End
Yes
32-bit
LQFP208/BGA216
Mid-End
Yes
16-bit
LQFP144/
BGA176 / LQFP176
No
No
LQFP100/LQFP144
Yes
No
LQFP100/LQFP144
Low-End
MT48LC4M16A2P-7E : 64Mb
MT48LC16M16A2P-7E : 256Mb
14
Build the project (F7) and debug (Ctrl-D) this may take around one
minute and run (F5).
Every push of USER button will switch to next demonstration.
The Discovery kit is present for you, you can keep it after
the seminar.
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16
17
Benefits
AHB bus Master
Can access any part of address space ext. memory, internal SRAM, Flash.
Multi-Layer Support
Windowing
Blending
Flexible programmable parameters for each Layer
19
LCD-TFT architecture
FIFO
PFC
64x32b
LCD_CLK
Blending
LCD_HSYNC
Layer2
LCD_VSYNC
FIFO
64x32b
PFC
Dithering
LCD_DE
LCD_R[7:0]
Configuration and
status registers
APB Interface
LCD_G[7:0]
Synchronous
Timings
Generation
LCD_B[7:0]
LCD Panel
AHB Interface
Layer1
20
LTDC Timings
Start of
Frame
HSYNC
Active Width
HBP
HFP
VSYNC
VBP
D1,L1
Active
Heigh
Dm,, Ln
VFP
10/17/2013
21
Frame Display
1 Frame
VSYNC
Vertical Back
Porch (VBP)
LCD Lines
Vertical Front
Porch (VFP)
1 Line
HSYNC
LCD_CLK
LCD RGBs
LCD Data
Enable
Horizontal
(VBP)
LCD Columns
Horizontal
(HFP)
480
22
Vertical/Horizontal transactions
Vertical transaction
Start of Frame
Horizontal transaction
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24
Total Pixel
320x240 (QVGA)
76.8K
16bpp
153.6
8bpp
76.8
480x272
(WQVGA)
130.5K
16bbp
261.12
640x480 (VGA)
307.2K
16bbp
614.4
25
LTDC Reset
It is reset by setting the LTDCRST bit in the RCC_APB2RSTR register
26
LCD-TFT Signals
The LCD-TFT IO pins not used by the application can be used for
other purposes.
LCD-TFT Signals
Description
LCD_CLK
LCD_HSYNC
Horizontal Synchronization
LCD_VSYNC
Vertical Synchronization
LCD_DE
Data Enable
LCD_R[7:0]
LCD_G[7:0]
LCD_B[7:0]
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28
29
Aliased
0xFF = opaque
Anti-aliased
0xFFFF0000 0xAAFF0000 0x30FF0000
30
31
bpp
31:24
23:16
15:8
ARBG8888
Ax[7:0]
Rx[7:0]
Gx[7:0]
Bx[7:0]
32
RGB888
Bx+1[7:0]
Rx[7:0]
Gx[7:0]
Bx[7:0]
24
RGB565
Rx+1[4:0] Gx+1[5:3]
Gx+1[2:0]
Bx+1[4:0]
ARGB1555
Gx+1[2:0]
Bx+1[4:0]
ARGB4444
Ax+1[3:0] Rx+1[3:0]
L8
Lx+3[7:0]
Lx+2[7:0]
Lx+1[7:0]
Lx[7:0]
AL88
Ax+1[7:0]
Lx+1[7:0]
Ax[7:0]
Lx[7:0]
16
AL44
Ax+3[3:0]
Lx+3[3:0]
Ax+2[3:0] Lx+2[3:0]
Ax+1[3:0] Lx+1[3:0]
Ax[3:0] Lx[3:0]
Gx+1[3:0]
Bx+1[3:0]
Rx[4:0]
Ax[0]
7:0
Gx[5:3]
Rx[4:0] Gx[4:3]
Ax[3:0]
Rx[3:0]
Gx[2:0]
Gx[2:0]
Gx[3:0]
Bn[4:0]
16
Bx[4:0]
16
Bx[3:0]
16
ARGB1555
0
PFC
32
ARGB8888
RGB888
ARGB4444
ARGB1555
RGB565
Direct coding
33
AL88
L8
AL44
A8
L4
A4
Index
Color
LookUp Table
0x00
0x01
Indirect coding
...
0xFF
34
35
CLUT- Palletized
The R, G and B values and their own respective address are
programmed through the LTDC_LxCLUTWR register.
L8 and AL88 input pixel format, the CLUT has to be loaded by 256 colors
AL44 input pixel format, the CLUT has to be loaded by 16 colors. The address of
each color must be filled by replicating the 4-bit L channel to 8-bit.
L0 (indexed color 0), at address 0x00,
L1, at address 0x11.
L2, at address 0x22
Indexed 16 L4
Source - wikipedia.org
Indexed 256 - L8
RGB888
36
Picture quality
Difference is mostly visible in the color transitions (like
the blue sky)
Dithering is improving the quality, but it make worse
details recognition
Dithering
17/10/2013
37
START_POS_X
START_POS_Y
END_POS_Y
END_X_POS
38
Frame Buffer
Line Length
Pitch
.
.
Number of Lines
39
.
.
.
.
40
Horizontal
scroll
Vertical scroll
320
240
320
400
41
Layer 2
42
Blending Example 1
Layer 1 blending with background
Background is black
Layer 2 is disabled.
100%
75%
50%
25%
0%
43
Blending Example 2
Layer 1 and Layer 2 blending
Background color is black
Layer 1 Constant Alpha set to 100 %
Layer 2 Constant Alpha is set to:
100%
75 %
50 %
25 %
0%
44
45
46
47
48
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LTDC interrupts
Two interrupts vectors:
LTDC global interrupt
Line interrupt
Register Reload
Interrupt event
Event flag
Enable bit
Line
LIF
LIE
Register Reload
RRIF
RRIEN
FIFO underrun
FUERRIF
FUERRIE
Transfer Error
TERRIF
TERRIE
50
Chrom-ART Accelerator
STM32F4 Graphic Accelerator (DMA2D)
Overview
Step 1 : Create the content in a frame buffer
Text 1
Font 1
Prev
Next
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53
21C
Humidity
62%
ARMED
-5C
54
21C
Humidity
62%
ARMED
-5C
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56
Bitmap or Vector
Bitmap
High ROM usage
No CPU usage if no compression,
but can be needed for
uncompressing
Geometrical transformations
limited and would need filtering
Description standard bitmap files
that are converted into C table
Vector graphics
Low ROM usage
High CPU usage as image needs
to be generated : a GPU is
mandatory
Geometrical transformations are
natural
Description through
Polygons : 3D graphics
Curves : 2D graphics
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58
STM32F42x/F43x Architecture
Cortex-M4
Chrom-ART
Accelerator
TFT
Controller
Bus Matrix
Internal
Flash
Internal
SRAM
External
Memory
Controller
59
60
Bitmaps
Overview
Bitmap are an array representation of an image
It shall have the at least following properties
Width (in pixel)
Width
How color are coded
Height
61
Blending
Blending consist in drawing an image onto another respecting the
transparency information
As a consequence blending implies to read 2 sources, then blend
then write to the destination
Blended
Not Blended
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Background
Almost Uniform
L8 mode
Button
Round shape
Gradient
ARGB8888 mode
14:21
Temperature
21C
Humidity
62%
-5C
Icon
Complex shape
Many colors
ARGB8888 mode
ARMED
Fonts
Specific management with A8 or A4 mode
63
DMA2D source
parameters:
Location in
memory, width,
height, pixel format
DMA2D destination
parameters:
Location in buffer,
width, height, pixel
format, line offset
foreground
output
DMA2D
ARMED
background
FLASH content
ARMED
64
Font management
Bitmap fonts are managed only using alpha channel (transparency)
PFC
65
Summary
To generate my 24bpp frame buffer I will have to
Copy background from the ROM to the frame buffer with PFC L8 to RGB888
Copy buttons & icons from the ROM to the frame buffer with blending
Copy characters from the ROM to the frame buffer with PFC A4 to ARGB8888 and
blending
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67
Chrom-ART Accelerator
(DMA2D)
Overview
The Chrom-ART combines both a DMA2D and graphical oriented
functionality for image blending and pixel format conversion.
To offload the CPU of raw data copy, the Chrom-ART is able to copy
a part of a graphic content into another part of a graphic content, or
simply to fill an part of a graphic content with a specified color.
In addition to raw data copy, additional functionality can be added
such as image format conversion or image blending (image mixing
with some transparency).
68
Chrom-ART
Accelerator
TFT
Controller
Bus Matrix
Internal
Flash
Internal
SRAM
External
Memory
Controller
69
Chrom-ART features
AHB bus master with burst access to any system memory
Programmable bitmap height, width and address in the memory
Programmable data format (from 4-bit indirect up to 32-bit direct)
Dedicated memory for color lookup table (CLUT) independent from LTDC
Programmable address destination and format
Optional image format conversion from direct or indirect color mode to
direct color mode
70
Foreground
FG FIFO
FG PFC
Blender
BG FIFO
Background
BG PFC
Output
PFC
Output
FIFO
71
Bitmap parameter
Address
Width
Original_Address
14:21
Temperature
21C
Original_Height
Height
Humidity
62%
-5C
ARME
D
Original_Width
Address = Original_Address + (X + Original_Width * Y) * BPP
LineOffset = Original_Width - Width
72
Output CM[2:0]
ARGB8888
0000
000
RGB888
0001
001
RGB565
0010
010
ARGB1555
0011
011
ARGB4444
0100
100
L8
0101
Not supported
AL44
0110
Not supported
AL88
0111
Not supported
L4
1000
Not supported
A8
1001
Not supported
A4
1010
Not supported
73
CLUT management
When an indirect color mode L8, AL44 or AL88 is used, the bitmap
CLUT must be loaded into the Chrom-ART
Each FG and BG has its own dedicated memory for CLUT.
74
Supported operations
4 functional modes are supported
Register to memory : the destination bitmap is filled with the specified output color
Memory to memory : the data are fetch through the FG and are written to the
destination bitmap without any color format modification (no PFC)
Memory to memory with PFC : the data are fetch through the FG and are written
to the destination bitmap after being converted into the destination color format
(PFC)
Memory to memory with PFC and blending : the data are fetched through the
FG and the BG, are converted, are blended together and are written to the
destination bitmap
75
Alpha modulation
When the PFC is activated the Alpha value of the pixel can be
modified as follow
Kept as it is
76
Line Watermark
For synchronization purpose, an interrupt can be generated when a
specified line has been written by the Chrom-ART into the memory
The line number is defined by the filed LW[15:0] of the DMA2D_LWR
register
DMA2D
transfer
Line
watermark
interrupt
77
Interrupts
Interrupt
Flag
Enable
Clear
Description
Transfer Error
TERIF
TERIE
CTERIF
Transfer Complete
TCIF
TCIE
CTCIF
Transfer Watermark
TWIF
TWIE
CTWIF
CAEIF
CAEIE
CCAEIF
CLUT Transfer
Complete
CTCIF
CTCIE
CCTCIF
CEIF
CEIE
CCEIF
Configuration Error
78
Application
Application
STemWin
STemWin
Cortex-M4
Chrom-ART
Cortex-M4
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www.st.com/stm32f4