FPGA BASED STEPPER MOTOR DRIVE

CHAPTER 3
HARDWARE DESCRIPTION
3.1 FPGA

Field-programmable gate array (FPGA) is an integrated circuit designed to be

configured by the customer or designer after manufacturinghence "field-programmable".
FPGAs are programmable digital logic chips. The FPGA configuration is generally specified
using a hardware description language (HDL), similar to that used for an application-specific
integrated circuit (ASIC).
Before the advent of programmable logic, custom logic circuits were built at the board
level using standard components, or at the gate level in expensive application-specific (custom)
integrated circuits. The FPGA is an integrated circuit that contains many (64 to over 10,000)
identical logic cells that can be viewed as standard components. Each logic cell can
independently take on any one of a limited set of personalities. The individual cells are
interconnected by a matrix of wires and programmable switches. A user's design is implemented
by specifying the simple logic function for each cell and selectively closing the switches in the
interconnect matrix. The array of logic cells and interconnects form a fabric of basic building
blocks for logic circuits. Complex designs are created by combining these basic blocks to create
desired circuit.

Figure 3.1 Comparison of ASIC and FPGA

FPGA BASED STEPPER MOTOR DRIVE

3.1.1 FPGA ARCHITECTURE

Figure 3.2: FPGA Architecture

The architecture of the FPGA is as shown in the figure. It consists of
3.1.1.1 Logic block

3.1.1.2 Routing block

3.1.1.3 Input output or I/O Blocks.
3.1.1.1 Logic block:
Basically the fundamental units of FPGA are a Logic Block. It is programmable in nature
so sometimes it is also called as Programmable Logic Block. Inside these logic blocks additional
digital circuitry is present that makes it actually programmable in nature. Basically a logic block
constitutes of LUTs that stands for Look up Tables. FPGAs are built from one basic "logic-cell",
duplicated hundreds or thousands of time. A logic-cell is basically a small lookup table ("LUT"),
a D-flip-flop and a 2-to-1 mux (to bypass the flip-flop if desired).The LUT is like a small RAM
and has typically 4 inputs, so can implement any logic gate with up to 4-inputs.

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.3: Logic block

3.1.1.2 Routing Blocks

Each logic-cell can be connected to other logic-cells through interconnect resources

(wires/MUXs placed around the logic-cells).

Each cell can do little, but with lots of them connected together, complex logic functions

can be created.
FPGAs also have fast dedicated lines in between neighboring logic cells.
The most common type of fast dedicated lines is carry chains".
Carry chains allow creating arithmetic functions (like counters and adders) efficiently

(low logic usage & high operating speed).

Older programmable technologies (PAL/CPLD) don't have carry chains and so are

quickly limited when arithmetic operations are required.

Also a programmable switch is present in order to switch the interconnections between
various Logic blocks and I/O Blocks.

Figure3.4: Interconnects
3.1.1.3 I/O Blocks
Input Output blocks that are present in the FPGAs acts as an interface to the external
environment, which can help connect FPGAs to the outside world.
8

FPGA BASED STEPPER MOTOR DRIVE

Todays FPGAs provide support for dozens of I/O standards thus providing the ideal
interface bridge in your system. I/O in FPGAs is grouped in banks with each bank independently
able to support different I/O standards. Todays leading FPGAs provide over a dozen I/O banks,
thus allowing flexibility in I/O support.
3.2

XILINX SPARTRAN 3A/3AN STARTER KIT

XILINX invented the FPGA. Basically it is the Technology leader. Its General philosophy
is to provide all the features possible, at the cost of extra complexity. The Spartan 3 FPGA can be
programming directly from the Xilinx ISE package, greatly simplifying and expediting the
design process. Programming the FPGA using a schematic, state diagram, or verilog module is a
universally simple and straightforward process.
The Spartan 3 FPGA board is a robust board containing many features. A list of key
features and their location on the board is listed below, and all of these features are explained in
great detail in the manual provided with the FPGA (UG334).
1. VGA (HD-15) Monitor Port
2. 9-pin (DB-9)
3. Power Connector
4. A1 Expansion Port
5. A2 Expansion Port
6. B1 Expansion Port
7. PS/2 Port
8. Seven Segment Displays
9. Switches (8)
10. Buttons (4)
11. LEDs (8)
12. Power LED

FPGA BASED STEPPER MOTOR DRIVE

13. Spartan 3 FPGA Core

14. Program LED
15. JTAG Port (used to program the FPGA)

Figure 3.5 SPARTRAN 3A/3AN starter kit Overview

Double-check the position of the board jumpers, these settings are required for the
demonstration design to configure correctly.

Optionally connect a VGA display device. The display device can be a CRT, a flat panel,
or even a projector.

Optionally connect headphones or amplified speakers to the audio jack.

Set the SUSPEND switch to the RUN position

10

FPGA BASED STEPPER MOTOR DRIVE

Connect the included AC adapter to wall power and also to the board. The AC adapter
also includes attachments to support worldwide locals.

Turn on the power switch.

The character LCD and VGA display, if connected, display various informational
messages and instructions. If an audio device is connected, the board offers words of
welcome in a variety of languages.

Use the rotary/push-button switch to control various board functions.

Optionally connect a PS/2-style keyboard to support one of the included demonstrating

designs.

3.2.1

Optionally connect a PC directly to the board using a standard 9-pin serial cable.

Switch

3.2.1.1 Slide Switches

11

FPGA BASED STEPPER MOTOR DRIVE

The Spartan - 3A/3AN FPGA Starter Kit board has four slide switches. The slide
switches are located in the lower right corner of the board and are labelled SW3 through SW0.
Switch SW3 is the left-most switch, and SW0 is the right-most switch.

. Figure 3.6: Four Slide Switches

When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low.
The switches typically exhibit about 2 ms of mechanical bounce. There is no active debouncing
circuitry, although such circuitry could easily be added to the FPGA design programmed on the
board.
The UCF constraints for the four slide switches, including the I/O pin assignment and the
I/O standard used. The PULLUP resistor is not required, but it defines the input value when the
switch is in the middle of a transition.
NET "SW" LOC = "V8" | IOSTANDARD = LVCMOS33;
NET "SW" LOC = "U10"| IOSTANDARD = LVCMOS33;
NET "SW" LOC = "U8" | IOSTANDARD = LVCMOS33;
NET "SW" LOC = "T9" | IOSTANDARD = LVCMOS33;
3.2.1.2 SUSPEND Switch

12

FPGA BASED STEPPER MOTOR DRIVE

The SUSPEND slide switch connects directly to the FPGAs SUSPEND input pin. If
Suspend mode is enabled in the FPGA application, then the FPGA enters Suspend mode
whenever the switch is set to SUSPEND. If the switch is then changed back to RUN, then
the FPGA resumes operation from the state before it entered Suspend mode. Likewise, if
Suspend mode is enabled, then the AWAKE pin is reserved to indicate when the FPGA is in
Suspend mode.

Figure 3.7: Suspend Switch

To enable Suspend mode, add the configuration string CONFIG ENABLE_SUSPEN =
FILTERED to the user constraints file (UCF). If Suspend mode is not enabled in the
application, then the SUSPEND switch has no effect on the design and the AWAKE pin is
available as a general purpose I/O.
3.2.1.3 Push-Button Switches
The Spartan-3A/3AN Starter Kit board has four momentary-contact push-button
switches. The push buttons are located in the lower right corner of the board and are labeled

13

FPGA BASED STEPPER MOTOR DRIVE

BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins that connect to
the push buttons appear in parentheses and the associated UCF.
NET "BTN_EAST" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "BTN_NORTH" LOC = "T14" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "BTN_SOUTH" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "BTN_WEST" LOC = "U15" | IOSTANDARD = LVCMOS33 | PULLDOWN;

Figure 3.8: Four Push-Button Switches Surround the Rotary Push-Button Switch

3.2.2 LED
3.2.2.1 Discrete LEDs
The Spartan-3A/3AN Starter Kit board has eight individual surface-mount LEDs located
immediately above the slide switches. The LEDs are labeled LED7 through LED0. LED7 is the
left-most LED, LED0 the right-most LED.
14

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.9: Eight Discrete LEDs

Each LED has one side connected to ground and the other side connected to a pin on the
device via a 390 current limiting resistor. To light an individual LED, drive the associated
FPGA control signal High. If the FPGA is not yet configured, the LEDs may be dimly lit because
pull-up resistors are enabled during configuration. The FPGAs PUDC_B pin is connected to
GND on the board.
The UCF constraints for the four push-button switches, including the I/O pin assignment,
the I/O standard used, the output slew rate, and the output drive current. Optional Discrete
LEDs.The Spartan-3A/3AN Starter Kit board provides two optional LEDs. Depending on which
features are used by an application, these LED connections may be also used as user-I/O pins.
UCF Constraints for Eight Discrete LEDs
NET "LED" LOC = "W21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "LED" LOC = "Y22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "LED" LOC = "V20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "LED" LOC = "V19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
15

FPGA BASED STEPPER MOTOR DRIVE

NET "LED" LOC = "U19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;

NET "LED" LOC = "U20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "LED" LOC = "T19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "LED" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
3.2.2.2 Optional Discrete LEDs
The Spartan-3A/3AN Starter Kit board provides two optional LEDs. Depending on which
features are used by an application, these LED connections may be also used as user-I/O pins.

Figure 3.10: AWAKE and INIT_B LEDs

3.2.2.3 AWAKE LED

The yellow-coloured AWAKE LED connects to the FPGAs AWAKE pin and is used if
the FPGA Suspend mode is enabled in the bitstream. If the Suspend mode is not used, then the
FPGAs AWAKE pin is available as a full user-I/O pin.

16

FPGA BASED STEPPER MOTOR DRIVE

If the FPGA is not yet configured, the FPGAs AWAKE pin is dimly lit because pull-up
resistors are enabled during configuration. The FPGAs PUDC_B pin is connected to GND on
the board. To light the AWAKE LED in an application, drive the AWAKE pin High.
3.2.2.4 INIT_B LED
The red-coloured INIT_B LED serves multiple purposes:

At power-up or when the PROG_B button is pressed, the LED flashes momentarily

while the FPGA clears its configuration memory.

If configuration fails for any reason, then the FPGAs DONE LED will be unlit and
the INIT_B LED will light. This indicates that the FPGA could not successfully

configure.
After the FPGA successfully completes, the INIT_B pin is available as a general
purpose user-I/O pin. If no signal drives INIT_B, then it is defined as an input pin
with a pull-down resistor. It might appear that the LED dimly glows. Drive the

INIT_B pin High to turn off the LED or Low to light the LED.
If using the Read back CRC feature, the INIT_B pin is reserved and signals a CRC
error after configuration. If such an error occurs, the FPGA drives INIT_B Low,
lighting the LED.

If using the INIT_B pin as a user-I/O pin after configuration, drive the pin Low to light
the LED and High to shut it off. Jumper J46, shown in Table 4-2, page 40, must be in either the
Disabled or Enabled during Configuration setting.
The Always Enabled setting for Jumper J46 allows the FPGA to read additional data
from the Platform Flash PROM after configuration
3.2.3 Clock sources
The Spartan-3A/3AN FPGA Starter Kit board supports three primary clock input sources
The board includes an on-board 50 MHz clock oscillator.
Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA can
generate clock signals or other high-speed signals on the SMA-style connector.

17

FPGA BASED STEPPER MOTOR DRIVE

A 133 MHz clock oscillator is installed in the CLK_AUX socket. Optionally substitute a
separate eight-pin DIP-style clock oscillator in the provided socket.
Each of the clock inputs connect directly to a global buffer input. As shown in Table 3-1,
each of the clock inputs also optimally connects to an associated DCM.
Only the CLK_AUX or the CLK_SMA input can use the associated DCM at any time.
However, both inputs are available as clock inputs

Figure 3.11: Clock Sources on Starter Kit Board

18

FPGA BASED STEPPER MOTOR DRIVE

Clock Input
CLK_50MHZ
CLK_AUX
CLK_SMA

FPGA Pin

I/O Bank

E12
V12
U12

Global Buffer

0
2
2

GCLK5
GCLK2
GCLK3

Associated
DCM
Top Right
Bottom Right
Bottom Right

LOC
DCM_X2Y3
DCM_X2Y0
DCM_X2Y0

Table 3.1: Clock Inputs and Associated Global Buffers and DCMs.

3.2.3.1 50 MHz On-Board Oscillator

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The
oscillator is accurate to 2500 Hz or 50 ppm.
3.2.3.2 Auxiliary Clock Oscillator Socket
A 133 MHz clock oscillator is installed in the auxiliary clock oscillator socket. The
provided eight-pin socket accepts clock oscillators that fit the eight-pin DIP (8DIP) footprint.
Substitute the oscillator in this socket if the FPGA application requires a frequency other than 50
MHz or 133 MHz. alternatively, use the FPGAs Digital Clock Manager (DCM) to generate or
synthesize other frequencies from the on-board 50 MHz or 133 MHz oscillator.
3.2.3.3 SMA Clock Input or Output Connector
To provide a clock from an external source, connect the input clock signal to the SMA
connector. The FPGA can also generate a single-ended clock output or other high-speed signal on
the SMA clock connector for an external device.
3.2.4 FPGA Configuration Options
The Spartan-3A/3AN FPGA Starter Kit board supports a variety of FPGA configuration
options:

19

FPGA BASED STEPPER MOTOR DRIVE

Program the Spartan-3AN internal SPI Flash memory, then configure the FPGA at

power-up. This option is not available in the Spartan-3A Starter Kit.

Download FPGA designs directly to the Spartan-3A/3AN FPGA via JTAG, using the
on-board USB interface. The on-board USB-JTAG logic also provides in-system
programming for the on-board Platform Flash PROM. SPI serial Flash and Strata

Flash programming are performed separately.

Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then
configure the FPGA from the image stored in the Platform Flash PROM using Master

Serial mode.
Program the on-board 16 Mbit STMicroelectronics SPI serial Flash PROM or the 16
Mbit Atmel SPI-based Data Flash PROM, then configure the FPGA from the image
stored in the SPI serial Flash PROM using SPI mode. Further, an FPGA application
can dynamically load different FPGA configurations using the FPGAs Multi Boot

mode.
Program the on-board 32 Mbit STMicroelectronics parallel NOR Flash PROM, then
configure the FPGA from the image stored in the Flash PROM using BPI Up
configuration mode. Further, an FPGA application can dynamically load different
FPGA configurations using the FPGAs Multi Boot mode.

20

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.12: Starter Kit FPGA Configuration Options

The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed. The DONE pin LED lights
when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA
to restart its configuration process. The Xilinx Platform Flash PROM provides easy, JTAGprogrammable configuration storage for the FPGA. The FPGA configures from the Platform
Flash using Master Serial mode.
3.2.4.1 Programming the FPGA or Platform Flash PROM via USB
The Spartan-3A/3AN Starter Kit includes embedded USB-based programming logic and
a USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the
iMPACT programming software directly programs the FPGA, the Platform Flash PROM, or the
on-board CPLD. Direct programming of the parallel or serial Flash PROMs is not presently
supported.
3.2.4.2 Connecting the USB Cable
21

FPGA BASED STEPPER MOTOR DRIVE

The kit includes a standard USB Type A/Type B cable. The actual cable color might vary
from the picture.

Figure 3.13: Standard USB Type A/Type B Cable

The wider and narrower Type A connector fits the USB connector at the back of the
computer.
After installing the Xilinx software, connect the square Type B connector to the Spartan3A/3AN Starter Kit board. The USB connector is on the left side of the board, immediately next
to the Ethernet connector. When the board is powered on, the Windows operating system
automatically recognizes and installs the associated driver software.

22

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.14: Connect the USB Type B Connector to the Starter Kit Board Connector
When the USB cable driver is successfully installed and the board is correctly connected
to the PC, a green LED lights up, indicating that the programming cable is ready. The USB
connection also has a red LED, which only lights if the Xilinx software is programming
firmware updates to the USB interface.
3.2.5 Expansion Connectors
The Spartan-3A/3AN FPGA Starter Kit board provides a variety of expansion
connectors for easy interface flexibility to other off-board components. The board includes the
I/O expansion headers.
A Hirose 100-pin edge connector with 43 associated FPGA user-I/O pins
Two stake pin headers, each that supports up to five differential data channels plus a
differential clock or 12 single-ended I/O signals
Two six-pin Peripheral Module connections, plus mounting holes for a third module.
Landing pads for an Agilent or Tektronix connector less probe.

23

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.15: Expansion Headers

3.2.5.1 Hirose 100-Pin FX2 Edge Connector (J17)
A 100-pin edge connector is located along the right edge of the board. This connector is a
Hirose FX2-100P-1.27DS header with 1.27 mm pitch. Throughout the documentation, this
connector is called the FX2 connector.

24

FPGA BASED STEPPER MOTOR DRIVE

.
Figure 3.16: FPGA Connections to the Hirose 100-Pin Edge Connector
Three signals are reserved primarily as clock signals between the board and FX2
connector, although all three connect to full I/O pins.
The Spartan-3A/3AN Starter Kit board provides power to the Hirose 100-pin FX
connector and any attached board via two supplies (see Figure 15-2). The 5.0V supply provides a
voltage source for any 5V logic on the attached board or alternately provides power to any
voltage regulators on the attached board.
A separate supply provides the same voltage as that applied to the FPGAs I/O Banks 0, 1,
and 2 called VCCO_012. This supply is 3.3V by default. All FPGA I/Os that interface to the
Hirose connector are in Bank 0 or Bank 1. For improved signal integrity, a majority of pins on
the B side of the FX2 connector are tied to GND.
The FX2 connect has two rows of connectors, both with 50 connections each, shown in
the table using light yellow shading. The pin assignment for the connector is identical to that
used on the Spartan-3E Starter Kit board, although the Spartan-3E board pinout includes a few
input-only pins. The Spartan- 3A/3AN Starter Kit board pin assignment uses only full I/O pins
and are backwards compatible with the Spartan-3E Starter Kit board
25

FPGA BASED STEPPER MOTOR DRIVE

Shared

FX2 Connector
B

Signal Name

FPGA Pin

J34

A (top) (bottom)

FPGA
Pin

Signal Name

Supply to FPGA

I/O Banks 0, 1, 2

VCCO_012

VCCO_012

TMS_B

TDO_XC2C

JTSEL

TCK_B

TDO_FX2

GND

GND

SHIELD
GND

GND

FX2_IO1

A13

GND

GND

FX2_IO2

B13

GND

GND

FX2_IO3

A14

GND

GND

FX2_IO4

B15

GND

GND

FX2_IO5

A15

10

10

GND

GND

FX2_IO6

A16

11

11

GND

GND

FX2_IO7

A17

12

12

GND

GND

FX2_IO8

B17

13

13

GND

GND

FX2_IO9

A18

14

14

GND

GND

FX2_IO10

C18

15

15

GND

GND

FX2_IO11

A19

16

16

GND

GND

FX2_IO12

B19

17

17

GND

GND

FX2_IO13

A20

18

18

GND

GND

FX2_IO14

B20

19

19

GND

GND

FX2_IO15

C19

20

20

GND

GND

FX2_IO16

D19

21

21

GND

GND

FX2_IO17

D18

22

22

GND

GND

FX2_IO18

E17

23

23

GND

GND

FX2_IO19

D20

24

24

GND

GND

FX2_IO20

D21

25

25

GND

GND

FX2_IO21

D22

26

26

GND

GND

FX2_IO22

E22

27

27

GND

GND

26

FPGA BASED STEPPER MOTOR DRIVE

Shared

FX2 Connector
A (top)

B
(bottom)

FPGA
Pin

Signal Name

F18

28

28

GND

GND

F19

29

29

GND

GND

FX2_IO25

F20

30

30

GND

GND

FX2_IO26

E20

31

31

GND

GND

FX2_IO27

G20

32

32

GND

GND

FX2_IO28

G19

33

33

GND

GND

FX2_IO29

H19

34

34

GND

GND

FX2_IO30

J18

35

35

GND

GND

FX2_IO31

K18

36

36

GND

GND

FX2_IO32

K17

37

37

GND

GND

FX2_IO33

K19

38

38

GND

GND

FX2_IO34

K20

39

39

GND

GND

FX2_IO35

L19

40

40

GND

GND

FX2_IO36

L18

41

41

GND

GND

FX2_IO37

M20

42

42

GND

GND

FX2_IO38

M18

43

43

GND

GND

FX2_IO39

L20

44

44

GND

GND

FX2_IO40

P20

45

45

GND

GND
FX2_CLKIN

Signal Name

FPGA Pin

FX2_IO23
FX2_IO24

J34

GND

GND

46

46

M22

FX2_CLKOUT

L22

47

47

GND

GND

GND

GND

48

48

L21

FX2_CLKIO

5.0V

49

49

5.0V

5.0V

50

50

SHIELD

Table 3.2: Hirose 100-Pin FX2 Connector Pinout and FPGA Connections (J17)
3.2.5.2 Differential I/O Connectors
The Spartan-3A/3AN Starter Kit board includes stake pin headers with excellent signal
integrity and matched impedance traces to demonstrate high-performance differential I/O. Each
differential pair supports approximately 600 Mbits per second (Mbps) data rates. All I/O pairs
support differential input termination (DIFF_TERM) as described in the Spartan-3A and
Spartan-3AN data sheets.
The board is primarily designed to support loopback operations using a standard 34-pin
socket-to-socket cable.
The two differential I/O headers consist of a 2x17 array of stake pins arrange on 0.1-inch
centers. The headers are not keyed. Ground pins are interspersed with the signal pins for
27

FPGA BASED STEPPER MOTOR DRIVE

improved signal integrity over any attached cable. Power is also supplied, via the nominally 3.3V
rail, labeled VCCO_012. The power connectors are for potential daughter cards that plug into the
connector.
The J15 connector is primarily designed to transmit output data while the J2 connector is
primarily designed to receive input data. However, both headers are equally good at transmitting
differential data. The Receive header does have special provisions for capturing the receive
clock input.
The pin assignment for the J2 Receive connector. The FPGA ball assignment is listed in
parentheses.

Table 3.3: Receive Header (J2)

Table 3.4: Transmit Header (J15)

Differential Pair

Signal Name

FPGA
Ball

FPGA Pin Name

28

Signal Direction

Header.Pi
n

FPGA BASED STEPPER MOTOR DRIVE

Receive Header, J2 (Top Header)
RX_<0>
RX_<1>
RX_<2>
RX_<3>
RX_<4>

RXN_<0>

B4

IO_L31N_0

I/O

J2.6

RXP_<0>

A4

IO_L31P_0

I/O

J2.5

RXN_<1>

A5

IO_L28N_0

I/O

J2.10

RXP_<1>

B6

IO_L28P_0

I/O

J2.9

RXN_<2>

A6

IO_L26N_0

I/O

J2.14

RXP_<2>

A7

IO_L26P_0

I/O

J2.13

RXN_<3>

A8

IO_L22N_0

I/O

J2.22

RXP_<3>

A9

IO_L22P_0

I/O

J2.21

RXN_<4>

C10

IO_L21N_0

I/O

J2.26

RXP_<4>

A10

IO_L21P_0

I/O

J2.25

RX_CLK_N

A11

IO_L18N_0
GLK7

I/O

J2.30

RX_CLK_P

A12

IO_L18P_0
GCLK8

I/O

J2.29

TXN_<0>

AA3

IO_L03N_2

I/O

J1..6

TXP_<0>

AB2

IO_L03P_2

I/O

J1.5

TXN_<1>

AA4

IO_L04N_2

I/O

J1.10

TXP_<1>

AB3

IO_L04P_2

I/O

J1.9

TXN_<2>

AB6

IO_L08N_2

I/O

J1.14

TXP_<2>

AA6

IO_L08P_2

I/O

J1.13

TXN_<3>

AB7

IO_L10N_2

I/O

J1.22

TXP_<3>

Y7

IO_L10P_2

I/O

J1.21

TXN_<4>

AB8

IO_L12N_2

I/O

J1.26

TXP_<4>

AA8

IO_L12P_2

I/O

J1.25

TX_CLK_N

AB10

IO_L15N_2

I/O

J1.30

TX_CLK_P

AA10

IO_L15P_2

I/O

J1.29

RX_CLK

Transmit Header J15 (Bottom Header)

TX_<0>
TX_<1>
TX_<2>
TX_<3>
TX_<4>
TX_CLK

Table 3.5: Differential I/O Connections and Header Connections

3.2.6 Six-Pin Accessory Headers:

29

FPGA BASED STEPPER MOTOR DRIVE

The six-pin accessory headers provide easy I/O interface expansion using the various
Digilent Peripheral Modules.
3.2.6.1 J18 Header:
The J18 header is located in the bottom right corner of the board, along the right edge,
adjacent to the BTN_EAST push button. It uses a female six-pin 90 socket. Four FPGA pins
connect to the J18 header, J18_IO<4:1>. The board supplies 3.3V to the accessory board
mounted in the J18 socket on the bottom pin.

Figure 3.17: FPGA Connections to the J18 Accessory Header

3.2.6.2 J19 Header
The J19 header is left unpopulated on the board. Four FPGA pins connect to the J19
header, J19_IO<4:1>. The board supplies 3.3V to the accessory board mounted in the J19
socket on the bottom pin.

Figure 3.18: FPGA Connections to the J19 Accessory Header

30

FPGA BASED STEPPER MOTOR DRIVE

3.2.6.3 J20 Header

The J20 header is the top-most six-pin connector along the right edge of the board. It
uses a female six-pin 90 socket. Four FPGA pins connect to the J20 header, J20_IO<4:1>. The
board supplies 3.3V to the accessory board mounted in the J20 socket on the bottom pin.

Figure 3.19: FPGA Connections to the J20 Accessory Header

3.2.7 Voltage Supplies

The voltage supplies are located in the upper left corner of the board

31

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.20: Spartan-3A/3AN Starter Kit Board Voltage Supplies

The Spartan-3A/3AN FPGA Starter Kit board requires a 5.0V DC voltage input,
typically supplied by the AC wall adapter included with the kit. However, there is also a
provision to connect the board directly to a 5.0V DC supply using through-hole mounting solder
pads.
The AC wall adapter must be a regulated 5.0V DC supply, as supplied with the kit. Some
components and interfaces on the board, such as the LCD character display and the PS/2 port are
powered directly from the 5.0V supply rail.
The 5.0V input voltage is then converted to the other supply voltages required by the
board component. All non-5V voltages are supplied by two space-efficient and cost-effective
National Semiconductor LP3906 Quad-Output voltage regulators. Each regulator incorporates
32

FPGA BASED STEPPER MOTOR DRIVE

two high-current switching (buck) regulators and two low-drop out (LDO) linear regulators.

Series
Voltage

Regulator

Regulator

Output

Voltage Level

Component
s Supplied

Jumper
Control

FPGA internal
core voltage,
SW1

1.2V

J9

SW2

3.3V

J10

National
Semiconductor

CCINT
FPGA I/O
Banks 0, 1, and
2
(VCCO_0,
VCCO_1, and
VCCO_2). All
3.3V

LP3906
Components.
(IC19)

FPGA internal
auxiliary
LDO1

3.3V

J11

LDO2

1.8V

J12

voltage, VCCAUX
Embedded
USB
programmer
DDR2
SDRAM
termination

SW1

0.9V

J40
Network

National

SW2

1.8V

J13

Semiconductor
LP3906

LDO1

3.3V

J41

33

DDR2
SDRAM
component,
FPGA I/O
Bank 3
(VCCO_3)
Voltage
reference to

FPGA BASED STEPPER MOTOR DRIVE

converter
channels C and
D.
(IC18)
DDR2
SDRAM
voltage

1.8V

LDO2

(voltage
divided

J42

to 0.9V)

reference,
FPGA I/O
Bank 3
VREF inputs
(VREF_3)

Table 3.6: Voltage Regulators and Supply Rails

The board exploits all four regulator outputs for testing and evaluation purposes.
However, a typical Spartan-3A/3AN FPGA application uses far fewer rails.

The board uses a separate supply for VCCAUX and sets it to 3.3V by default. In a
typical application, the FPGAs VCCAUX supply could connect directly to the 3.3V

supply used for FPGA I/O Banks 0, 1, and 2.

By default, the VCCAUX supply is set to 3.3V
Using the I2C interface on regulator IC19, VCCAUX can be reduced to 2.5V to

reduce overall power consumption or to verify operation with VCCAUX = 2.5V.

The DDR2 SDRAM interface uses multiple regulator outputs to test voltage

margining.
One high-current 1.8V rail supports the DDR2 SDRAM component itself, and

supplies the FPGAs I/O Bank 3, which connects to the DDR2 SDRAM.
One high-current 0.9V supplies the DDR2 SDRAM termination network.

A low-current 1.8V supply is voltage divided with resistors to provide a highaccuracy 0.9V voltage reference for the DDR2 SDRAM component and to supply
the VREF inputs on FPGA I/O Bank 3.

34

FPGA BASED STEPPER MOTOR DRIVE

3.3 MCT2E Opto-coupler:

Opto coupler is used as interface between IR sensor and FPGA board. We use this
because the logic levels of IR sensor and that of FPGA are different. FPGA logic 0 is 0V and
logic 1 is 3.3v where as IR sensors logic 0 is 0V and logic 1 is 5V hence in order to make both
of them compatible with each other we use this opto coupler.
3.3.1 Description:
Standard Single Channel Phototransistor Couplers. The MCT2/ MCTE family is an
Industry Standard Single Channel Phototransistor. Each optocoupler consists of gallium arsenide
infrared LED and a silicon NPN phototransistor. These couplers are Underwriters Laboratories
(UL) listed to comply with a 5300 VRMS isolation test voltage. This isolation performance is
accomplished through Vishay double moulding isolation manufacturing process. Compliance to
DIN EN 60747-5-2(VDE0884)/ DIN EN 60747-5-5 pending partial discharge isolation
specification is available for these families by ordering option 1.
These isolation processes and the Vishay ISO9001 quality program results in the highest
isolation performance available for a commercial plastic phototransistor optocoupler. The
devices are available in lead formed configuration suitable for surface mounting and are
available either on tape and reel, or in standard tube shipping containers.
3.3.2 Features of MCT2E
Interfaces with common logic families
Input-output coupling capacitance < 0.5 pF
Industry Standard Dual-in line 6-pin package
5300 VRMS isolation test voltage

3.3.3 Applications of MCT2E

AC mains detection
35

FPGA BASED STEPPER MOTOR DRIVE

Reed relay driving

Switch mode power supply feedback
Telephone ring detection
Logic ground isolation
Logic coupling with high frequency noise rejection

Figure 3.21: MCT2E chip

Figure 3.22 pin diagram of MCT2E

3.3

ULN2003A:
When pulses are sent from fpga to stepper motor ,the pins at which pulses are going will

not have enough current level to drive the motor and hence level of current must be increased

36

FPGA BASED STEPPER MOTOR DRIVE

and therefore we use ULN2003A to amplify current level. This has Darlington pair which
increases current levels.
3.4.1

DESCRIPTION:
The ULN2001A, ULN2002A, ULN2003 andULN2004A are high voltage, high current

Darlington arrays each containing seven open collector Darlington pairs with common emitters.
Each channel rated at 500mA and can withstand peak currents of 600mA. Suppression diodes are
included for inductive load driving and the inputs are pinned opposite the outputs to simplify
board layout.
These versatile devices are useful for driving a wide range of loads including solenoids, relays
DC motors, LED displays filament lamps, thermal pinheads and high power buffers. The
ULN2001A/2002A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper
lead frame to reduce thermal resistance. They are available also in small outline package (SO-16)
as ULN2001D/2002D/2003D/2004D.

Figure 3.23 ULN2003A chip

3.4.2

Features of ULN2003A:
Seven Darlingtons per package output current 500mA per driver.
(600mA peak) output voltage 50v integrated suppression diodes.
Inductive loads outputs can be paralleled.
Higher current TTL/CMOS/PMOS/DTL compatible inputs pinned opposite outputs.
Simplify layout.

37

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.24: Pin diagram of ULN2003A

Figure 3.25: Schematic of ULN2003A

38

FPGA BASED STEPPER MOTOR DRIVE

Table 3.7: Absolute maximum rating

39

FPGA BASED STEPPER MOTOR DRIVE

Table 3.8: Electrical characteristics

3.5 Stepper Motor and Drive:
A stepper motor is a brushless, synchronous electric motor that converts digital pulses
into mechanical shaft rotation. Every revolution of the stepper motor is divided into a discrete
number of steps, in many cases 200 steps, and the motor must be sent a separate pulse for each
step. The stepper motor can only take one step at a time and each step is the same size. Since
each pulse causes the motor to rotate a precise angle, typically 1.8, the motor's position can be
controlled without any feedback mechanism. As the digital pulses increase in frequency, the step
movement changes into continuous rotation, with the speed of rotation directly proportional to
the frequency of the pulses. Step motors are used every day in both industrial and commercial
applications because of their low cost, high reliability, high torque at low speeds and a simple,
rugged construction that operates in almost any environment.

40

FPGA BASED STEPPER MOTOR DRIVE

Figure 3.26: stepper motor

3.5.1 Stepper Motor Advantages:

The rotation angle of the motor is proportional to the input pulse.

The motor has full torque at standstill (if the windings are energized).
C 9Precise positioning and repeatability of movement since good stepper motors have an

accuracy of 3 to 5% of a step and this error is non-cumulative from one step to the next.
Excellent response to starting/stopping/reversing.
Very reliable since there are no contact brushes in the motor. Therefore the life of the step

motor is simply dependent on the life of the bearing.

The stepper motors response to digital input pulses provides open-loop control, making

the motor simpler and less costly to control.

it is possible to achieve very low speed synchronous rotation with a load that is directly

coupled to the shaft.

A wide range of rotational speeds can be realized as the speed is proportional to the
frequency of the input pulses.

3.5.2 Types of Step Motors:

There are three basic types of step motors: variable reluctance, permanent magnet, and
hybrid. This discussion will concentrate on the hybrid motor, since these step motors combine
the best characteristics of the variable reluctance and permanent magnet motors. They are
constructed with multi-toothed stator poles and a permanent magnet rotor. Standard hybrid
motors have 200 rotor teeth and rotate at 1.8 step angles. Because they exhibit high static and
dynamic torque and run at very high step rates, hybrid step motors are used in a wide variety of
41

FPGA BASED STEPPER MOTOR DRIVE

commercial applications including computer disk drives, printers/plotters, and CD players. Some
industrial and scientific applications of stepper motors include robotics, machine tools, pick and
place machines, automated wire cutting and wire bonding machines, and even precise fluid
control devices.
3.5.3 Step Modes:
Stepper motor "step modes" include Full, Half and Micro step. The type of step mode
output of any stepper motor is dependent on the design of the driver.
3.5.3.1FULLSTEP
Standard hybrid stepping motors have 200 rotor teeth, or 200 full steps per revolution of the
motor shaft. Dividing the 200 steps into the 360 of rotation equals a 1.8 full step angle.
Normally, full step mode is achieved by energizing both windings while reversing the current
alternately.
3.5.3.2 HALF STEP
Half step simply means that the step motor is rotating at 400 steps per revolution. In this
mode, one winding is energized and then two windings are energized alternately.
3.5.3.3 MICROSTEP:
Micro stepping is a relatively new stepper motor technology that controls the current in the
motor winding to a degree that further subdivides the number of positions between poles.
Omegamation micro stepping drives are capable of dividing a full step (1.8) into 256 micro
steps, resulting in 51,200 steps per revolution (.007/step). Micro stepping is typically used in
applications that require accurate positioning and smoother motion over a wide range of speeds.
Like the half-step mode, micro stepping provides approximately 30% less torque than full-step
mode.
3.5.4 Linear Motion Control
The rotary motion of a stepper motor can be converted to linear motion using a lead
screw/worm gear drive system .The lead, or pitch, of the lead screw is the linear distance travel
for one revolution of the screw. If the lead is equal to one inch per revolution, and there are 200

42

FPGA BASED STEPPER MOTOR DRIVE

full steps per revolution, then the resolution of the lead screw system is 0.005 inches per step.
Even finer resolution is possible by using the step motor/drive system in micro stepping mode.
3.5.5 Series vs. Parallel Connection:
There are two ways to connect a stepper motor, in series or in parallel. A series
connection provides a high inductance and therefore greater torque at low speeds. A parallel
connection will lower the inductance which results in increased torque at faster speeds.

Figure 3.27: Series vs. Parallel Connection

3.5.6 Driver Technology Overview

The stepper motor driver receives step and direction signals from the indexer or control
system and converts them into electrical signals to run the step motor. One pulse is required for
every step of the motor shaft. In full step mode, with a standard 200-step motor, 200 step pulses
are required to complete one revolution. The speed of rotation is directly proportional to the
pulse frequency. Some drivers have an on-board oscillator which allows the use of an external
analog

signal.
Speed and torque performance of the step motor is based on the flow of current from the

driver to the motor winding. The factor that inhibits the flow, or limits the time it takes for the
current to energize the winding, is known as inductance. The effects of inductance, most types of
driver circuits are designed to supply a greater amount of voltage than the motor's rated voltage.
The higher the output voltage from the driver, the higher the level of torque vs. speed. Generally,

43

FPGA BASED STEPPER MOTOR DRIVE

the driver output voltage (bus voltage) should be rated at 5 to 20 times higher than the motor
voltage rating. In order to protect the motor from being damaged, the step motor drive should be
current-limited to the step motor current rating.
3.5.7 Choosing a Stepper Motor and Drive
The choice of a step motor depends on the application's torque and speed requirements.
Use the motor's torque-speed curve (found in each drive's specifications, example in figure C) to
select a motor that will do the job. Every stepper drive in the Omegamation line shows the
torque-speed curves for that drive's recommended motors. If your torque and speed requirements
can be met by multiple step motors, choose a drive based upon the needs of your motion systemstep/direction, stand-alone programmable, analog inputs, micro stepping- then choose one of the
recommended motors for that drive. The recommended motor list is based on extensive testing
by the manufacturer to ensure optimal performance of the step motor and drive combination.

44