1.Define the jobs performed by the BIU and EU in the 8086.

The functions performed by the Bus interface unit are:

- The BIU is responsible for the external bus operations.
- It performs fetching, reading, writing for memory as well as I/O of data for peripheral devices.
- The BIU also performs address generation and the population of the instruction queue.
The Execution unit is responsible for the following work:
- The instructions are decoded and executed by it.
- The EU accepts instructions from the instruction queue and from the general purpose registers
it takes data.
- It has no relation with the system buses.

2.What are the conditions under which the EU enter into the WAIT mode?

The EU goes into the WAIT mode in the following three conditions:
- If an instruction requires an access to a memory location which is not present in the queue the
EU enters into the WAIT state.
- The EU enters into the WAIT mode when a JUMP instruction is executed. In such cases the
existing queue contents are removed the EU waits for more instructions
from the new address in the memory.
- Certain instructions can take quite some time to execute in such cases the EU again goes into
the WAIT state. For cases such as these the BIU waits till the EU is able
to extract some bytes from the queue.

3.Explain briefly how the register in the 8086 are grouped together?

The 8086 in total consists of 14 16 bit registers. They are grouped together in the following way:
- All the registers are divided into the following groups: Data, Pointers and Index group, segment
group and status and control flag group.
- The accumulator AX, base BX, count CX and data DX account for the data registers.
- The stack pointer SP, base pointer BP, source index SI, Destination index DI and the Instruction
painter IP are the pointer registers.
- The Extra segment, code segment and stack segment are in the segment group of registers
- A single 16 bit flag register is present in the Control flag group.

4.Mention briefly the advantages of memory segmentation in 8086?

Some of the advantages of memory segmentation in the 8086 are as follows:

- With the help of memory segmentation a user is able to work with registers having only 16-bits.
- By memory segmentation the various portions of a program can be of more than 68kb.
- The data and the users code can be stored separately allowing for more flexibility.
- Also due to segmentation the logical address range is from 0000H to FFFFH the code can be
loaded at any location in the memory.

5.Briefly explain the logical address, base segment address and physical address.

- Logical address is contained in the 16-bit IP, BP, SP, BX, SI or DI. It is also known as the offset

address or the effective address.

- The base segment address is contained in one of the 16bit contents of the segment registers CS,
DS, ES, SS.
- The physical address or the real address is formed by combining the offset and base segment
addresses. This address is 20bit and is primarily used for the accessing
of the memory.

6.Mention the different types of instructions responsible for data transfer

instructions.

The following are the different types of instructions:

- Move byte or word instructions: they are used to perform primarily the move function on words
/ bytes
- Exchange byte or word instructions: as their name suggests they are used to perform exchange
operations
- Translate byte instructions: used for transfer purposes.
- Load effective address instructions: used to calculate the effective address and load it to
memory.
- Load data segment instructions: used for loading purposes.
- Load extra segment instructions: used for special instructions such as span etc.

7.Mention the characteristics of the CMP instructions.

The various characteristics of the Compare (CMP) instruction are as follows:

- The CMP instruction can be used to compare two 8-bit or two 16-bit numbers.

- Whenever a compare operation is performed the result of such an operation reflects in one of
the six status flags CF, AF, OF, PF, SF and ZF.
-The CMP operation is also known as the subtraction method as it uses two`s complement for it.
- The result of a CMP operation is never saved but corresponding to the result of the instruction
the flag statuses may be changed or reset.
- The operands of CMP instruction may reside in the memory or can be a component of an
instruction.

8.Point out the major differences in Short label and Near label jump instructions.

The characteristics of Short Label instructions are:

- This type of instruction relative to the jump instruction address specifies the jump.
- The new value of an IP is specified with an 8-bit operand.
- From the location of the jump instruction the range in which this instruction can be used is
between -126 to +129 bytes.
The characteristics of Near Label instructions are as follows:
- For Near label instruction the address of the jump is specified in relative terms to the jump
instruction itself.
- The new values of Ip is specified with a sixteen-bit operand.
- This type of instruction covers the complete range of the code segment currently used.

9.Point out the differences between the NMI and INTR?

The characteristics of NMI are as follows:

- They are also known as the non-maskable types.
- They are always give higher priorities over the INTR.
- The interrupt is edge triggered specifically Low to High transition.
- In order to function they must remain high for at least 2 cycles of CLK.
- These interrupts do not send out any form of acknowledgements.
The characteristics of INTR are:
- They are also known as the maskable types of interrupts.
- They have a lower priority as compared to NMI.
- These interrupts are level triggered and not edge triggered.
- These interrupts do not support latching and must remain high till the CPU acknowledges them
to do so.

10.Explain briefly in steps what happens when an interrupt occurs.

The following steps occur when an interrupt occurs ( both for hardware and software )
- First thing the contents of the flag register the CS and IP are pushed into the stack.
- To disable the single steps and INTR interrupts the TF and IF are cleared.
- The program then jumps to the beginning or starting address of the ISS.

- When the IRET gets executed in the last line ( this occurs at the end of the ISS) the CS and IP
flag contents are popped from the stack and placed in the appropriate registers.
- Once all the flags are restored to their original condition the IF and TF are also restored to their
previous values.

11.List out the differences between Isolated I/O and Memory mapped I/O.

The characteristics of isolated I/O are as follows:

- The devices of I/O are treated in a separate domain as compared to memory.
- A total of 1mb address space is allowed for memory applications.
- In order to maximize the I/O operations ( isolated ) separate instructions are always provided to
perform these operations.
- One of the disadvantages is that the data transfer only occurs between the I/O port and the AL,
AX registers.
The characteristics of the memory mapped I/O are as follows:
- In such scenarios the devices (I/O) are treated as a part of the memory only.
- Complete 1mb of memory cannot be used as they are a part of the memory.
- In case of memory mapped I/O operations no external separate instructions are required.
- There is data transfer restriction in case of memory mapped instructions.

12.Mention the internal interrupts characteristics.

Some of the characteristics of internal interrupts are as follows:

- The type of code of an interrupt is either predefined or can be contained within the instruction
itself.
- In case of INTR interrupt inputs the generation of complementary INTA bus cycles are not
generated.
- No internal interrupt can be disabled in the case of such interrupts barring single step interrupts.
- Priority Wise always the internal interrupts barring single step interrupts are always given
higher priority as compared to external interrupts.

13.Explain the types of interrupts from Type 0 to 4 briefly.

The following are the various types of interrupts:

- Type 0 interrupts: This interrupt is also known as the divide by zero interrupt. For cases where
the quotient becomes particularly large to be placed / adjusted an error might occur.
- Type 1 interrupts: This is also known as the single step interrupt. This type of interrupt is
primarily used for debugging purposes in assembly language.
- Type 2 interrupts: also known as the non-maskable NMI interrupts. These type of interrupts are
used for emergency scenarios such as power failure.
- Type 3 interrupts: These type of interrupts are also known as breakpoint interrupts. When this
interrupt occurs a program would execute up to its break point.
-Type 4 interrupts: Also known as overflow interrupts is generally existent after an arithmetic
operation was performed.

14.Briefly explain the three different types of control flags for the 8086.

- The 8086 has three control flags namely TF, IF and DF. All three of them can be user
programmed to suit their needs.
- The trap flag allows the cpu to run in a single stepping mode. This comes in very handy in
debugging and development purposes.
- The interrupt flag causes the INTR ( maskable interrupt ) to be enabled else it would remain
disabled. Whenever the cpu is reset so is IF reset / cleared.
- In string operations primarily the Direction flag is used. The STD instruction is responsible for
the setting of the DF.

15.Briefly explain the Pointers and Index group of registers.

- Stack pointer and base pointer are the two pointer registers whereas the Source index and
Destination index are the index group of registers.
- They are primarily used to store relative to segment registers the locations of offset addresses of
memory locations. They serve the purpose of being memory pointers.
- The source index and destination index are also used as general purpose register. In such cases
the SI and DI are implemented as source and destination index registers.
- In stacks, data areas might exist, to be able to access such data which contains the BP register.

15.Explain the two types of conditional jumps.

- The two types of unconditional jumps are intersegment and intrasegment jumps.
- In the case of intrasegment jumps as the name suggest is a special type of jump in which the

address to which the jump is to be performed is present / lies in the same code segment from
where the jump is performed from. In order to perform this jump changes just need to be made in
the Instruction pointer.
- In the case of intersegment jumps the jump takes place from one segment to another. In order to
be able to make these kinds of jumps the changes need to be made in both the code segment and
the instruction pointer.