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Atrenta, Inc.
2077 Gateway Place
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Atrenta Inc, 2013 | All rights reserved
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INTRODUCTION
Todays system-on-a-chip (SoC) designs are creating more challenges than ever
challenges that demand bringing the product to market faster, before the
competition does. The electronics industry and growing competition require that
SoCs achieve a short time to market (TTM) while design complexity continues to grow
at a rapid rate. Another challenge is to keep the SoC design and overall product
costs as low as possible.
How can design companies meet such challenges as TTM, design complexity and
competitive differentiation while keeping costs down? With ever-shortening TTM, one
way is through IP reuse. This implies building a solid, extensible architectural platform
and deriving newer platforms from it as per the application needs, which reduces
design time and increases success rate. There is a need to address the difficulties that
design companies are facing today to create derivative designs. As we are in the
era of highly complex giga-scale products, the error margin or the tolerance guard
band is getting tighter and tighter with respect to previous design approaches.
Conventional chip assembly processes are largely manual, or home grown
script-based, which takes a lot of man hours (even months) and still are not error free.
So what we need is an automated, reliable and flexible solution to accomplish the
necessary tasks in the shortest possible time. An ideal solution will contain hooks to
capture and modify the existing design to drive new functionality. The solution will
enable the designer to increase the abstraction level of connectivity, manipulate the
design hierarchy and perform IP selection. Furthermore, the solution should make use
of a standard database to improve interoperability and ease design handoff.
As the popularity of reusing existing designs or intellectual property (IP) blocks
continues to grow, design challenges escalate. As time to market pressures and
product complexities increase, the pressure to reuse complex building blocks
increases significantly. The solution to the productivity problem is increasing the
abstraction level in design technology and introducing tools to support re-use of
components and system parts. Apart from existing methodologies, one new
approach is to create derivative designs on top of existing ones, which is called
derivative design methodology.
A modern SoC may contain 500 or more IPs (including integration logic), many of
which may have 100 or more ports. Designers have already realized that creating,
reviewing and maintaining 50,000 connections in HDL through a text editor is
exceptionally painful. The experimental results on real applications show that the
proposed approach is effective in making derivative design on the top of an existing
one. Here, we are considering the inputs to be expressed at the register transfer level
(RTL) or in IP-XACT format, which form the reference specification for design
modifications. We will cover each step of a derivative design flow one-by-one.
The migration from an existing design to a derivative design requires smoothly cruising
along many milestones. Success of the previous milestone becomes a prerequisite to
enter the next one. These milestones typically revolve around careful IP selection,
mapping IP ports to interfaces, glue logic management, hierarchy manipulation and
finally archiving and exporting all the modifications as a new-born design. Another
dimension of the problem that makes these milestones even more complex is the
Atrenta Inc, 2013 | All rights reserved
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meaningful integration of elements, which could be part RTL, part IP-XACT, part XML
or some other format that do not easily gel well with the others.
DERIVATIVE DESIGN FLOW
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HIERARCHY MANIPULATION
Performing hierarchy manipulation without an automated tool is a very tedious and
error-prone task. Even though it often seems like it may be a simple movement of an
instance across a hierarchy, it can often consume several hours or even days when
done manually. One challenge here is to preserve connectivity across hierarchies as
well as the creation of new ports and interfaces at intermediate hierarchies after the
movement. Another challenge is to preserve attributes and the type of connectivity
model while creating or dissolving a hierarchy. The change in an existing hierarchy is
again a very highly error-prone task and requires a lot of human dedication to avoid
a mistake. The process of debugging any problems introduced accidentally after
hierarchy manipulation is again a very time consuming activity for the designer.
Automation for performing hierarchy manipulation is the only solution to handle the
complexity around making such changes in hierarchy while ensuring errors are not
being introduced.
DATABASE MANAGEMENT
Databases are designed to offer an organized mechanism for storing, managing
and retrieving information. The main aim here is to improve the flow of information
between IP vendors and between EDA tools by defining the interfaces provided by
that IP in a standardized form such as IP-XACT, Tcl, etc. An automated mechanism is
required to convert the design into a standard database accurately and efficiently.
THE ATRENTA SOLUTION
Atrentas GenSys Assembly solution automatically reads in an existing design in the
form of RTL or a standard database like IP-XACT to derive newer functionality as
shown in the detailed derivative design flow in Figure 2.
The GenSys Assembly RTL import utility helps to bring the design database into a new
structured object model, which is more flexible, reliable, and user-friendly to make
changes according to derivative design specification in a very interactive way.
The RTL import feature will extract the top-level abstraction (peripheral part) and
populate the GenSys database while maintaining the low level abstraction
(behavioral part) in terms of glue logic at the same location. Glue logic needs to be
retained throughout the flow for later usage.
During this RTL read process, one block will be created for all assignment/tie-off
statements. For each process/concurrent statement in the RTL, there will be a
separate block at each level of hierarchy in the design.
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Once the interfaces are inferred, only a generator run is required to quickly infer
interface connections throughout the design. At any point in time, the user can
generate the interface summary report to review the higher level of abstraction
statistics.
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CONCLUSION
GenSys by Atrenta is a framework for creating a derivative design while boosting
productivity in terms of quick iterative cycles while eliminating errors in the design.
A derivative design flow requires an assembly framework with the following attributes:
Atrentas GenSys solution covers all the above attributes and more. It has been
successfully used to tape out many chips at leading semiconductor companies. It
ensures a valid and well-managed derivative design approach.
ABOUT ATRENTA
Atrentas SpyGlass Predictive Analysis software platform significantly improves
design efficiency for the worlds leading semiconductor and consumer
electronics companies. Patented solutions provide early design insight into
the demanding performance, power and area requirements of the complex
system on chips (SoCs) fueling todays consumer electronics revolution. More
than two hundred companies and thousands of design engineers worldwide rely
on SpyGlass to reduce risk and cost before traditional EDA tools are deployed.
SpyGlass functions like an interactive guidance system for design engineers and
managers, finding the fastest and least expensive path to implementation for
complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
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