EE6502 MICROPROCESSORS AND MICROCONTROLLERS

OBJECTIVES:
To study the Architecture of P8085 & C 8051
To study the addressing modes & instruction set of 8085 & 8051.
To introduce the need & use of Interrupt structure 8085 & 8051.
To develop skill in simple applications development with programming
8085 & 8051
To introduce commonly used peripheral / interfacing
UNIT I 8085 PROCESSOR 9
Hardware Architecture, pin outs Functional Building Blocks of Processor Memory
organization I/O ports and data transfer concepts Timing Diagram Interrupts.
UNIT II PROGRAMMING OF 8085 PROCESSOR 9
Instruction -format and addressing modes Assembly language format Data transfer, data
manipulation & control instructions Programming: Loop structure with counting & Indexing
Look up table - Subroutine instructions - stack.
UNIT III 8051 MICRO CONTROLLER 9
Hardware Architecture, pin outs Functional Building Blocks of Processor Memory
organization I/O ports and data transfer concepts Timing Diagram Interrupts-Comparison
to Programming concepts with 8085.
UNIT IV PERIPHERAL INTERFACING 9
Study on need, Architecture, configuration and interfacing, with ICs: 8255,
8254,8237,8251,8279, - A/D and D/A converters &Interfacing with 8085 & 8051.

8259,

UNIT V MICRO CONTROLLER PROGRAMMING & APPLICATIONS 9

Data Transfer, Manipulation, Control Algorithms& I/O instructions Simple programming
exercises key board and display interface Closed loop control of servo motor- stepper motor
control Washing Machine Control.
TOTAL: 45 PERIODS
OUTCOMES:
Ability to understand and analyse, linear and digital electronic circuits.
To understand and apply computing platform and software for engineering
problems.
TEXT BOOKS:
1. Krishna Kant, Microprocessor and Microcontrollers, Eastern Company Edition, Prentice
Hall of India, New Delhi, 2007.
2. R.S. Gaonkar, Microprocessor Architecture Programming and Application, with 8085, Wiley
Eastern Ltd., New Delhi, 2013.
3. Soumitra Kumar Mandal, Microprocessor & Microcontroller Architecture, Programming &
Interfacing using 8085,8086,8051,McGraw Hill Edu,2013.
REFERENCES:
1. Muhammad Ali Mazidi & Janice Gilli Mazidi, R.D.Kinely The 8051 Micro Controller and
Embedded Systems, PHI Pearson Education, 5th Indian reprint, 2003.
2. N.Senthil Kumar, M.Saravanan, S.Jeevananthan, Microprocessors and Microcontrollers,
Oxford, 2013.

3. Valder Perez, Microcontroller Fundamentals and Applications with Pic, Yeesdee

Publishers, Tayler & Francis, 2013.

UNIT I 8085 PROCESSOR 9

Hardware Architecture, pin outs Functional Building Blocks of Processor Memory
organization I/O ports and data transfer concepts Timing Diagram Interrupts.
1.1 Hardware Architecture & Functional Building Blocks of Processor
1.2 Pin Outs
1.3 Memory organization
1.4 I/O ports and data transfer concepts
1.5 Timing Diagram
1.6 Interrupts
1.1 Hardware Architecture
MICROPROCESSOR 8085 Hardware Architecture

8085 Bus Structure

Address Bus

The address bus is a group of 16 lines generally identified as A 0 to A15.

The address bus is unidirectional: bits flow in one directionfrom the MPU to
peripheral devices.

The MPU uses the address bus to perform the first function: identifying a
peripheral or a memory location.

8085 Bus Structure

Data Bus

The data bus is a group of eight lines used for data flow.
These lines are bi-directional - data flow in both directions between the MPU
and memory and peripheral devices.
The MPU uses the data bus to perform the second function: transferring
binary information.
The eight data lines enable the MPU to manipulate 8-bit data ranging from 00
to FF (28 = 256 numbers).
The largest number that can appear on the data bus is 11111111.

Control Bus

The control bus carries synchronization signals and providing timing signals.
The MPU generates specific control signals for every operation it performs.
These signals are used to identify a device type with which the MPU wants to
communicate.

Registers of 8085

The 8085 have six general-purpose registers to store 8-bit data during
program execution.
These registers are identified as B, C, D, E, H, and L.
They can be combined as register pairsBC, DE, and HLto perform some
16-bit operations.

Accumulator (A)

The accumulator is an 8-bit register that is part of the arithmetic/logic unit

(ALU).
This register is used to store 8-bit data and to perform arithmetic and logical
operations.
The result of an operation is stored in the accumulator.

Flags

The ALU includes five flip-flops that are set or reset according to the result of
an operation.
The microprocessor uses the flags for testing the data conditions.
They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC)
flags. The most commonly used flags are Sign, Zero, and Carry.
The bit position for the flags in flag register is,
D7
D6
D5
D4
D3
D2
D1
D0
S

AC

CY

1. Sign Flag (S):

i.
After execution of any arithmetic and logical operation, if D 7 of the
result is 1, the sign flag is set. Otherwise it is reset.
ii.
D7 is reserved for indicating the sign; the remaining is the magnitude
of number.
iii.
If D7 is 1, the number will be viewed as negative number. If D 7 is 0, the
number will be viewed as positive number.
2. Zero Flag (z): If the result of arithmetic and logical operation is zero, then
zero flag is set otherwise it is reset.
3. Auxiliary Carry Flag (AC): If D3 generates any carry when doing any
arithmetic and logical operation, this flag is set. Otherwise it is reset.
4. Parity Flag (P): If the result of arithmetic and logical operation contains
even number of 1s then this flag will be set and if it is odd number of 1s it
will be reset.
5. Carry Flag (CY): If any arithmetic and logical operation result have any
carry then carry flag is set otherwise it is reset.
Arithmetic and Logic Unit (ALU)
It is used to perform the arithmetic operations like addition, subtraction,
multiplication, division, increment and decrement and logical operations like
AND, OR and EX-OR.
It receives the data from accumulator and registers.
According to the result it set or reset the flags.
Program Counter (PC)
This 16-bit register sequencing the execution of instructions.
It is a memory pointer. Memory locations have 16-bit addresses, and that is
why this is a 16-bit register.

The function of the program counter is to point to the memory address of the
next instruction to be executed.
When op code is being fetched, the program counter is incremented by one
to point to the next memory location.

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer.
It points to a memory location in R/W memory, called the stack.
The beginning of the stack is defined by loading a 16-bit address in the stack
pointer (register).
Temporary Register: It is used to hold the data during the arithmetic and logical
operations.
Instruction Register: When an instruction is fetched from the memory, it is
loaded in the instruction register.
Instruction Decoder: It gets the instruction from the instruction register and
decodes the instruction. It identifies the instruction to be performed.
Serial I/O Control: It has two control signals named SID and SOD for serial data
transmission.

Timing and Control unit

It has three control signals ALE, RD (Active low) and WR (Active low) and
three status signals IO/M (Active low), S0 and S1.
ALE is used for provide control signal to synchronize the components of
microprocessor and timing for instruction to perform the operation.
RD (Active low) and WR (Active low) are used to indicate whether the
operation is reading the data from memory or writing the data into memory
respectively.
IO/M (Active low) is used to indicate whether the operation is belongs to the
memory or peripherals.
If,
IO/M(Acti
Data Bus
S1
S2
ve Low)
Status(Output)
0
0
0
Halt
0
0
1
Memory WRITE
0
1
0
Memory READ
1
0
1
IO WRITE
1
1
0
IO READ
0
1
1
Opcode fetch
Interrupt
1
1
1
acknowledge

Interrupt Control Unit: It receives hardware interrupt signals and sends an acknowledgement
for receiving the interrupt signal.

1.2 Pin Outs & Signals

PIN DETAILS OF 8085
1.
2.
3.
4.
5.
6.

The signals can be grouped as follows

Power supply and clock signals
Address bus
Data bus
Control and status signals
Interrupts and externally initiated signals
Serial I/O ports

1. Power supply and Clock frequency signals:

Vcc + 5 volt power supply
Vss
Ground
X1, X2: Crystal or R/C network or LC network connections to set the
frequency of internal clock generator.
The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally.
CLK (output)-Clock Output is used as the system clock for peripheral and
devices interfaced with the microprocessor.

Pin Diagram of 8085

2. Address Bus

Logical Schematics of 8085

A8 A15 (output; 3-state)

It carries the most significant 8 bits of the memory address or the 8 bits of
the I/O address;

3. Multiplexed Address / Data Bus

AD0 AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as
well as data bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver
the lower order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as
data bus.
The CPU may read or write out data through these lines.
4. Control and Status signals
ALE (output) - Address Latch Enable.
This signal helps to capture the lower order address presented on the
multiplexed address / data bus.
RD (output 3-state, active low) Read memory or IO device.
This indicates that the selected memory location or I/O device is to be
read and that the data bus is ready for accepting data from the memory or I/O
device.
WR (output 3-state, active low) - Write memory or IO device.
This indicates that the data on the data bus is to be written into the
selected memory location or I/O device.
IO/M (output) - Select memory or an IO device.
This status signal indicates that the read / write operation relates to
whether the memory or I/O device.
It goes high to indicate an I/O operation.
It goes low for memory operations.
5. Status Signals
It is used to know the type of current operation of the microprocessor.
IO/M(Acti
ve Low)
0
0
0
1
1
0

S
1
0
0
1
0
1
1

Data Bus Status

(Output)
0
Halt
1
Memory WRITE
0
Memory READ
1
IO WRITE
0
IO READ
1
Op code fetch
Interrupt
1
1 1
acknowledge
6. Interrupts and externally initiated operations:
They are the signals initiated by an external device to request the
microprocessor to do a particular task or work.
There are five hardware interrupts called,
S2

On receipt of an interrupt, the microprocessor acknowledges the interrupt by

the active low INTA (Interrupt Acknowledge) signal.

Reset In (input, active low)

This signal is used to reset the microprocessor.
The program counter inside the microprocessor is set to zero.
The buses are tri-stated.
Reset Out (Output)
It indicates CPU is being reset.
Used to reset all the connected devices when the microprocessor is reset.
7. Direct Memory Access (DMA)
Tri state devices:

3 output states are high & low states and additionally a high impedance
state.
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if
A is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled
and the output Q enters into a high impedance state.
E
A
Q
State
1(hig
0
1
High
h)
1
1
0
Low
0(low
0
0
High impedance
)
0
1
0
High impedance
For both high and low states, the output Q draws a current from the input of
the OR gate.
When E is low, Q enters a high impedance state; high impedance means it is
electrically isolated from the OR gates input, though it is physically
connected. Therefore, it does not draw any current from the OR gates input.
When 2 or more devices are connected to a common bus, to prevent the
devices from interfering with each other, the tri state gates are used to
disconnect all devices except the one that is communicating at a given
instant.

The CPU controls the data transfer operation between memory and I/O
device. Direct Memory Access operation is used for large volume data
transfer between memory and an I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected
directly by external control circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this
signal, the microprocessor acknowledges the request by sending out HLDA
signal and leaves out the control of the buses. After the HLDA signal the DMA
controller starts the direct transfer of data.

READY (input)
Memory and I/O devices will have slower response compared to
microprocessors.
Before completing the present job such a slow peripheral may not be able to
handle further data or control signal from CPU.
The processor sets the READY signal after completing the present job to
access the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
8. Single Bit Serial I/O ports:
SID (input)
- Serial input data line
SOD (output)
- Serial output data line

These signals are used for serial communication.

1.3 Memory interfacing

Interfacing Memory with 8085

A microprocessor will have its own address space for accessing physical memory. The memory
locations that are directly addressed by the microprocessor is called physical memory space.
For example a microprocessor like 8085 has 16 address lines, and it can access a physical
memory space of 64K starting from 0000H to FFFFH as shown in Table 1.3.1. The
process of interfacing memories to microprocessor and allocating address to each memory
location is called memory mapping. The complete address space may be considered as a
single memory block. But practically, when ICs are used as memory devices, instead of a
single IC (Integrated Chip), few devices that fit into the address space will be used. This is
due to the fact a microprocessor based system requires at least one ROM/EPROM and a
RAM. For example instead of using a memory device of size 64KB (Kilo Bytes), we can use
8 memory devices with a capacity of 8KB each. This will reduce the chip replacement cost
while servicing the microprocessor-based system. When memory blocks are used, to access all
the locations in a block n address lines are needed so that

n
2 =8K
3
=2 K
3
10
=2 x2
= 213
Therefore n = 13
Address Decoding and memory mapping
Memory address decoding is nothing but to assign an address for each location in the memory
chip. The data stored in the memory is accessed by specifying its address. Memory address
can be decoded in two ways
i)
Absolute or Fully decoding
and
ii)
Linear Select or Partial decoding
There are many advantages in absolute address decoding. They are
i
Each memory location has only one address, there is no duplication in the
address
ii
Memory can be placed contiguously in the address space of the
microprocessor
iii
Future expansion can be made easily without disturbing the existing
circuitry
There are few disadvantages in this method
i
Extra decoders are necessary
ii
Some delay will be produced by these extra decoders.
The main advantage of linear select decoding is its simplified decoding circuit. This reduces
the hardware design cost. But there are many disadvantages in this decoding.
i
Multiple addresses are provided for the same location
ii
Complete memory space of the microprocessor is not efficiently used
iii
Adding or interfacing ICs with already existing circuitry is difficult.
Absolute Address Decoding
16
The 8085 microprocessor has 16 address lines. Therefore it can access 2
locations in the
physical memory. If all these lines are connected to a single memory device, it will decode
16
these 16 address lines internally and produces 2 different addresses from 0000H to FFFFH
so that each location in the memory will have a unique address as shown in table 1 . 3.1 and
figure 1 . 3.1. This is called absolute address decoding. Figure 1 . 3.1 is called the memory
map of 8085 address space and it shows how each location in the physical memory gets
an address from the address space of the microprocessor.
A15 A14 A13
0
0 0
0

A11 A10 A9
0 0 0 0

A7 A6 A5 A4 A3 A2
A0 Hex Address
0 0 0 0 0 0 0 0
0000H

0
0

0
0
-

1
1

0
0
-

1
1

0
0

0
0

1
1

0
0
-

1
1

1
1

0
0
-

1
1

0
0

0
0

0
0
-

0
0
-

0
0
-

0
0
-

0 0
0 1
- - -

1
1 1 1
1 1 1 1
1
1 1 1
1 1 1 1
Table 1.3.1: Memory Address

1
1

1
0

0001H
0002H
- - - - -

0
1

FFFEH
FFFFH

Figure 1.3.1: 64KB Memory Map (Single Block)

Instead of connecting all the 16 address lines to a single 64 KB memory device, we can also
use memory devices of lower capacity. In such cases the physical memory space of the
microprocessor is divided into smaller memory spaces or memory blocks. Each block is
selected by a block select address signal and the memory locations with in a block are
accessed by the processors address lines. This is called address portioning. For example if
the memory device (memory block) has only 13 address lines, we can use the lower 13 address
lines (A0 A12) to access the locations with in a memory block and the remaining 3 lines
(A13, A14 and A15) to access 8 such blocks. These three lines are called the block select
address signals and this is called address partitioning. Depending on the number of
memory blocks, the number of block select address lines will change. The starting address
and ending address of each block can be found as shown in Table 1 . 3.2. Since each
block is an Integrated Chip (IC), and each chip has a Chip Select signal, the block select
address lines must be used to select the ICs. We have to produce eight chip select signals
from the three address lines. Therefore we have to decode these lines using a 3 to 8 decoder
or 1 of 8 decoder. In this case the lower thirteen address lines of the processor are connected
to the 13 address lines of the memory chip and hence they are internally decoded in the
memory. The higher 3 address lines (A13, A14 and A15) are externally decoded by a 3 to 8
decoder. Since three lines can provide a maximum of 8 addresses, in this case they are said
to be fully decoded and hence each location in each block has a specific unique address as
shown in table 1.3.2. This is called as absolute address decoding. The diagrammatic
representation of each block with its address range shown in figure 1 . 3.2 is called the
memory map of the microprocessor system.

Bloc
k No A15A14A13
A12
1
0 0 0
0

A11 A10
A9A8
0 0
0

Hex
A7 A6 A5 A4 A3
A1 A0 Address
range
A2
0 0
0 0 0 0 0 0 0000H to

2
3
4
5
6
7
8

0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1FFFH
2000H to
3FFFH
4000H to
5FFFH
6000H to
7FFFH
8000H to
9FFFH
A000H to
BFFFH
C000H to
DFFFH
E000H to
FFFFH

Table 1.3.2: Address Space for Memory Blocks

Figure 3.2: 64KB Memory Map (Eight Blocks)

We use 74LS138 address decoder to generate the chip select signals for each memory
block. In this decoder when the address lines A13, A14 and A15 are 000, the output line
Y0 will be activated as shown in figure 3.3. This in turn selects the first memory block.
Similarly when these lines are 001 (C=0, B=0 and A=1) Y1 will be activated and the
second memory block will be selected. When the 8085 microprocessor is reset the contents of
the program counter will be 0000H. Since this content is placed on the address bus while
accessing the memory, the microprocessor will start executing the program from the address
0000H. A monitor program must be placed starting from this address, so that it reads the
inputs and takes action based on that program. The input may even be a function key that
requires a specific action to be carried over. Since this program is fixed and developed by
the manufactures of the product it is called as firmware and it is stored in a ROM or in an
EPROM. Therefore, in any microprocessor based system an EPROM should be placed at the
reset address (0000H). In addition to EPROM, any microprocessor based system would

require at least few RAM locations to store temporary data. Specifically there should be a
RAM for stack operations. So, though we are using eight memory chips of 8KB size each, at
least one of the eight ICs must be an EPROM and it should be placed at the starting
address of 0000H. The memory map for this case can be given as shown in figure 1.3.2. The
EPROM chip must be selected using the chip select signal CS1 and the RAM1 chip must be
selected using CS2. The memory interface diagram may be given as shown in Figure 1.3.4.

Figure 1.3.3: Memory Block Decoder

In this type of memory interfacing, all the address lines (A0 to A15) have been used. Each
location in the memory will have a single address. This type of address decoding is
called as absolute or fully decoded addressing.
Most of the microprocessor based systems do not use the complete 64 KB memory space.
Even one EPROM and a RAM will be sufficient. For example in the memory map shown
in figure 1 . 3.2, if only the EPROM and RAM 2 are used in the practical system, the
memory map of such a system can be given as shown in figure 1.3.5. Still each location has
single address. Therefore it is also called absolute address decoding. The main advantage of
this type of decoding is, you can add memory devices for this system without disturbing the
already connected devices. The memory interface diagram for this case is given in figure
1.3.6.

1.3.4 Memory interface diagram.

Figure 1.3.5: Memory Map with EPROM and RAM 2

Figure 1.3.6: Interfacing EPROM and RAM

Instead of using 3 to 8 decoder, NAND/AND/OR gates can also be used to generate
chip select signals as shown in figure 3.7. In this case, CS1 will be activated to select the
EPROM, when all the three inputs to the OR gate (OR1) are zero. Similarly the chip select
signal CS3 will be activated to select RAM 2 only when A13 = 0, A14 = 1 and A15 = 0.
This is also an absolute address decoding method. But, here we need more decoders (gates)
when we want to add more memory chips. The main advantage of the absolute address
decoding is the contiguous placement of the memory locations. So no memory space of the
microprocessor is wasted without being used.

Figure 1.3.7: Address Decoding using OR Gates

Linear Select Address Decoding

In the circuit given in figure 1.3.8, the address line A15 of the microprocessor has not been
used for decoding the chip select signals. The outputs Y0 and Y2 of the 74LS138 decoder will
be activated as given in table 1.3.3. Since the address line A15 is not connected to the decoder
and the pin C of the decoder has been grounded, irrespective of the signal A15 (i.e.A15 is 0
or 1), the pin C is 0. So, you will get Y0 selected twice i.e. when A15 = 0 and when A15 = 1.
Similarly Y2 will also be selected twice. Therefore the address map for the EPROM and RAM
is found as shown in Table 1.3.4.
A15 C A14 A13 Y0 Y2
B
A
0
0
0
0
0
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
1
0
Table 1.3.3: Linear Select Address Decoding Chip Select Signals

Figure 1.3.8: Linear Select Address Decoding - Circuit Diagram

Block
No
1

A15 A1 A12 A1 A1 A9 A8 A A
0 0 0 0 0 0 0 0
0 0
0
0

0
1

0
0

1
0

1
0

1
0

1 1
0 0

1 1
0 0

0
1

1
0

0
0

1
0

1
0

1
0

1 1
0 0

1 1
0 0

1
1

0
1

0
0

1
0

1
0

1
0

1 1
0 0

1 1
0 0

1 1

7
1

Hex Address
A5 A4 A3 A A0 range
0 0 0 0 0 0 0000H
to
1 1 1 1 1 1 1FFFH
0 0 0 0 0 0 4000H
to
1 1 1 1 1 1 5FFFH
0 0 0 0 0 0 8000H
to
1 1 1 1 1 1 9FFFH
0 0 0 0 0 0 C000H
to
1 1 1 1 1 1 DFFFH

Table 3.4: Linear Select Decoding Memory Address Ranges

The same EPROM is selected both for the address range 0000H to 1FFFH and 8000H to
9FFFH. This is due to the signals A13 and A14 which have same values in both the cases
and hence activates the same chip select signal CS1. Similarly the RAM is selected both
for the address range 4000H to 5FFFH and C000H to DFFFH. The memory map for this case
is as shown in figure 1.3.9.

Figure 1.3.9: Linear Select Address Decoding Memory Map

Figure 1.3.10: Linear Select Address Decoding using OR gates

In this type of address decoding, if we want to add a RAM chip at the address space
8000H to 9FFFH, which was unnecessarily occupied by the first EPROM, we have to change
the decoding circuit. We may not simply add additional circuitry without disturbing the
already existing circuit. In this method each location in the physical memory is accessed by
more than one address (here two addresses) i.e. address space is wasted. This type of
address decoding is called as Linear Select or partially decoded addressing. This happens
when we have few address lines without being used for decoding. The same circuit can also
be implemented using OR gates as shown in figure
1.3.10. In this circuit the OR gates require only two inputs. This is possible, since we have left
A15 address line unconnected. Therefore, linear select addressing reduces the hardware
requirements.
1.3 . 2 B u s C o n t e n t i o n
Consider the timing diagram shown in figure 1.3.11 that reads a byte (opcode) from the
memory. At the end of the ALE signal, all the 16 bits of the address will be available on the
bus. The decoder (74LS138) produces the chip select signals from these address lines after a
small decoding delay. The chip select signal will be generated with in 30 ns after the trailing
edge of ALE signal. When the chip select signal enables the memory chip, since the address
has been already placed on the address pins of the memory, the memory will place the data
on the data lines after a small access delay called the memory access time. The output buffer
of the memory will be enabled within 20 ns after getting CS signal. The memory access
time is the time delay between the address placed on the address bus by the address decoder
and the data placed by the memory on the data bus. If the data are placed before the end of
the T1 state, both the lower order address and the data from the memory will be placed on the
AD0 AD7 lines i.e. both the microprocessor and the memory try to access the same lines as
shown in figure 1.3.11 by hashed lines. If the microprocessor tries to place 1 (+5V) and
the memory tries to place 0 (0 V or Ground), then the microprocessor pin will be
shorted through the memory. This may even damage the processor. This is called bus
contention. So, the bus contention will occur when two ICs try to place data on the same
bus at the same instant of time. This effect will be very adverse in the case of high speed
memories interfaced with slow processors. Since the RD or WR signal is issued by the
processor only after the first T- state, if these signals are used along with the output of the
address decoders to select the chip, the content of the memory will not be placed before the
start of the T2 state.

Figure 1.3.11: Bus Contention Reading Opcode from the Memory

Figure 1.3.12: Avoiding Bus Contention

By using a standard 3 to 8 decoder as shown in figure 1.3.12, the CS signal can be delayed
until the end of T1 state. The address decoder is enabled by the G3 signal and hence the CS
signal is generated only when RD or WR is low. In figure 1. 3.11, point A activates point B
and point B in turn activates point C to avoid bus contention.
If you are using logic gates to decode the addresses, bus contention may be avoided by
combining the output of the final stage of the decoder with RD or WR signal to produce an
active low chip select signal.

NB: Instead of connecting the RD or WR signals to the input or output of the address
decoder, the best practice to avoid bus contention is to connect the RD signal to the OE pin
of EPROM/RAM and WR signal to R/W pin of RAM.
Example 1 . 3.1:
Interface a 4K EPROM, one 4K RAM and one 8K RAM to a microprocessor with the
following Memory Map.

Figure 3.13: Memory Map

Example 1.2:
How many memory locations will be available if the memory has 16 address lines?
The number of locations that can be accessed by using 16 address lines will be
216 = 65536 locations
Example 1.3:
A memory chip has 10 address lines. What is its storage capacity?
The memory chip which has 10 address lines will have 210 locations. Since each location can
store only one byte of data, the memory capacity will be 210 bytes or 1024 bytes or 1 Kilo Bytes.
Example 1.4:
A memory chip has 16 address lines. What is its storage capacity?
The memory chip which has 16 address lines will have 216 locations. Since each location can
store only one byte of data, the memory capacity will be 216 bytes or (216 = 26 x 210 = 26 KB = 64
KB
NB:
210 = 1024 = 1 Kilo Bytes = 1 KB.
26 = 64
A memory chip select decoder is used to provide chip select signal for each memory
device (IC). This will decide the address range that is allotted for each memory IC. 74LS138
is a 3 to 8 decoder and it can be used for this purpose. In this example the minimum memory
10
block size is 4K. To access 1K locations 10 address lines must be used (2 =1K = 1024
2
10
12
locations). So to access 4K locations (4 X 1K = 2 X 2 = 2 ) 12 address lines (A0

A11) must be used. Since 8085 has 16 address lines the decoding can be indicated as shown
below.

Figure 1.3.14: Variable Address Lines

While accessing 4 K locations the lower 12 bits (A0 A11) can have either 0 or 1. If all the
12 bits are 0 then that will be the starting address of that memory block if all 12 bits are 1 that
will be the end address of the block. The remaining 4 address lines (A12 - A15) are the block
select address signals, which decide the memory block number. For example, if A15 A12
is 0000 then memory block that can be accessed by the remaining address lines is block 0. If
it is 0001 the memory block that can be accessed is 1. Note that the memory blocks 5 and 6
are combined because a 8-K RAM is to be placed there. The following table shows the starting
and ending address of each memory block.

Block No
A1 A1 A1 A12 A1 A1 A A8 A7 A A A4 A3 A
6 5
2
5 4 3
1 0 9
0 0 0 0
0 0 0 0
0 0 0 0
0 0

0
0

0 0 0
0 0 1

1 1 1 1
0 0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

0
0

0 0 1
0 1 0

1 1 1 1
0 0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

0
0

0 1 0
0 1 1

1 1 1 1
0 0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

0
0

0 1 1
1 0 0

1 1 1 1
0 0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

0
0

1 0 0
1 0 1

1 1 1 1
0 0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

1 0 1

1 1

1 1

1 1 1

1 1 1 1
:
:
0
0 0
0

15

1 1
0 0 0

Hex Address
A A0 Range
1
0 0 0000H
to
1 1 0FFFH
0 0 1000H
to
1 1 1FFFH
0 0 2000H
to
1 1 2FFFH
0 0 3000H
to
1 1 3FFFH
0 0 4000H
to
1 1 4FFFH
0 0 5000H
to
1 1 5FFFH

0 0 0 0

F000H

to
1 1 1 1
1 1 1 1
1 1 1 1 FFFFH
Table 3.5: Memory Map
The 74LS138 decoder has three input pins marked as CBA when all these three pins are 0
then the output pin O0 will be activated i.e. O0 becomes zero. When CBA is 001 the O1
will be activated and all other output pins will be at high state. i.e. any one of the output pins
O0 to O7 is selected based on the input A, B and C and this will happen only if the control
pins G1, G2 and G3 are properly activated. Table 3.5 shows that address line A15 is
always zero for the address range 0000H to 6FFFH. So this can be connected to G3 pin of
the 74LS138. The output pins of 74LS138 must be selected only for memory operations.
During memory operations IO/M = 0. So IO/ M is connected to G2 pin of the 74LS138 and
hence for any IO operation the chip 74LS138 will not activate any of the output pins.
The pin G1 is connected to +5V through a resistor to enable 74LS138.
The O0 pin of 74LS138 is connected to the chip select (CS) signal of the 4K EPROM.
This allows selecting this EPROM chip when the microprocessor sends address in the range
0000H to 0FFFH. Similarly O1 pin of 74LS138 is connected to the CS of 4K RAM. Since
no memory chip is connected in the address range 2000H to 3FFFH, the output pin Q2 is
left free. The 8K RAM requires address from 4000H to 5FFFH and these addresses are
covered by Q4 and Q5 pins. So these two pins are connected to a two input AND gate. The
output of the AND gate is connected to the chip select pin of the RAM and this CS will be
activated (active low) if either Q4 or Q5 is low.
i.e. the output of the AND gate will be 0 for the addresses 4000H to 5FFFH and hence the 8K
RAM chip is selected for this address range.
C B A
Output pin Activated
0 0 0
O0
0 0 1
O1
0 1 0
O2
0 1 1
O3
1 0 0
O4
1 0 1
O5
1 1 0
O6
1 1 1
O7
Table 3.1: Function Table of 74LS138
The address lines A0 to A11 of 8085 MPU must be connected to the corresponding address
pins of the memory chip and the data lines D0 to D7 of MPU must be connected to the
corresponding data pins of all the memory chips. Since 8K RAM has 13 address lines in
addition to the twelve address lines (A0 to A11) A12 of MPU must also be connected to
the A12 pin of the 8K RAM. You note that bus contention is not addressed in this circuit.
1

1 1 1

Figure1.3.15: Memory Interfacing

1.3 . 3

Interfacing low speed memory

To avoid bus contention, the RD or WR signal of the microprocessor is used along with
the address decoding to produce the CS signal for the memory. The RD or WR signal starts
approximately in the middle of the T2 state and available up to the end T3 state. If the
microprocessor operates at 3 MHz, these signals are available for approximately 1.5 T state
or 500 ns (1.5 / 3 MHz = 0.5 micro seconds) and hence the memory access time should be
less than 500 ns. If the memory access time is more than this value the data cannot be read.
If a low speed memory has access time greater than this value, Wait cycles are introduced
between T2 and T3. In such a case, the CS select signal need not be delayed until RD or WR
signals are issued by the microprocessor. The memory can decode the address as soon as it gets
the address from the microprocessor. In this case the total delay introduced will be equal to
the sum of the delays introduced by the decoder, wait cycles and the delay introduced due
to memory access time. For example 2716 EPROM has access time of 450 ns and therefore it
can be directly interfaced with 3 MHz 8085, but one wait cycle is necessary if it is
interfaced with a microprocessor operating at 5 MHz. A low speed memory can also be
interfaced with a high speed processor by using low frequency crystal but this will slow down
not only the memory read/write operation but all activities of the processor.
The READY pin of 8085 processor is used to introduce wait states. For normal operations
of the processor this pin should be connected to logic high. When this pin is made low, the
processor will enter into wait state until it is made high again. A special circuitry called Wait
State Generator as shown in figure 1.3.16 is required for this purpose. This circuit will
introduce a wait state equal to one T-state of the processor cycle as shown in figure
1.3.17. The ALE signal fed to the clock input of the first D-type flip-flop will transfer the
logic high input (+5V) placed on its D0 pin to Q0 during its positive edge. The Q0 output is
connected to D1 input of the second flip-flop. So, the logic high output on Q0 will be
transferred to the output Q1 of the second flip-flop during the positive edge of T2 state. The
complement value of Q1 is available on Q1 pin of the second flip-flop. This will reset the

first flip-flop i.e. Q0 will become logic 0 as shown in figure 1.3.17. At the same time since
Q1 has been connected to the READY pin of the processor, the processor enters into wait
state. It will remain in that state until Q1 becomes high. This extends the length of the RD
signal as shown in figure 1.3.17 and allows memory to take one more clock period time to
place the contents on the bus. The logic 0 placed on D1 pin during this time will be transferred
to Q1 in the positive edge of the next clock cycle (T3 state). This will make Q1 logic high
and hence the READY signal becomes high and the processor continues its work. It should be
noted that wait state can be introduced in any machine cycle of 8085 except in bus idle cycle.
The 8085 checks the READY signal at the second T-state of every machine cycle.

Figure 1.3.16: Wait State Generator

Interfacing More than 64K Memory

The 8085 microprocessor can address only 64K memory at a time, if you want to interface
more than 64K memory; you can use a jumper or an IO port bit as shown in figure 1.3.18.

the chip select signal CS3 will select RAM 2 if the jumper connects B and C and it will select
RAM 3 if the jumper connects A and B. Similarly CS4 will select RAM 4 if the port bit is
zero and RAM 5 if the port bit is one. The main difference between jumper selection and
port bit selection is the manual selection in the first case and automatic or program
activated selection in the second case.

Figure 3.18: Interfacing more than 64 K Memory

A microprocessor has address space for memory. Any memory chip that is being
interfaced with processor must fit into this memory space. A memory map diagram
shows the address boundary for each memory chip interfaced with the processor and an
address decoder decides the address range for each chip. There are two types of address
decoding viz absolute address decoding and linear select address decoding. When high
speed memories are interfaced with slow processors bus contention may occur and when a
low speed memory is to be accessed by a fast processors wait state must be introduced
using external circuitry.

1.4 I/O ports and data transfer concepts

8085A family includes memory components, which are directly compatible
to the 8085A CPU. For example, a system consisting of the three chips,
8085A, 8156, and 8355 will have the following features:
2K Bytes ROM
256 Bytes RAM
1 Timer/Counter
4 8bit l/O Ports
1 6bit l/O Port
4 Interrupt Levels
Serial In/Serial Out Ports
In addition to standard l/O, the memory mapped I/O offers an efficient l/O
addressing technique. With this technique, an area of memory address
space is assigned for l/O address, thereby, using the memory address for
I/O manipulation. The 8085A CPU can also interface with the standard
memory that does not have the multiplexed address/data bus.

1.5 Timing Diagram

The sequence of operations that a processor has to carry out for executing the
instruction is called Instruction cycle. Each instruction cycle of a processor consists of a
number of machine cycles. The machine cycle also called as processor cycle is the basic
operation performed by the processor. To execute an instruction, the processor will run
one or more machine cycles in a specific order. A machine cycle will do only one
operation such as memory read, memory write, input port read and output port write. The
8085 microprocessor uses seven types of machine cycles i.e. opcode fetch cycle, memory
read, memory write, I/O read, I/O write, interrupt acknowledge and bus idle machine
cycles as shown in table 2.2. In general, the instruction cycle of an instruction can be
divided into fetch and execute cycles. The fetch cycle reads the opcode from memory.
The execute cycle is executed to decode the instruction and to perform the work
instructed by the instruction. A system designer uses the status signals to track the
internal operations of the processor and to expand the memory of the system. It
differentiates an opcode from address or data. It is also used to identify whether a
machine cycle is read cycle or write cycle. In 8085 microprocessor, a machine cycle can
have maximum of 6 T-states and an instruction cycle can have a maximum of 5 machine
cycles.
Machine Cycle
Status
No. of T
Control
IO/M
S1
S0
states
Signals
Opcode Fetch
0
1
1
4 RD=0
Memory Read
0
1
0
3 RD=0
Memory Write
0
0
1
3 WR=0
I/O Read
1
1
0
3 RD=0
I/O Write
1
0
1
3 WR=0
INTR Acknowledge
1
1
1
3 INTA=0
Bus Idle
0
0
0
3
Let the instruction MVI A, 9AH be stored in the memory as follows.
Address
4100
4101

Opcode
3E
9A

Mnemonic
MVI A, 9AH

The Timing diagram shown in figure 2.8 indicates that the MVI A, 9AH instruction
stored at the address 4100H is executed with two machine cycles i.e. one Opcode
Fetch cycle and one Memory Read cycle. The opcode fetch cycle uses 4 clock signals
(T1, T2, T3 and T4) and memory read cycle uses 3 clock signals. Each clock signal (a
logic low part and a logic high part) is called a T-State. So an opcode fetch machine
cycle has 4T states. Generally the opcode fetch cycle of any 8085 instruction uses 4T
states. But some instructions like INX H uses 6T states for opcode fetch.
All operations with in 8085 are synchronized with the clock signal. The frequency of the
clock signal depends on the crystal connected with 8085. If a 6 MHz crystal is
connected, a 3 MHz clock will be generated i.e. the clock is internally divided by 2. This
3 MHz clock is called the operating frequency of the Microprocessor. In the above

example the instruction is executed using 7 T-stats. If F is the operating frequency in Hertz
and T is the time taken by a T-state then,
T = 1/ F Seconds----------------------------------------------------------------2.1

If an instruction has N number of T-states, then the execution time for that instruction is
given by
Execution Time = N x T Seconds------------------------------------------2.2
In the above example the operating frequency is 3MHz; therefore each T-state will have
6
a time equal to 1/3MHz i.e. 1/3x10 seconds or 1/3 micro seconds. Hence this instruction
will be executed in 7 x 1/3 microseconds.
The table given below shows the status signals for each type of machine cycle and the
number of T-stats required for each machine cycle.
Opcode Fetch Cycle

At T1 state of figure 2.8, the microprocessor starts the process of reading the first byte of
an instruction (opcode) stored in the memory and it sets the signals IO/M=0, S1=1,
S0=1 to indicate an Opcode Fetch cycle (refer Table 2.2 for the states of these signals
for other operations). The Microprocessor places the higher order byte of the address
(41H) on the address lines A15 A8 and the lower order address on the multiplexed lines
AD7 - AD0. Since this address exists only during T1 period this address must be captured
and stored using an external latch as explained in section 2.3.1. So the ALE (Address
Latch Enable) signal is generated during this T1 time, which is used to enable the
external latch to capture the address and this signal is disabled at the end of the T1 as
shown in figure 2.8.
At T2 state, the processor issues a RD signal which enables the memory to place the data
(stored in the address provided during T1 state) on AD7 - AD0 lines. This data goes in
to the instruction register. At T2 state the program counter is incremented by one. The RD
signal extends up to the end of T3 state. The arrow marks indicate that the point at the tail
activates point at the head i.e. until the tail point occurs the head point is blocked.
This is necessary because the memory should not place the opcode immediately after it
receives the address; it should be sufficiently delayed otherwise both address and opcode
will be placed at the same time on the same lower order data lines during T1 state.
At T4 state 8085 microprocessor decodes the opcode and finds out that a second byte
(data 9AH) is to be read from the memory. During this time the contents of the bus A15
A8 are not important and the data bus AD7 AD0 goes in to high impedance state (Hi Z
state). High impedance state indicates that AD7 AD0 pins of the Microprocessor isolates
it from other ICs such as memory and ports.
The status signals for opcode fetch cycle will be set to IO/M =0 S0 = 1 and S1 =1 as per
the details given in table 2.2.
Memory Read cycle

The second machine cycle of this instruction is Memory Read cycle. This cycle consists
of 3T states.
At T1 state of this cycle, Microprocessor issues IO/M=0, S1=1, S0=0. Microprocessor
places the next memory address 4101H on the bus i.e. the microprocessor places the higher
order address 41H on the bus lines A15 A8 and the lower order address 01H on AD7
AD0 lines and makes ALE signal high to latch the lower order address.
At T2 state ALE will be in deactivated state. So the lower order address latched already
will be available on the output of the latch but the lines AD7 AD0 need not have that
address. At the rising edge of T2 state the memory places the data (9AH) stored in the

corresponding address (4101H) on AD7 AD0 lines. At the same time the
Microprocessor issues read signal (RD becomes 0) and the program counter is
automatically incremented by one.
At T3 state 8085microprocessor reads the data from AD7 AD0 bus and stores it in the
accumulator.
The status signals for memory read cycle will be set to IO/M =0 S1 = 1 and S0 =0 as per
the details given in table 2.2.
NB: Memory Write machine cycle will be generated when the microprocessor wants to
store any byte in the memory. In this cycle instead of RD signal, the microprocessor issues
WR signal and data flows from microprocessor to memory. Other operations are same.
You note that when RD signal becomes active i.e. 0, the WR signal will be at logic high
and vice versa. During T1 and T4 states both RD and WR signals will be at logic 1. For
I/O operations IO/M signal will be at logic high, the status signals S0 and S1 will also
change as per the details given in table 2.2. More examples on timing diagram can be
found in chapter 5.
Generally to draw
needed.
a
b
c

the timing diagram of an 8085 instruction, the following information is

Number of bytes in the instruction
Type of machine cycles
Number of T-states in the opcode fetch cycle

Table 2.3 shows some of the important instructions and the machine cycles used for
executing those instructions.
Instruction
(Mnemonic)
STA 4100H

Opcode

Machine Cycles

32 00 41

LXI H, 4567H

21 67 45

MVI A, 80H

3E 80

LHLD 4200H

2A 00 42

OUT 80H

D3 80H

Opcode Fetch
Memory Read
Memory Read
Memory Write
Opcode Fetch
Memory Read
Memory Read
Opcode fetch
Memory Read
Opcode Fetch
Memory Read
Memory Read
Memory Read
Memory Read
Opcode Fetch
Memory Read
I/O Write

Total no. of T
states
4+3+3+3=13

4+3+3=10
4+3=8

4+3+3+3+3=16

4+3+3=10

Call 4300H

CD 00 43

RET

C9

DAD B

09

Opcode Fetch
Memory Read
Memory Read
Memory Write
Memory Write
Opcode Fetch
Memory Read
Memory Read
Opcode Fetch
Bus Idle
Bus Idle

4+3+3+3+3=16

4+3+3=10
4+3+3=10

Table 2.3 Instructions and T-states

The Instruction decoder, ALU, General Purpose Registers, and Timing and
Control Unit are the major logical blocks of any microprocessor architecture.
Flags

are

processor

used

has

for

five

conditional

hardware

execution

of

the

program.

The

8085

interrupts and it also has two pins for

implementing serial data transfer. The data and the lower order address are
time multiplexed. The status signals indicate the type of operation

the

processor is executing. The 8085 microprocessor has a different memory

and I/O address spaces.
1.6 Interrupt structure

An interrupt is a signal or condition that causes processor to stop its normal

execution flow and makes it to jump to some other location for processing the
interrupt.
8085 has 4 mask-able interrupts and 1 non-mask-able interrupts. Mask able
interrupts can be disabled be DI instruction. Among four mask-able interrupts one is
non-vectored interrupt, that is processor cannot go to a fixed location as in case of
vectored interrupt, the external device which caused interrupts needs to specify the
vector address.
8085 interrupt response process:
Interrupts should be enabled by using EI instruction, then only processor
responds to all mask able interrupts.
When microprocessor is executing a program, it checks for INTR line during
execution of each instruction.
If INTR is high then processor completes executing the current instruction,
disables the interrupts and sends a INTA signal

INTA is used by the external hardware to specify the restart instruction to

processor( since INTR is a non-vectored interrupt).
When microprocessor receives the RST instruction, it saves PC content on
stack and PC is loaded with the vector address.
Microprocessor executes the instructions at vector address.
The interrupts should be enabled if required in the ISR(interrupt service
routine)
At the end of interrupt service routine, RET instruction loads the PC from the
stack. So processor comes back to the instruction where it was interrupted
previously.
Restart instructions:
RST n
These instructions are like software interrupts to 8085. When these instructions are
executed processor vectors(jumps) to a specific location called restart location. The
following list gives restart location for different RST instructions.
'n' value -- Vector location -- hex code
RST 0 -- 0000H -- C7
RST 1 -- 0008H -- CF
RST 2 -- 0010H -- D7
RST 3 -- 0018H -- DF
RST 4 -- 0020H -- E7
RST 5 -- 0028H -- EF
RST 6 -- 0030H --F7
RST 7 -- 0038H --FF
To get the vector location 'n' value is multiplied by 8 and the result is converted to
hexadecimal notation. For example RST 3 instruction, multiply 3*8=24. 24 in
hexadecimal notation is 18H. So vector address is 0018H.
8085 has 5 external interrupts. As already mentioned in this 4 are vectored interrupts
and 1 is non-vectored interrupt.
RST 5.5, RST 6.5, RST 7.5, TRAP are vectored interrupts. INTR is non-vectored
interrupt. TRAP is a non mask able interrupt.

Interrupt Priority:
when more than one interrupts occur at the same time, then processor responds to
them according to the following priority
TRAP(highest)
RST 7.5
RST 6.5
RST 5.5
INTR (lowest)
Interrupt vector locations:
TRAP 0024H(it is same as RST 4.5)
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
To get the vector location for RST interrupts, interrupt value is multiplied by 8 and the
result is converted to hexadecimal notation. For example RST 5.5 instruction,
multiply 5.5*8=44. 44 in hexadecimal notation is 2CH. So vector address is 002CH.

Trigger levels:
TRAP is level and edge triggered
RST 7.5 is positive edge triggered
RST 6.5, RST 5.5 are level triggered.
Masking of interrupts:
SIM instruction sets mask pattern for RST 5.5, RST 6.5, RST 7.5.
SIM instructions reads accumulator bit pattern and accordingly masks the interrupts.
The bit pattern is shown in below figure. It also resets D flip-flop of RST 7.5 interrupt.
And it also implements serial I/O.
Hardware interrupts:

An external device initiates the hardware interrupts and placing an

appropriate signal at the interrupt pin of the processor.
If the interrupt is accepted then the processor executes an interrupt
service routine.

The 8085 has five hardware interrupts

(1) TRAP

(2) RST 7.5

(3) RST 6.5

(4) RST 5.5

(5) INTR

TRAP:

This interrupt is a non-maskable interrupt. It is unaffected by any mask or

interrupt enable.
TRAP bas the highest priority and vectored interrupt.
TRAP interrupt is edge and level triggered. This means hat the TRAP must
go high and remain high until it is acknowledged.
In sudden power failure, it executes a ISR and send the data from main
memory to backup memory.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
receives HOLD and TRAP at the same time then HOLD is recognized first
and then TRAP is recognized).
There are two ways to clear TRAP interrupt.
1.By resetting microprocessor (External signal)
2.By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:
The RST 7.5 interrupt is a maskable interrupt.
It has the second highest priority.
It is edge sensitive. ie. Input goes to high and no need to maintain high
state until it recognized.

Maskable interrupt. It is disabled by,

1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.

Enabled by EI instruction.

RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high
and stay high until it recognized.
Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.

Enabled by EI instruction.
The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:

INTR is a maskable interrupt. It is disabled by,

1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.

Enabled by EI instruction.
Non- vectored interrupt. After receiving INTA (active low) signal, it has to
supply the address of ISR.
It has lowest priority.
It is a level sensitive interrupts. ie. Input goes to high and it is necessary
to maintain high state until it recognized.
The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each
instruction.

2. If INTR signal is high, then 8085 complete its current instruction and sends
active low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction
OPCODE on the data bus. In the case of multibyte instruction, additional interrupt
acknowledge machine cycles are generated by the 8085 to transfer the
additional bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on
stack and execute received instruction.
SIM and RIM for interrupts:

The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST
5.5 using SIM instruction.
The status of these interrupts can be read by executing RIM instruction.

The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can
be performed by moving an 8-bit data to accumulator and then executing
SIM instruction.
The format of the 8-bit data is shown below.

The status of pending interrupts can be read from accumulator after

executing RIM instruction.
When RIM instruction is executed an 8-bit data is loaded in accumulator,
which can be interpreted as shown in fig.

UNIT II PROGRAMMING OF 8085 PROCESSOR 9

Instruction - format and addressing modes Assembly language format Data transfer, data
manipulation & control instructions Programming: Loop structure with counting & Indexing
Look up table - Subroutine instructions - stack.

Instruction cycle, Machine cycle, fetch and execute cycles

Instruction cycle
An instruction is a command given to the microprocessor to perform a specific
operation on the given data. Sequence of instructions written for a processor to
perform a particular task is called a program. Program & data are stored in the
memory. The microprocessor fetches one instruction from the memory at a time &
executes it. It executes all the instructions of the program one by one to produce the
final result. The necessary steps that a microprocessor carries out to fetch an
instruction & necessary data from the memory & to execute it constitute an
instruction cycle.
In other words, an instruction cycle is defined as the time required completing the
execution of an instruction.
An instruction cycle consists of a fetch cycle and an execute cycle. The time required
to fetch an opcode (fetch cycle) is a fixed slot of time while the time required to
execute an instruction (execute cycle) is variable which depends on the type of
instruction to be executed.
Instruction cycle(IC) = Fetch cycle (FC) + Execute cycle (EC)
This is shown diagrammatically in the Fig.3.11

Figure 11 Instruction cycle

Machine cycle:
Machine cycle is defined as the time required for completing the operation of
accessing either memory or I/O device. In the 8085, the machine cycle may consist
of three to six T states. The T-state is defined as one sub-division of the operation
performed in one clock period. These sub-divisions are internal states synchronized
with the system clock. In every machine cycle the first operation is op-code fetch and
the remaining will be read or write from memory or IO devices.
Fetch operation:
The first byte of an instruction is its op-code. An instruction may be more than
one byte long. The other bytes are data or operand address. The program counter
(PC) keeps the memory address of the next instruction to be executed. In the
beginning of a fetch cycle the content of the program counter, which is the address of
the memory location where op-code is available, is sent to the memory. The memory
places the op-code on the data bus so as to transfer it to the microprocessor. The
entire operation of fetching an op-code takes three clock cycles.

Execute operation:
The op-code fetched from the memory goes to the instruction register (IR).
From the instruction register it goes to the decoder circuitry which decodes the
instruction. After the instruction is decoded, execution begins. If the operand is in
general purpose registers execution is immediately performed.
The time taken for decoding and execution is one clock cycle. If an instruction
contains data or operand and address which are still in the memory, the
microprocessor has to perform some read operations to get the desired data. After
receiving the data it performs execute operation. A read cycle is similar to a fetch
cycle. In case of a read cycle the quantity received from the memory are data or
operand address instead of an op-code. In some instructions write operation is
performed. In write cycle data are sent from the microprocessor to the memory or an
output device. Thus we see that in some cases an execute cycle may involve one or
more read or write cycles or both.

Instruction set of 8085

An Instruction is a command given to the microprocessor to perform a
given task on specified data. Each instruction has two parts one is the task to be
performed called the operation code (op-code) and the second is the data to be
operated on, known as operand. The operand or data can be specified in various
ways.
Instruction and data formats:
The format of a typical instruction is composed of two parts: an operation
code or op-code and an operand. Every instruction needs an op-code to specify
what the operation of the instruction is and then an operand that gives the
appropriate data needed for that particular operation code.
According to the word or byte size the 8085 instructions are classified into
three types. They are
a) One byte (single) instructions
b) Two byte instructions
c) Three byte instructions
Onebyte instructions: An instruction with only opcode and do not require any dat
or address is called a one byte instruction.
Ex: 1. MOV C, A
2. ADD B
3. CMA

Hex code = 4FH (one byte)

Hex code = 80H (one byte)
Hex code = 2FH (one byte)

Twobyte instructions: At two byte instruction is one which contains an 8-bit opcode and 8-bit operand (Data).
Ex: 1. MVI A, 09
2. ADD B, 07
3. SUB A, 05

Hex code = 3E, 09 (two bytes)

Hex code = 80, 07 (two bytes)
Hex code = 97, 05 (two bytes)

Threebyte instructions: A three byte

bit address.
Ex: 1.LXI H, 8509
2 .LDA 8509
3. JMP 9567
4. STA 3525

instruction contains an opcode plus a 16

Hex code = 21, 09, 85 (Three bytes)

Hex code = 3A, 09, 85 (Three bytes)
Hex code = C3, 67, 95 (Three bytes)
Hex code = 32, 35, 25 (Three bytes)

DATA FORMATS: The 8085 is an 8-bit microprocessor which process only binary
numbers. But it is very difficult to understand these binary numbers by a common
user. So, we have to code these binary numbers into different data formats. The
commonly known data formats are ASCII, BCD, signed integers and unsigned
integers. The ASCII code is a 7-bit alpha-numeric code that represents decimal
numbers, English alphabets and certain special characters. The ASCII stands for
American Standard code for Information Interchange
The term BCD stands for binary coded decimal, used for decimal numbers
from 0-9.An 8-bit register can store two BCD numbers. A signed integer is either a
D7
positive or a negative number. In 8085 microprocessor the most significant bit
is
used for the sign. Here 0 denotes positive sign and 1 denotes the negative sign. An
integer without a sign can be represented by all the 8-bits in a microprocessor
register. So, the largest number that can be processed at one time is FFH. The
numbers larger than 8-bits like 16, 24, 32 bits can be processed by dividing them in
groups of 8-bits.

CLASSIFICATION OF INSTRUCTIONS
An instruction is a binary pattern designed inside a microprocessor to perform
a specific function. The entire group of instructions, called the instruction set,
determines what functions the microprocessor can perform. The 8085
microprocessor instruction set has 74 operation codes that result in 246 instructions.
This instruction set includes all the 8080A instructions plus two additional instructions
namely SIM and RIM.
The instruction set of 8085 microprocessor is classified into five groups. They are:
1. Data transfer (copy) group.
2. Arithmetic group
3. Logic group
4. Branch control group
5. Machine control and I/O group.

Data transfer (copy) instructions

The data transfer instructions are used to transfer data from one
register to another register, from memory to register or register to memory but not
from one memory location to another memory location. Actually this data transfer
instruction copies the data from source to destination and the contents of the source
are not altered. So, the data transfer instruction performs basically copy operation.
Examples of data transfer instructions are MOV, MVI (Move Immediate), LXI (Load
Immediate H-L Pair), LDA (Load Accumulator), STA (Store Accumulator), LHLD
(Load H-L pair direct), SHLD (Store H-L pair direct), XCHG (Exchange the contents
of H-L pair with D-E pair) etc
Ex: MVI A, 55H ; Move the data 55H into Accumulator
MOV B, C ; Copies the contents of C register into B register
IN 00H
; Read the Input port(00H is the port address)
OUT 01H ; write data to an output port(01H is the port address)
LXIH 8570H ; Load H-L pair by address 8570H.
In the 8085 microprocessor, data transfer instructions do not affect any flags.
Arithmetic Instructions
The arithmetic operations like addition, subtraction, increment and decrement
are performed by the 8085 microprocessor using the following arithmetic
instructions.
ADD, ADI (Add Immediate), SUB (Subtract), SUI (Subtract Immediate), INR
(Increment), DCR (Decrement) etc
The arithmetic operations Add and subtract are performed in relation to
the contents of the accumulator. But, the increment or the decrement operations can
be performed in any register.
Ex:ADD B, C
ADI 08
SUB A, B
SUI 05
INR B
DCR C

; Add the contents of B register to the B register contents

; Add the data 08 to the accumulator.
; Subtract the contents of B register from accumulator.
;Subtract immediate the 8-bit data from accumulator
; Increment the B register contents by one bit
; Decrement the C register contents by one bit.

Arithmetic instructions modify all the flags according to the data conditions of the
result. The INR and DCR instructions affect all flags except the carry flag.
Logical Group of Instructions:
Since the microprocessor is a programmable logic chip, it can be perform all
the logic functions of the hard-wired logic through its instruction set. The 8085
processor can perform the logic instructions like, AND, OR, NOT (Complement) and
X-OR (Exclusive OR) etc The mnemonics of these instructions are given below.
ANA :
ANI :
ORA :

Logically AND the contents of a register

Logically AND immediate the 8-bit data.
Logically OR the contents of a register.

OR :
XRA :
XRI :
CMA :

Logically OR immediate the 8-bit data.

Exclusive-OR the contents of a register.
Immediate Exclusive-OR the 8-bit data
Complement the accumulator

All the logic operations are performed in relation to the contents of the accumulator.
The CMA instruction does not affect any flags. The executions of the logical
instruction do not affect the contents of the operand register.
Branch Instructions
These instructions are very important because they allow the microprocessor
to change the sequence of a program either conditionally or unconditionally. The
conditional branch instructions transfer the program to the specified label when
certain condition is satisfied. The unconditional branch instructions transfer the
program to the specified location unconditionally.
We know that the microprocessor is a sequential machine. So, it executes machine
codes from one memory location to the next. Branch instructions instruct the
microprocessor to go to a different memory location and the processor continues
executing machine codes from the new location. The address of the new locations
either specified explicitly or provided by the microprocessor or some times by
additional hardware. The Branch instructions are classified into three categories.
They are
(a). Jump instructions
(b). Call and return instructions
(c). Restart instructions.
Jump instructions specify memory locations explicitly and they are 3-byte
instructions. These Jump instructions are of two types. They are , Unconditional
Jump and Conditional Jump.
Unconditional Jump:
This is similar to Unconditional Go to statement in BASIC. When this
instruction is executed the 16-bit address available immediately in the instruction is
loaded into the program counter , so that the next sequence of instruction execution
starts from this location. This Unconditional Jump instruction enables the
programmer to create continuous loops.
JMP (16 bit address). So, this is a 3-byte instruction where the first
byte is op-code and the second, third bytes specify memory address.
For example, the instruction JMP 8500H, instructs the microprocessor to go to the
memory location8500H unconditionally. Sometimes, the jump location is specified
using a label also.
Conditional Jump:

This instruction allows the microprocessor to make decision depending on

certain conditions indicated by flags. The 8085 processor Jump instruction is
associated with four flags. Namely Carry flag (CY), Zero flag (Z), Sign flag (S) and
Parity flag (P). The following instructions shown in Table 3.3 transfer the program
sequence to the memory location specified under the given conditions.
S. No
1
2
3
4
5
6
7
8

Instruction
JC (16 bit Addr)
JNC (16 bit Addr)
JZ (16 bit Addr)
JNZ (16 bit Addr)
JP (16 bit Addr)
JM (16 bit Addr)
JPE (16 bit Addr)
JPO (16 bit Addr)

Description
Jump on carry (if CY=1)
Jump on no carry (if CY=0)
Jump on Zero (if Z=1)
Jump on no Zero (if Z=0)
Jump on plus (if D7=0; S=0)
Jump on minus (if D7=1; S=1)
Jump on Even Parity (if P=1)
Jump on Odd Parity (if P=0)

Table 3 various conditional jump instructions

To understand the instructions, let us consider the instruction JC (16 bit address).
The meaning of this instruction is, the microprocessor is instructed to jump the
specified 16 bit memory location if there exists a carry after the arithmetic operation
else it will execute the next instruction in the sequence.
CALL and RETURN Instructions
The microprocessor uses the two instructions CALL and RETURN to
implement subroutines. Here CALL instruction calls a subroutine program which is
not a part of the main program and the RET instruction at the end of the subroutine
program to return the control to the main program.
Ex: CALL (16 bit memory address)
RET
RESET (RST) Instruction
The 8085 processor provides eight RST instructions to transfer the program control
to a specific location on page 00H. These instructions are 1-byte instructions. The
various RST instructions and their call locations are given in the following Table 3.4
S. No
1
2
3
4
5
6
7
8

Mnemonics
RST 0
RST1
RST2
RST3
RST4
RST5
RST6
RST7

Hex code
C7
CF
D7
DF
E7
EF
F7
FF

Call location In Hex

0000
0008
0010
0018
0020
0028
0030
0038

Table 4 Various RST instructions and their call locations

Machine control and I/O Instructions

There are six basic machine control instructions. They are
EI (Enable Interrupt)
DI (Disable Interrupt)
NOP (No Operation)
SIM (Set Interrupt Mask)
RIM (Read Interrupt Mask)
HLT (Halt)
EI (Enable Interrupt): This is a one byte instruction used to enable the interrupt. This
instruction is used to enable the interrupts when the microprocessor is reset or the
interrupt enable flag is reset after interrupt acknowledge. This instruction takes one
machine cycle with four states. The op-code is FBH.
DI (Disable Interrupt): This is a one byte instruction which resets the interrupt enable
flag to disable all the interrupts except TRAP. It takes one machine cycle with four
states. The op-code is F3H.
NOP (No Operation): when this instruction is executed, the microprocessor performs
nothing. Microprocessor spends four states doing nothing. It is a one byte instruction
whose op-code is 00H.This instruction is normally used to generate very small time
delays of the order of few micro seconds. This NOP instruction is also very useful
when we are required to insert a few instructions in the main program additionally .
SIM (Set Interrupt Mask): This instruction masks the interrupt as desired. This is a
dual purpose instruction. The first purpose is to set or reset the mask of the
maskable interrupt. The second purpose is to send the data out through the SOD pin
at pin number 4 of the microprocessor.
RIM (Read Interrupt Mask): This instruction copies the status of the interrupts into
the accumulator. It is also used to read the serial data through the SID pin
HLT (Halt): After execution of this instruction the microprocessor goes into the halt
state. The processor can be restarted by a valid interrupt or by applying a RESET
signal. The microprocessor takes 5T states to implement the halt instruction.
I/O instructions:
There are two important instructions to input the data into the microprocessors
accumulator through the input port and output the data from the accumulator to the
output port. They are

IN (port address)
OUT (port address)

This port address is an 8-bit address. In both these instructions the default register is
Accumulator.

Ex: (i) IN 01H. This instruction will copy the contents into the Accumulator through
the port whose address is 01H. It takes three machine cycles and takes 10 states.
The op-code is DBH.
(ii)OUT 02H. This instruction sends the contents of Accumulator to the outport
whose address is 02H. It is a two byte instruction which requires 10 states. The opcode for this instruction is D3H.

ADDRESSING MODES
Majority of the instructions of 8085 microprocessor requires an operand
(either data or address) on which the intended operation can be performed. Some
instructions may require only one operand and some other instructions require two
operands for its instruction execution. The speed of execution mainly depends on the
position of the operand in the instruction. The scheme involved in identifying the
position of operands in an instruction is known as addressing mode.
There are five addressing modes 8085 processor. They are
i. Immediate addressing mode
ii. Direct addressing mode
iii. Register addressing mode.
iv. Register indirect addressing mode.
v. Implicit addressing mode.
(i). Immediate Addressing mode: The mode of addressing in which the operand is
a part of the instruction itself is known as Immediate Addressing mode. If the
immediate data is 8-bit, the instruction will be of two bytes. If the immediate data is
16 bit, the instruction is of 3 bytes.
Ex: (1). ADI DATA ; Add immediate the data to the contents of the accumulator.
(2).LXIH 8500H : Load immediate the H-L pair with the operand 8500H
(3). MVI 08H
; Move the data 08 H immediately to the accumulator
(4). SUI 05H
; Subtract immediately the data 05H from the accumulator
(ii) Direct Addressing mode: The mode of addressing in which the 16-bit address
of the operand is directly available in the instruction itself is called Direct Addressing
mode. i.e., the address of the operand (data) is available in the instruction itself. This
is a 3-byte instruction.
Ex: (1). LDA 9525H ; Load the contents of memory location into Accumulator.
(2). STA 8000H ; Store the contents of the Accumulator in the location 8000H
(3). IN 01H ; Read the data from port whose address is 01H.
(iii). Register addressing modes: The mode, in which the operand is in one of the
general purpose registers, is known as the register addressing mode.
Ex: (1). MOV A, B;
Move the contents of B register to A register.
(2). SUB D;
Subtract the contents of D register from Accumulator.
(3). ADD B, C; Add the contents of C register to the contents of B register.

(iv). Register indirect addressing modes: The 16-bit address location of the
operand stored in a register pair (H-L) is given in the instruction. The address of the
operand is given in an indirect way with the help of a register pair. Hence it is called
Register indirect addressing mode
Ex: (1).LXIH 9570H; Load immediate the H-L pair with the address of the location
9570H
MOV A, M; Move the contents of the memory location pointed by the H-L pair
to accumulator
(v). Implicit Addressing mode: The mode of instruction which do not specify the
operand in the instruction but it is implicated is known as implicit addressing mode.
i.e., the operand is automatically considered to be in the Accumulator.
Ex: (1).CMA; complement the contents of Accumulator
(2).CMC; Complement carry
(3). RLC; Rotate Accumulator left by one bit
(4). RRC; Rotate Accumulator right by one bit
(5). STC; Set carry.
Beginning to use 8085 Assembly Language
The Intel 8085 microprocessor has 7 eight bit registers. These registers can hold a quantity as
large as 0FF H, 11111111 B, or 255 Decimal. These are 8 bit registers A, B, C, D, E, H, and
L.
An 8 bit register is loaded or initialized with the MVI instruction. Variations on this
are MVI A, byte ; MVI B, byte; etc.
The coding for MVI B, 4CH would be 06 4C, a 2 byte instruction.
You can copy (duplicate) the contents of one 8 bit register to another 8 bit register
with the MOV instruction. The format for this is MOV to, from. An example is MOV A, E
with the one byte code of 7BH. Here the contents of E is duplicated in the A register.
Certain of these registers can be used as pairs. These are BC, DE, and HL. A register pair acts
as though it is a 16 bit register. A 16 bit register can hold a quantity as large as 0FFFF H,
65535 Decimal, or 1111111111111111 B. These 16 bit registers are known by their first letter
only. BC is designated B, DE is designated D, HL is designated as H.
The register pairs are initialized with the LXI instruction. LXI B, 1234H would load the B
register with 12H and the C register with 34H. The coding for this would be 01 34 12. 01
represents LXI B, with 3412 being the data in Intel byte swapped form. Of course, you could
also initialize BC with separate MVI B, 12H and MVI C, 34H instructions.
Review:
Load an 8 Bit register, use MVI r, byte. (r = A,B,C,D,E,H,L)

Load a 16 Bit register with LXI rp, 2 bytes. (rp = B, D, H)

Duplicate an 8 bit register into another with MOV r1, r2.
The Increment ( INR, INX) instructions are used to add 1 to the contents of a register. INR is
for the 8 bit registers, INX is for the 16 bit paired registers. INR C adds one to the contents of
C. INX B adds 1 to the contents of the BC 16 bit register pair.
The Decrement (DCR, DCX) instructions work the same way except 1 is subtracted.
Example: If DE contains 2237H and you INX D, DE gets one added to become 2238H. D
still contains 22 and E contains 38.
If you now do INR D followed by DCR E, the new contents of DE is 2337.
The registers were treated separately since we used the 8 bit versions of increment and
decrement.
The Zero Flag, is a part of the flag (F) register. When an 8 bit register hits zero as the result of
an increment, decrement, arithmetic or logical operation, the zero flag becomes active. This
allows some decision making to be done by the JNZ or JZ or CNZ or CZ instructions.
For example, if the H register contains 01 and we decrement with DCR H, the register now
contains 0 and the zero flag goes active. We make use of this with the conditional jump and
conditional call instructions. These are JZ, jump if zero, JNZ, jump if not zero, etc.
In the delay loop discussed in class, the conditional jump depends on the B register being
zero or non zero depending on your viewpoint.

THE next instruction is here if B=0 and we don't do the jump back up to loop.
Not all instructions have an effect on the ZERO flag. DCR, INR, ORA, ANA, ADD, SUB,
XRA, CMP, CMA all work because they are 8 bit instructions.
Simply loading a register does not affect the zero flag. For instance, MVI B, 0 does not set
the zero flag into operation. MOV instructions don't affect the zero flag either.
Certain 16 bit instructions also don't do anything to the zero flag. These include DCX, INX,
LXI. We use the 16 bit instructions in longer delay loops. For example, if we write a delay
program using the BC register pair, we get a whole lot more delay since a double register can
hold a much larger number. 65535 in fact. That's 0FFFFH. ( 4 F's )
A double register delay loop requires a TRICK to discover if the pair is empty. JNZ isn't good
enough by itself to work with a 16 bit decrement (DCX).......

A 16 bit double register delay loop looks like this:

A 16 bit Decrement (DCX) or Increment (INX) doesn't affect the zero flag so we cannot use
the JNZ instruction directly. We must use this software test or trick to discover if we have
emptied BC and finished 65535 decrements.
The idea behind the 'trick' is that if we OR B with C the result will only be zero if both B and
C are already zero. Since there is no instruction that directly OR's B with C, we move one of
these into A and use the ORA instruction to accomplish OR ing B with C. That's how we
learn if BC is zero having done 65535 decrements.
The 16 bit delay loop provides much more delay than the 8 bit delay loop. 255 decrements vs
65535 decrements. We will be using both of these programming structures. Memorize them;
study them to be sure you understand how they operate.
SUBROUTINES
Subroutines are easy with the CALL and the RET instructions. A delay subroutine is easily
created by beginning with the NAME and ending with the RET instruction. The main
program then CALLs the subroutine and return is automatic when the job is done. One thing
though......
The Stack Pointer register (SP) must be initialized for any CALL or RET instruction to work
reliably. This is done with the LXI SP instruction. We load the SP with an address from valid
memory, away from our software, for use by the CPU. The processor will store return
addresses in its stack area. A counter program that uses a subroutine would look like this:

ASSEMBLY LANGUAGE PROGRAMMING EXAMPLES:

Addition Programs
Address
of the
memory
location
8000

Hex
code

Label

Mnemonics
OpOperand
code

Comments

21,00,90

LXI

H, 9000

8003
8004
8005

3E
00
86

MVI

A, 00

Initialise memory pointer to point

the first data location 9000.
Clear accumulator

ADD

A, M

8006

23

INX

8007

86

ADD

A, M

The first number is added to

accumulator [A] [A] + M
Increment the memory pointer to
next location of the Data.
The 2nd number is added to
contents of accumulator
The contents of accumulator are
stored in memory location 9002.

8008
32
STA
9002
8009
02
800A
90
800B
76
HLT
Stop the execution
Example 1: Addition of two 8-bit numbers whose sum is 8-bits.

Explanation: This assembly language program adds two 8-bit numbers stored in two
memory locations .The sum of the two numbers is 8-bits only. The necessary
algorithm and flow charts are given below.
ALGORITHM:
Step1. : Initialize H-L pair with memory address XX00 (say: 9000).
Step2. : Clear accumulator.
Step3. : Add contents of memory location M to accumulator.
Step4. : Increment memory pointer (i.e. XX01).
Step5. : Add the contents of memory indicated by memory pointer to accumulator.
Step6. : Store the contents of accumulator in 9002.
Step7. : Halt
PROGRAM:

Ex: Input: Ex: (i) 9000 29 H

9001 16 H
Result: Ex: (i) 9002 3F H

Ex :(ii) 9000 49 H
9001 32 H
Ex :( ii) 9002 7B

Flow Chart
Start

Initialise H-L Pair with XX00

Clear Accumulator

Add contents of M to Accumulator

# Increment memory pointer(XX01)
# Add contents of M to A

Copy the contents of Reg. A

to memory location XX02

Stop

Fig 3.18
Example 2: Addition of two 8-bit numbers whose sum is 16 bits.
Explanation: The first 8-bit number is stored in one memory location (say 8500) and
the second 8-bit number is stored in the next location (8501).Add these two numbers
and check for carry. Store the LSB of the sum in one memory location (8502) and the
MSB (carry) in the other location(8503).
ALGORITHM:
Step1. : Initialize H-L pair with memory address X (say: 8500).
Step2. : Clear accumulator.
Step3. : Add contents of memory location M to accumulator.
Step4. : Increment memory pointer (i.e. 8501).
Step5. : Add the contents of memory indicated by memory pointer to accumulator.
Step6. : Check for Carry
Step 7 : Store the sum in 8502.
Step8 : Store the Carry in 8503 location
Step 9 : Halt

Flow Chart

Start

Initialise H-L Pair with XX00

Clear Accumulator
(00) A

Add
contents of
# Increment memory
pointer(XX01) &
# Add contents of M to A

Store the sum in the location xx02

Is
Carry
exists ?

Yes

No

Store carry
in the XX03

Store Zero
in the XX03
Stop

Fig 3.19

PROGRAM:
Address of Hex
the
code
memory
location

Lab
el

Mnemonics
OpOperand
code

Comments

8000

LXI

H, 8500 H

8003
8004
8005

21,00
,85
3E
00
86

MVI

A,00

ADD

A, M

8006
8007
8008

0E
00
23

MVI

C,00

INX

8009

86

ADD

A, M

800A

32

JNC

FWD

800B
800C
800D
800E

0E
80
0C
32

INR
STA

C
8502 H

800F
8010
8011
8012
8013
8014
8015

02
85
79
32
03
85
76

MOV
STA

A,C
8503 H

FW
D

HLT

Initialise memory pointer to point

the first data location 9000.
Clear accumulator
The first number is added to
accumulator [A] [A]+M
Initial value of Carry is 0
Increment the memory pointer to
next location of the Data.
The 2nd number is added to
contents of accumulator
Is Carry exists ? No,go to the label
FWD
Make carry =1
The sum is stored in memory
location 8502.

Store the carry at 8503 location

Stop the execution

Ex: Input:

Ex :

8500 97 H
8501 98H

RESULT: 8502 32 H
8503 -- 01 H

Example 3: Decimal addition of two 8-bit numbers whose sum is 16 bits.

Explanation: Decimal addition of two 8-bit numbers is same as that of two 8-bit
numbers program. Except that the use of DAA instruction. The first 8-bit number is
stored in one memory location (say 8500) and the second 8-bit number is stored in
the next location(8501).Add these two numbers and use the DAA instruction to get
the result in decimal. Also check for carry. Store the LSB of the sum in one memory
location(8502) and the MSB (carry) in the other location(8503).
ALGORITHM:
Step1. : Initialize H-L pair with memory address XXXX (say: 8500).
Step2. : Clear Carry register C.
Step3. : Move contents of memory location M to accumulator.
Step4. : Increment memory pointer (i.e. 8501).
Step5. : Add the contents of memory indicated by memory pointer to accumulator.
Step6. : Apply the instruction DAA (Decimal adjust after addition)
Step7: Check for Carry
Step8: Store the sum in XX02.
Step9: Store the Carry in XX03 location
Step10: Halt
Flow Chart

Start

Initialize H-L Pair with XX00

Clear Carry register

(00) C

Add contents of M
to Accumulator

# Increment memory
pointer(XX01) &
# Add contents of M to A

Apply DAA instruction to

convert Hex data to decimal
form

Store the sum in the

location XX02

Is
Carry
Exists?

No
Store Zero in
the XX03
location

Yes

Stores carry in
the XX03
location

Stop

Fig .20
PROGRAM
Address of
the memory
location

Hex
code

Label

Mnemonics
OpOperand
code

Comments

8000

LXI

8003
8004
8005

21,
00,85
0E
00
7E

MVI

H, 8500 Initialise memory pointer to point

H
the first data location 9000.
C, 00
Clear accumulator

MOV

A, M

8006

23

INX

8007

86

ADD

A, M

8008
8009

27
D2

DAA
JNC

FWD

Is Carry exists? No, go to the label

FWD

800C
800D
800E
800F
8010
8011

0D
80
0C
32
02
85
79
32

INR
STA

C
8502 H

Make carry =1
The contents of accumulator are
stored in memory location 8502.

MOV
STA

A, C
8503 H

Carry is moved to accumulator

A Carry is stored in the location
8503

8012
8013
8014

03
85
76

FWD

HLT

The first number is added to

accumulator [A] [A]+M
Increment the memory pointer to
next location of the Data.
The 2nd number is added to
contents of accumulator

Stop the execution

Ex: Input:

Ex :

8500 67 D
8501 85 D

RESULT:

8502 52 D
8503 01 (Carry)

Stack and Subroutines

Stack is a set of memory locations in the Read/Write memory which is used for temporary
storage of binary information during the execution of a program. It is implemented in the
Last-in-first-out (LIFO) manner. i.e., the data written first can be accessed last; One can put
the data on the top of the stack by a special operation known as PUSH. Data can be read or
taken out from the top of the stack by another special instruction known as POP.
Stack is implemented in two ways. In the first case, a set of registers is arranged in a shift
register organization. One can PUSH or POP data from the top register. The whole block of
data moves up or down as a result of push and pop operations respectively. In the second
case, a block of RAM area is allocated to the stack. A special purpose register known as stack
pointer (SP) points to the top of the stack. Whenever the stack is empty, it points to the
bottom address. If a PUSH operation is performed, the data are stored at the location pointed
to by SP and it is decremented by one. Similarly if the POP operation is performed, the data
are taken out of the location pointed at by SP and SP is incremented by one. In this case the
data do not move but SP is incremented or decremented as a result of push or pop operations
respectively.
Application of Stack: Stack provides a powerful data structure which has applications in
many situations. The main advantage of the stack is that, we can store data (PUSH) in it
without destroying previously stored data. This is not true in the case of other registers and
memory locations. Stack operations are also very fast, the stack may also be used for storing
local variables of subroutine and for the transfer of parameter addresses to a subroutine. This
facilitates the implementation of re-entrant subroutines which is a very important software
property.
The disadvantage is, as the stack has no fixed address, it is difficult to debug and document a
program that uses stack.
Stack operation: Operations on stack are performed using the two instructions namely PUSH
and POP. The contents of the stack are moved to certain memory locations after PUSH
instruction. Similarly, the contents of the memory are transferred back to registers by POP
instruction.
For example let us consider a Stack whose stack top is 4506 H. This is stored in the
16-bit Stack pointer register as shown in Fig.3.29

Figure.29 The PUSH

operation of the Stack
Let us
(register
contents

25

consider two registers

pair) B & C whose
are 25 & 62.
Reg. B
Reg. C
62

After PUSH operation the status of the Stack is as shown in Fig 3.30

Figure .30 After PUSH operation the status of the stack

Let us now consider POP operation: The Figs 3.31 & 3.32 explains before and after the POP
operation in detail

Figure 3.31 The POP operation of the Stack

Figure 32 After POP operation the status of the stack

Before the operation the data 15 and 1C are in the locations 4502 & 4503 and after the pop
operation the data is copied to B-C pair and now the SP register points to 4504 location.This
is shown in Fig.3.32

Programming Example FOR PUSH & POP

Write a program to initialize the stack pointer (SP) and store the contents of the register pair
H-L on stack by using PUSH instruction. Use the contents of the register pair for delay
counter and at the end of the delay retrieve the contents of H-L using POP.
Memory
Label
Mnemonics
Operand
Comments
Location
8000
LXI
SP, 4506 H
Initialize Stack
pointer
8003
LXI
H,2565 H
8006
8007
.
.
.
.
8.00A

PUSH

DELAY
.
.
.
POP

CALL
.
.
.
H

Push
contents.

the

Subroutine: It is a set of instructions written separately from the main program to execute a
function that occurs repeatedly in the main program.
For example, let us assume that a delay is needed three times in a program. Writing delay
programs for three times in a main program is nothing but repetition. So, we can write a
subroutine program called delay and can be called any number of times we need
Similarly, in 8085 microprocessor we do not find the instructions for multiplication and
division. For this purpose we write separate programs. So, in any main program if these
operations are needed more than once, the entire program will become lengthy and complex.
So, we write subroutine programs MUL & DIV separately from main program and use the
instruction CALL MUL (or) CALL DIV in the main program. This can be done any number
of times. At the end of every subroutine program there must be an instruction called RET.
This will take the control back to main program.
The 8085 microprocessor has two instructions to implement the subroutines. They are CALL
and RET. The CALL instruction is used in the main program to call a subroutine and RET
instruction is used at the end of the subroutine to return to the main program. When a
subroutine is called, the contents of the program counter, which is the address of the
instruction following the CALL instruction is stored on the stack and the program execution
is transferred to the subroutine address. When the RET instruction is executed at the end of
the subroutine, the memory address stored on the stack is retrieved and the sequence of
execution is resumed in the main program.
Diagrammatic representation
Let us assume that the execution of the main program started at 8000 H. It continues until a
CALL subroutine instruction at 8020 H is encountered. Then the program execution transfers
to 8070 H. At the end of the subroutine 807B H. The RET instruction is present. After
executing this RET, it comes back to main program at 8021 H as shown in the following Fig.
3.34

Fig.33 Diagrammatic representation of subroutine program execution

The same is explained using the assembly language program example.
Program Example:
Memory
Address

Mnemonics

Operand

Comments

8000
|
|
|
8020
8021
8022
8023
|
|
|
802F

LXI

SP, 8400 H

Initialize the Stack pointer at 8400 H

CALL

8070 H

Call a subroutine program stored at the

location 8070 H. (It is a three by
Instruction)
The address of the next instruction
following CALL instruction.

Next instruction
|
|
|
HLT

End of the main program

.

Subroutine Program:
Memory
Address
8070
|

Mnemonics
Instructions

Operand

Comments
Beginning of the Subroutine.

|
|
|
807B
807C

RET
Next Subroutine

End of the program

Instructions of next subroutine if any
End of the subroutine.

807F

RET

Delay programs:
In many situations it may be desired to provide some delay between the execution of
two instructions by a microprocessor. The delay can be produced by either hardware chip like
8253 or by writing a software program using registers of the processor. Here we will discuss
the software delay program. This delay program is not a part of the main program. Hence it is
called delay sub-routine program. For small delays we can use only one register. But for
longer delays one has to use two or three registers. The technique involved here is, a register
is loaded with a number and then decremented by using the instruction DCR until it becomes
zero. The time of execution of the microprocessor is equal to the delay time produced.
For example, we have constructed a display system where the LEDs receive the input from a
microprocessor. Since the microprocessor is a very fast device it sends the signal at very high
speeds there by our eye cannot recognize the display pattern. So, if you provide some delay
between two input signals, the display can be visualized clearly. Similarly to observe the
rotations of a stepper motor, a delay is needed between every two excitation signals applied
to the motor.
Delay Subroutine with one register:
Program
Address

Label

Machine
code

Mnemonics

Operand

Comments

MVI

A, FF

Get FF in register A

DCR

Decrement register A.

9003

JNZ

LOOP

9006

RET

Has the content of

register B becomes
zero? No, jump to
LOOP. Yes, proceed
ahead.
Return to main program

9000
9002

LOOP

Calculation of Delay time for the above program:

In the above program register A is loaded by FFH B(255 decimal) and it is decremented in a
loop until it becomes zero. The delay produced by this program is as follows
We should know the number of times each instruction of the above program is being
executed. The number of states required for the execution of each instruction is as follows:

Instructions
MVI A, FFH
(loop) DCR A
JNZ loop
RET

States
7
4
7/10
10

Total T States=3584
The time required for one T-state in INTEL 8085 microprocessor is nearly 330n.sec
Delay time is= 3584 x 333n.sec
= 3.584 x 0.333 x 10-3 seconds
= 1.18272 x 10-3 seconds
= 1. 193472 milliseconds
Delay Subroutine with two registers
Program:
Addres
s

Label

Mnemoni
c

Operan
d

Comments

MVI

B, 10H

Get desired number in register B

MVI

C, 56H

Get desired number in register

DCR

Decrement C.

8405

JNZ

LOOP2

Is [C] zero? No, go to LOOP2. Yes,

proceed further

8408

DCR

Decrement register B

8409

JNZ

LOOP1

840C

RET

Is [B] zero? No, go to LOOP1. Yes,

proceed further
Return to main program.

8400
8402
8404

LOOP
1
LOOP
2

Machin
e
Code

Delay Subroutine using register pair

Program:
Address

Label

Machine
Code

8000
LOOP

Mnemonic

Operand

Comments

LXI

D, FFFF

Get FFFF in register pair D-E

DCX

Decrement count

MOV

A, D

Move the contents of register D to

accumulator

ORA

Check if D and E are zero.

JNZ

LOOP

If D-E is not zero, jump to LOOP

RET

Return to main program

Delay Subroutine using three registers

Program:
Address

Label

Machine
Code

Mnemonic

Operand

Comments

8400

MVI

A, 98H

Get control word

8402

OUT

03

Initialize port foe LED Display

8404

MVI

B, 50H

8406

MVI

C, FFH

8408

MVI

D, FFH

840A

DCR

840B

JNZ

LOOP3

840E

DCR

840F

JNZ

LOOP2

8412

DCR

8413

JNZ

LOOP1

8416

MVI

A, 01

8418

OUT

01

8419

HLT

Delay Subroutine with three registers

Output for LED

Stop.

From the above discussion it is clear that with increase of T-states required for a delay
subroutine, the delay time also increases.
UNIT III 8051 MICRO CONTROLLER 9
Hardware Architecture, pin outs Functional Building Blocks of Processor Memory
organization I/O ports and data transfer concepts Timing Diagram InterruptsComparison to Programming concepts with 8085.

Architecture of 8051 Signals and Operational Features

A device that having microprocessor, memory and I/O signal lines on a single chip
fabricated by using VLSI technique is called microcontroller.
Comparison of Microprocessor and Microcontroller:
MICROPROCESSOR

MICROCONTROLLER

1. The functional blocks of a The microcontroller includes the functional

microprocessor are ALU, registers, blocks of a microprocessor and in addition
timing and control unit.
has timer, parallel I/O port, serial I/O port,
internal RAM and EPROM/EEPROM
memory. Some controllers have even ADC
and/or DAC.

PINS AND SIGNALS OF 8031/8051:

The INTEL 805 F is an 8-bit microcontroller with 128 byte internal RAM and 4kb
internal ROM.
The INTEL 8031 is same, as 8051 except that it does not have internal ROM.
The 8051 is a pin 40 pin IC available in Dual-In line package (DIP).
Requires a single power supply of +5V.
Its maximum internal clock frequency rating is 12 MHz.

Pin Diagram for 8051/8031 microcontroller

Signals of 8031/8051 microcontroller

Alternate functions of port pins

Ports: (pin 1 to 8, pin 10 to 17, pin 21 to 28 and pin 32 to 39)

1. The 8031/8051 microcontroller has 32 I/O pins and they are organized as four numbers of
8-bit parallel port.
2. The ports are denoted as port-0, port-1, port-2 and port-3. Each port can be used as either
8-bit parallel port or 8 numbers of 1-bit ports.
3. The ports behave as latches during output operation and behave as buffers during input
operation.
4. Port-1 can be used only for I/O operation
5. When external memory is employed, the port-0 function as multiplexed low byte address
or data lines, and port-2 function as high byte address lines. Therefore for accessing
external memory the microcontroller uses 16-bit address and access the memory in bytes.
Hence the addressable memory space is 64 kb (216 = 64kb).
6. The 8031/8051 allows the external memory to be organized as two banks of 64 kb. One is
program/code memory and the other is data memory.
PSEN (low signal): pin 29

The signal PSEN (low) is used as read control/enable for program

memory.
RD (low signal) and WR (low signal): pin 17 and pin 16
1. The port pin P3.7 function as read control and the port pin P3.6 function as write control
for data memory.
2. When two external memory banks are not desirable, the PSEN (low) and RD (low)
should be externally ANDed to provide a single read control signal. In such cases the
controller will access a common memory space (of maximum capacity 64 kb) for
program and data.
3. ALE is used to demultiplex the low byte address or data using an external latch.
EA (Low)/Vpp : pin 31
1. When the microcontroller access program from external memory, then this pin is low. ie.
EA (low) is enabled.
2. When the microcontroller access program from internal memory, then this pin is high. At
that time this pin is used to supply programming voltage +12V to EPROM/ROM.
XTAL 1 and XTAL2: pin 19 and pin18

The XTAL 1 and XTAL2 pins are provided for external quartz crystal connection,
in order to generate the required clock for the microcontroller. The maximum frequency of
quartz crystal that can be connected to 8051 microcontroller is 12 MHz.
RST (low): pin 9

The RST(low) signal is used to reset the microcontroller in order to bring the
controller to a known state.

Contents of register after reset

Interrupts: pin 12 to 15

The 8051 has five interrupts.

In this two interrupts are external interrupt as INT0 (Low), INT1 (Low) and the
remaining three are internal interrupts as timer-0, timer-1 and serial port.

All interrupts are maskable and vectored interrupts.

Vector address and priority of interrupts

ARCHITECTURE OF 8051:

Architecture of 8031/8051 microcontroller

Central processing Unit:
1. ALU:
1. It performs the arithmetic operations such as addition, subtraction, multiplication
and division.

2. The unit can perform logical operations such as AND, OR; and Exclusive-OR, as
well as rotate, clear, and complement.
3. The ALU can also manipulate one bit as well as eight-bit data types.
4. Individual bits may be set, cleared, complemented, tested, and used in logic
computation.
2. Accumulator:
1. It is an 8-bit register.
2. It holds a data and receives the result of the arithmetic instructions.
3. B register: An 8-bit general-purpose register.
4. Program Status Word:
1. Many instructions implicitly or explicitly affect (or are affected by) several status
flags, which are grouped together to form the Program Status Word.
2. It also used to select the memory bank.

5. Stack Pointer (SP):

1. The stack pointer register is 8 bit wide.
2. It is incremented before data is stored during PUSH and CALL instructions.
3. After reset the value of SP is 07H.
6. Data Pointer (DPTR):
1. The data pointer is a 16-bit register used to hold the 16-bit address of data memory.
2. This can also be used as two numbers of 8-bit data pointer namely DPH and DPL.
3. The 8-bit data pointers are used for accessing internal RAM and SFR.
4. The 16-bit data pointer is used for accessing external data memory.
5. The contents of data pointer are programmable using instructions.
7. Program Counter (PC):
1. It is a 16 bit register.
2. PC is used, as address pointer to access program instructions and it is automatically
incremented after every byte of instruction fetch.
I/O Devices:

1. The 8051 has four numbers of 8-bit ports namely port-0, port- 1, port-2 and port-3.
2. Each port has a latch and driver (or buffer).
3. When external memory is employed the port-0 lines will function as multiplexed low
byte address/data lines and port-2 lines will function as high byte address lines.
4. Also the port pins P3.7 and P3.6 are used to output read and write control signals
respectively.
5. The port-1 is dedicated I/O port and does not have any alternate function.
6. The ports are also mapped as internal memory in the controller and so they can be
addressed as memory locations for 8-bit operation.
Instruction Register (IR) & timing and control unit:
1. The 8051 has 8-bit ALU, which performs arithmetic and logical operations on binary
data.
2. The A and B registers are used to hold the input data and the result of ALU operation.
3. The controller will fetch the instructions one by one, starting from the address stored
in PC and store in IR, which decodes the instructions and give information to timing
and control unit.
4. Using the information supplied by the IR unit the control signals necessary for
internal and external operations are generated by the timing and control unit.
Timer/Counter & Serial port:
1. The 8031/8051 has two 16-bit programmable timer/counter namely timer-1 and timer
0.
2. In the counter mode of operation they can count the number of high to low transitions
of the signal applied to the timer pins.
3. In timer mode of operation they can be independently programmed to work in any one
of the four operation modes. They are called mode-0, mode-1, mode-2 and mode-3.
4. In mode-0 the serial port can either receive or transmit at fixed baud rate.
5. In mode-2 it can simultaneously transmit and receive at any one of the two selectable
baud rate.
6. In mode-1 and mode-3 it can work as full duplex serial port with variable baud rate,
which is programmed using timer-1.
Memory Organization:
1. Since the size of address pointers are 16-bit they can address up to 2 16 = 64kb memory
locations.
2. A microcontroller based system requires both EPROM and RAM. The EPROM is
required for permanent program and permanent data storage. The RAM is required for
temporary data storage and stack. The 8031/8051 has 64kb program memory address
space and 64kb data memory address space.
3. The microcontroller can only read from program memory such as ROM/EPROM/
EEPROM and the signal PSEN (Low) is used as read control for reading program
memory.
4. The microcontroller can read and write with data memory RAM. It has separate read
control signal RD(Low), and write control signal WR(Low) for reading and writing
with data memory respectively.
5. In 8031/8051 based system only memory mapped I/O is possible.
Program Memory:
1. In 8031 there is no internal ROM/EPROM and so the entire 64 kb program memory space
in the range 0000H to FFFFH is external. Therefore in 8031 based systems the pin
EA(Low) is always tied low or grounded (0V).

2. The 8051 has 4kb internal ROM which can be mapped to first 4kb address space of
program memory.
3. If EA(Low) pin is tied high or tied to V CC (+5V), then the internal 4kb ROM be mapped
as program memory in the address range 0000H to 0FFFH and the external program
memory 60kb will have the address range l000H to FFFFH
4. If EA(Low) pin is tied low or grounded (0V), then the internal ROM is ignored or cannot
be accessed. The entire 64 kb program memory address space is external with address
range 0000H to FFFFH.

The 8051 Program Memory

5. The PSEN (Low) signal is used to activate output enable signal to access the external
ROM/EPROM, as shown.

Accessing External Program Memory

6. The port 0 is used as a multiplexed address/bus. It gives lower order 8-bit address in the
initial T-cycle and later it is used as a data bus.
7. The 8-bit address is latched using external latch and ALE signal generated by 8051.
8. The port 2 provides the higher order 8-bit address.
9. The lower part of program memory stores the vector addresses for various interrupt
service routines.
10. Each interrupt is assigned with a fixed location in program memory.

Interrupt/Vector location

Data Memory:
1. In 8031/8051 microcontroller the entire 64kb data memory space is external.
2. The address range of external data memory is 0000H to FFFFH.
3. Apart from external data memory the 8031/8051 has 256 bytes of internal data
memory in which the first 128 bytes are called RAM and next 128 byte is called SFR.
4. The address range of SFRs and internal RAM are 00H to FFH
5. The MOVX instruction is used to access the external data memory.
6. The internal data memory space for 8051 is divided into three blocks: Lower
128bytes, Upper 128 bytes and SFRs.
7. The upper addresses and SFRs occupy the same block of address space, 80H through
FFH, and they are physically separate entities.
8. The upper address is accessible by indirect addressing only and SFRS are accessible
by direct addressing only.
9. Lower address space can be accessed either by direct addressing or by indirect
addressing.

a.
10. The 8051 Data Memory
11. The circuit diagram for connecting external data memory is shown. The multiplexed
address / data bus is provided by port 0.
12. Port 2 gives the higher order address bus.
13. The RD (Low) and WR (Low) signals from 8051 selects the memory read and
memory write operation, respectively.

Accessing External Data Memory

SPECIAL FUNCTION REGISTERS (SFR) :
1. The SFRs include 21 internal registers listed in table.
2. Each register of SFR has one byte address. Some of the registers are both byte and bit
addressable (The registers whose address ends with 0H or 8H are bit addressable).
3. The 8031/8051 has a separate 256 bytes internal RAM accessed by using 8-bit address.
4. In this 256 bytes address space, first 128 byte addresses are allotted to internal RAM
(00H to 7FH) and the next 128 bytes are allotted to SFR (80H to FFH).
5. Using MOV instructions SFR can access.

A and B Registers:
1. The A and B registers are called CPU registers.
2. They are used to hold the data for most of the CPU (ALU) operations.
3. The size of A and B registers are 8-bit.
4. In ALU operation, the result is stored in A-register and so it is also known as
accumulator.
Data Pointer (DPTR):
1. The data pointer is a 16-bit register used to hold the 16-bit address of data memory.
2. This can also be used as two numbers of 8-bit data pointer namely DPH and DPL.
3. The 8-bit data pointers are used for accessing internal RAM and SFR.
4. The 16-bit data pointer is used for accessing external data memory.
5. The contents of data pointer are programmable using instructions.
Program Status Word (PSW):
1. The PSW is also known as flag register.
2. The flags are useful for the programmer to test the condition of the result and make
decisions.
3. The format of PSW of 8031/8051 microcontroller is shown in fig.

4. The PSW consists of four math flags and two register bank select bits. The math flags
are Carry, Auxiliary Carry, and Overflow and Parity flags.
5. The flags are altered after arithmetic and logical operations depending on the result.
6. The carry flag is set when the result has a carry.
7. When there is a carry from lower nibble to upper nibble the auxiliary carry is set.
8. When the result has even parity, the parity flag is set.
9. In certain mathematical operations if the size of the result exceeds the size of
destination register then overflow flag is set.
10. The register bank select bits RS1 and RS0 are used to select any one of the four
register banks of the internal RAM. At any one time the microcontroller can work
with (or access) only one register bank selected by these bits.
11. The bank select bits are programmable and after reset the controller defaults to bank0. The selection of register bank using the RS1 and RS0 bits are listed in table.

Stack Pointer (SP):

1. The stack pointer always holds the 8-bit address of the top of stack.
2. The programmer can reserve any portion of RAM as stack.
3. After a reset the stack pointer is initialized to 07H.
4. The stack can be accessed using PUSH and POP instructions.
5. During PUSH operation the stack pointer is automatically incremented by one and
during POP operation the stack pointer is automatically decremented by one
Power Control Register (PCON):
1. The PCON register is used for power control and baud rate selection.
2. It also consists of general-purpose user flags. The format of PCON is shown in figure.
3. The controller can be driven to idle mode by setting IDL bit of PCON register.
4. In idle mode the clock signal is stopped to CPU (ALU), but the clock signal is
supplied to interrupt, timer and serial port blocks.
5. The idle mode can be terminated either by an interrupt or by hardware reset.
6. The power 12V can be reduced to 2V by setting PD bit.
7. During power down mode the internal oscillator is stopped.

8. The power down mode can be terminated only by a hardware reset.

9. The SMOD bit is used to decide the baud rate in serial port operating modes 1, 2 or 3.
In mode 2,
10. if SMOD =0, then the baud rate is 1/64 of oscillator frequency
11. if SMOD = 1, then the baud rate is 1/32 of oscillator frequency.
12. In mode 1 and 3, the baud rate depends on SMOD and timer-1 overflow rate.
a. The baud rate in mode 1 or 3 = (2SMOD/32) x (Timer-1 Overflow Rate).
13. The programmer, to indicate the status of certain events during program execution can
use the general-purpose flag bits GF1 and GF.
Serial Data Buffer Register (SBUF):
1. The SBUF register is used to hold the parallel data during transmission and reception.
2. During serial reception, the serial data is received via RxD pin and converted to
parallel data and stored in receive buffer.
3. During serial transmission, the parallel data is stored in transmit buffer and then
converted to serial data to transmit via TxD pin.
4. The transmit and receive buffers are assigned the same internal address 99H but
transmit buffer can be accessed only for write operation and receive buffer can be
accessed only for read operation.
5. When data is written to SBUF if goes to transmit buffer and when data is read from
SBUF it comes from receive buffer.
Timer Mode Control Register (TMOD):
1. The TMOD register is used to select the operating mode and the timer/counter
operation of the timers.
2. The format of TMOD register is,

3. The lower four bits of TMOD register is used to control timer-0 and the upper four
bits are used to control timer-1.
4. The two timers can be independently program to operate in various modes.

5. The TMOD register has two separate two bit field M0 and Ml to program the
operating mode of timers. The operating modes of timers are mode-0, mode-1, mode2 and mode-3. In all these operating modes the oscillator clock is divided by 12 and
applied as input clock to timer.
Mode-0
1. In mode-0 the timer register is configured as 13-bit register.
2. For timer-1 the 8 bits of TH1 and lower 5 bits of TL1 are used to form 13-bit register.
3. For timer-0 the 8-bit of TH0 and lower 5 bits of TL0 are used to form 13-bit register.
4. The upper three bits of TL registers are ignored.
5. For every clock input to timer the 13-bit timer register is incremented by one When
the timer count rolls over from all 1s to all 0s, (i.e., 1 1111 1111 1111 to 0 0000 0000
0000) the timer interrupt flag in TCON register is set to one
Mode-1
1. The mode-1 is same as mode-0 except the size of the timer register. In mode-1 the TH
and TL registers are cascaded to form 16-bit timer register.
Mode-2
1. In mode-2, the timers function as 8-bit timer with automatic reload feature. The TL
register will function as 8-bit timer count register and the TH register will hold an
initial count value.
2. When the timer is started, the initial value in TH is loaded to TL and for each clock
input to timer the 8-bit timer count register is incremented by one.
3. When the timer count rolls over from all 1s to all 0s (i.e., 1111 1111 to 0000 0000),
the timer interrupt flag in TCON register is set to one and the content of TH register is
reloaded in TL register and the count process starts again from this initial value.
Mode-3
1. In mode-3, the timer-0 is configured as two separate 8-bit timers and the timer-1 is
stopped.
2. In mode-3 the TL0 will function as 8-bit timer controlled by standard timer-0 control
bits and the TH0 will function as 8-bit timer controlled by timer-1 control bits.
3. While timer-0 is programmed in mode-3, the timer-0 can be programmed in mode-0,
1 or 2 and can be used for an application that does not require an interrupt.
a. The C/T(Low) bit of TMOD register is used to program the counter or timer
operation of the timer. When C/T bit is set to one, the timer will function as event
counter. The C/T(Low) bit is programmed to zero for timer operation.
b. The timer will run only if clock input is allowed.
c. When GATE = 1, the clock input to timer is allowed only if the signal at pin is
high and when GATE =0 the signal at INT (low) pin is ignored.
Serial Port Control Register (SCON):

The format of SCON register is shown.

Mode 0:
In this mode the serial port function as half duplex serial port with fixed baud rate.
The 8- bit serial data is received and transmitted through RxD pin and the controller
output the shift clock through TxD pin during reception and transmission.
The baud rate is fixed at 1 / 12 of the oscillator frequency.

Mode 1:
In this mode the serial port function as full duplex serial port with variable baud rate.
In this mode one data consists of 10 bits, which includes one start bit, eight data bit
and one stop bit. During reception the stop bit is stored as RB8 in SCON register.
Baud rate in mode-1 depends on the value of SMOD bit in PCON register and the
timer-1overflow rate.
Mode 2:
In this mode the serial port function as full duplex serial port with a baud rate of either
1/32 or 1/64 of the oscillator frequency.
In this mode one data consists of 11 bits which includes one start bit, eight data bit, a
programmable 9th data bit and one stop bit.
During transmission the TB8 of SCON register is added as 9th data bit and during
reception the 9th data bit is stored as RB8 in SCON register.
The baud rate depends on the value of SMOD bit in PCON register.
Mode 3:
1. The mode-3 is same as mode-2, except the baud rate.
2. In mode-3, the baud rate is variable. The baud rate depends on the value of SMOD
bit in PCON register and the timer- 1 overflow rate.
3. The serial mode bit-2 (SM2) has no effect in mode-0 and when programmed for
mode-0, the SM2 should be equal to zero.
4. In mode-1, SM2 is used to check a valid stop bit during reception. In mode-1, if
SM2 = 1, then receive interrupt (RI) is activated only when a valid stop bit is
received.
5. In mode-2 and mode-3 the SM2 bit is used to enable multiprocessor
communication.
6. In multiprocessor communication the serial port of a number of microcontrollers
can be connected to a common serial bus. One controller will act as a master and
all other controller will act as slave.
7. A unique 8-bit address is assigned to each slave and the SM2 bit in all the slaves is
set to 1.

8. When SM2 bit is one, the slaves will consider the received byte as address and
when SM2 bit is zero the slaves will consider the received byte as data.
9. For communication with a slave the master will first send as address byte and then
a data byte.
10. The master initiates communication with a slave by sending the address of the
slave on the bus. All the slaves will receive the address byte. Since SM2 = 1
initially in all the slaves, the received byte will be considered as address and the
slaves will verify whether the received address matches with assigned address.
The slave whose assigned address matches with received address will clear its
SM2 bit. Now SM2 bit of only one of the slave will be zero.
11. Next the master will send a data byte which is also received by all the slave, but
the data byte is accepted by the slave whose SM2 = 0 and so the receive interrupt
is activated only in one of the slave whose SM2 = 0.
12. After reading the received data from SBUF register, the SM2 bit of the slave
should be set to one again to receive next data.
13. The REN bit of SCON register can be used to enable or disable the serial
reception. When REN = 1, the serial reception is enabled and when REN = 0, the
serial reception is disabled.
14. The bits TI and RI of SCON register are transmitting interrupt flag and receive
interrupt flag respectively.
15. The controller will set the TI bit during the transmission of stop bit of a data
character in mode 1 to 3 and during the transmission 0 bit of a data character in
mode-0.
16. The controller will set the RI bit during the reception of stop bit of a data character
in mode 1 to 3 and during the reception of 8th bit of a data character in mode- 0.
Timer Control Register (TCON):
1. The TCON register consists of timer overflow flags, timer run control bits, external
interrupt flags and external interrupt type control bits.
2. The format of TCON register is,

When clock signal is applied, after reaching maximum value (i.e., the content of counter
is all 1s), the content of counter will become zero (i.e., all 0s). This condition is called
timer overflow and this is also the end of timing maintain by using the timer.
The TCON register has a 1-bit flag, TF for each timer to indicate the timer overflow or
end of timing.
Whenever the timer/counter overflows, the TF flag is set to one.
The TF flag is also used as an interrupt signal to initiate the execution of a subroutine.
When the controller executes a subroutine, the TF flag is cleared.
The TR bit is used to start/stop the timer/counter. When TR bit is set to one, the timer/
counter will start counting and continue the counting as long as TR bit is one. The
timer/counter will stop counting when TR bit is cleared to zero.

 When a valid external interrupt signal is detected the IE flag is set to one. When the
controller accepts the external interrupt and start processing it, the IE flag is cleared to
zero.
The IT = 1, when it recognize falling edge triggered external interrupt and IT = 0, when it
recognize logic low level external interrupt.
Interrupt Enable Register (IE):
The IE register is used to enable/disable the interrupts of 8051.
The interrupts are recognized by the controller only if they are enabled.
The format of IE register is,

If EA = 0, then it disable all the five interrupts of 8051.

If EA = 1, then it enable the interrupts. The EA bit is also called global enable.
Interrupt Priority Register (IP):
The 8051 has five interrupts.
The normal priority of these interrupts from highest to lowest are external interrupt-0,
Timer-0 interrupt, External interrupt- 1, Timer-1 interrupt and serial Port interrupt.
The IP register can be programmed to make the priority of any of the interrupt as highest.
When the priority bit of a particular bit is programmed as one then its priority will be
highest.
The format of IP register is,

ADDRESSING MODES:

An "addressing mode" refers to how you are addressing a given memory location.
In summary, the addressing modes are as follows, with an example of each:
Immediate Addressing
Direct Addressing
Indirect Addressing
External Direct

MOV A,#20h
MOV A,30h
MOV A,@R0
MOVX A,@DPTR

Code Indirect

MOVC A,@A+DPTR

Each of these addressing modes provides important flexibility.

Immediate Addressing
Immediate addressing is so-named because the value to be stored in memory immediately
follows the operation code in memory. That is to say, the instruction itself dictates what value
will be stored in memory.
For example, the instruction:
MOV A,#20h
This instruction uses Immediate Addressing because the Accumulator will be loaded with the
value that immediately follows; in this case 20 (hexidecimal).
Immediate addressing is very fast since the value to be loaded is included in the instruction.
However, since the value to be loaded is fixed at compile-time it is not very flexible.
Direct Addressing
Direct addressing is so-named because the value to be stored in memory is obtained by
directly retrieving it from another memory location. For example:
MOV A,30h
This instruction will read the data out of Internal RAM address 30 (hexidecimal) and store it
in the Accumulator.
Direct addressing is generally fast since, although the value to be loaded isnt included in the
instruction, it is quickly accessable since it is stored in the 8051s Internal RAM. It is also
much more flexible than Immediate Addressing since the value to be loaded is whatever is
found at the given address--which may be variable.
Also, it is important to note that when using direct addressing any instruction which refers to
an address between 00h and 7Fh is referring to Internal Memory. Any instruction which
refers to an address between 80h and FFh is referring to the SFR control registers that control
the 8051 microcontroller itself.
The obvious question that may arise is, "If direct addressing an address from 80h through
FFh refers to SFRs, how can I access the upper 128 bytes of Internal RAM that are available
on the 8052?" The answer is: You cant access them using direct addressing. As stated, if you
directly refer to an address of 80h through FFh you will be referring to an SFR. However, you
may access the 8052s upper 128 bytes of RAM by using the next addressing mode, "indirect
addressing."
Indirect Addressing
Indirect addressing is a very powerful addressing mode which in many cases provides an
exceptional level of flexibility. Indirect addressing is also the only way to access the extra
128 bytes of Internal RAM found on an 8052.
Indirect addressing appears as follows:
MOV A,@R0
This instruction causes the 8051 to analyze the value of the R0 register. The 8051 will then
load the accumulator with the value from Internal RAM which is found at the address
indicated by R0.
For example, lets say R0 holds the value 40h and Internal RAM address 40h holds the value
67h. When the above instruction is executed the 8051 will check the value of R0. Since R0
holds 40h the 8051 will get the value out of Internal RAM address 40h (which holds 67h) and
store it in the Accumulator. Thus, the Accumulator ends up holding 67h.
Indirect addressing always refers to Internal RAM; it never refers to an SFR. Thus, in a prior
example we mentioned that SFR 99h can be used to write a value to the serial port. Thus one
may think that the following would be a valid solution to write the value 1 to the serial port:

MOV
R0,#99h
;Load
the
address
of
the
serial
port
MOV @R0,#01h ;Send 01 to the serial port -- WRONG!!
This is not valid. Since indirect addressing always refers to Internal RAM these two
instructions would write the value 01h to Internal RAM address 99h on an 8052. On an 8051
these two instructions would produce an undefined result since the 8051 only has 128 bytes
of Internal RAM.
External Direct
External Memory is accessed using a suite of instructions which use what I call "External
Direct" addressing. I call it this because it appears to be direct addressing, but it is used to
access external memory rather than internal memory.
There are only two commands that use External Direct addressing mode:
MOVX A,@DPTR
MOVX @DPTR,A
As you can see, both commands utilize DPTR. In these instructions, DPTR must first be
loaded with the address of external memory that you wish to read or write. Once DPTR holds
the correct external memory address, the first command will move the contents of that
external memory address into the Accumulator. The second command will do the opposite: it
will allow you to write the value of the Accumulator to the external memory address pointed
to by DPTR.
External Indirect
External memory can also be accessed using a form of indirect addressing which I call
External Indirect addressing. This form of addressing is usually only used in relatively small
projects that have a very small amount of external RAM. An example of this addressing mode
is:
MOVX @R0,A
Once again, the value of R0 is first read and the value of the Accumulator is written to that
address in External RAM. Since the value of @R0 can only be 00h through FFh the project
would effectively be limited to 256 bytes of External RAM. There are relatively simple
hardware/software tricks that can be implemented to access more than 256 bytes of memory
using External Indirect addressing; however, it is usually easier to use External Direct
addressing if your project has more than 256 bytes of External RAM.
INTERRUPTS:
What Happens When an Interrupt Occurs?
When an interrupt is triggered, the following actions are taken automatically by the
The current Program Counter is saved on the stack, low-byte first.
Interrupts of the same and lower priority are blocked.
In the case of Timer and External interrupts, the corresponding interrupt flag is set.
Program execution transfers to the corresponding interrupt handler vector address.
The Interrupt Handler Routine executes.
What Happens When an Interrupt Ends?
An interrupt ends when the program executes the RETI (Return from Interrupt)
instruction. When the RETI instruction is executed the following actions are taken by the
microcontroller:
Two bytes are popped off the stack into the Program Counter to restore normal program
execution.
Interrupt status is restored to its pre-interrupt status.

Types of Interrupts:
The 8051 provide 5 interrupt sources.
They are,
1. External interrupt 0
2. Timer interrupt 0
3. External interrupt 1
4. Timer interrupt 1
5. Serial port interrupt
Interrupt Destinations:
The interrupts are stored in the lower addresses in program memory.
Interrupt
Address(HEX)
IEO
TF0
IE1
TF1
SERIAL

0003
000B
0013
001B
0023

Interrupt priority:
The normal priority of the interrupts are,
1. External interrupt 0
2. Timer interrupt 0
3. External interrupt 1
4. Timer interrupt 1
5. Serial port interrupt
The priority will be changed by the special function register IP and they are enabled by
IE register.
Interrupt Enable Register (IE):

The IE register is used to enable/disable the interrupts of 8051.

The interrupts are recognized by the controller only if they are enabled.
The format of IE register is,

If EA = 0, then it disable all the five interrupts of 8051.

If EA = 1, then it enable the interrupts. The EA bit is also called global enable.
Interrupt Priority Register (IP):

 The 8051 has five interrupts.

The normal priority of these interrupts from highest to lowest are external interrupt-0,
Timer-0 interrupt, External interrupt- 1, Timer-1 interrupt and serial Port interrupt.
The IP register can be programmed to make the priority of any of the interrupt as
highest.
When the priority bit of a particular bit is programmed as one then its priority will be
highest.
The format of IP register is,

UNIT V MICRO CONTROLLER PROGRAMMING & APPLICATIONS 9

Data Transfer, Manipulation, Control & I/O instructions Simple programming exercises key
board and display interface Closed loop control of servo motor- stepper motor control
Washing Machine Control.
INSTRUCTION SET AND APPLICATIONS
The 8031/8051 instructions can be classified into the following five groups.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branching instructions
5. Boolean instructions
Data Transfer Instructions:
Data transfer between registers and memory locations are done by data transfer
instructions.
The various mnemonics used for data transfer instructions are MOV, MOVC,
MOVX, PUSH, POP, XCH and XCHD, and they perform any one of the
following operations.
Copy the content of a SFR to internal memory or vice-versa.
Load an immediate operand to SFR/internal memory.
Exchange the content of SFR internal memory with accumulator.
Copy the content of program memory to accumulator.
Copy the content of data memory to accumulator or vice-versa.
6. Data moving / handling Instructions: Mnemonics
Operational description
Addressing No. of bytes
No. of

Mov a,#num
Mov Rx,a
Mov a,Rx
Mov Rx,#num
Mov a,add
Mov add,a
Mov add,#num
Mov add1,add2
Mov Rx,add
Mov add,Rx
Mov @Rp,a
Mov a,@Rp
Mov add,@Rp
Mov @Rp,add
Mov
@Rp,#num
Movx a,@Rp
Movx
a,@DPTR
Movx @Rp,a
Movx
@DPTR,a
Movc
a,@a+DPTR
Movc a,
@a+PC
Push add

Pop add

Copy the immediate data num in

to acc
Copy the data from acc to Rx
Copy the data from Rx to acc
Copy the immediate data num in
to Rx
Copy the data from direct
address add to acc
Copy the data from acc to direct
address add
Copy the immediate data num in
to direct address
Copy the data from add2 to add1
Copy the data from direct
address add to Rx
Copy the data from Rx to direct
address add
Copy the data in acc to address
in Rp
Copy the data that is at address
in Rp to acc
Copy the data that is at address
in Rp to add
Copy the data in add to address
in Rp
Copy the immediate byte num to
the address in Rp
Copy the content of external add
in Rp to acc
Copy the content of external add
in DPTR to acc
Copy the content of acc to the
external add in Rp
Copy the content of acc to the
external add in DPTR
The address is formed by adding
acc and DPTR and its content is
copied to acc
The address is formed by adding
acc and PC and its content is
copied to acc
Increment SP and copy the data
from source add to internal RAM
address contained in SP
copy the data from internal RAM
address contained in SP to
destination add and decrement
SP

mode

occupied

cycles used

immediate

register
register

1
1

1
1

immediate

direct

direct

direct

direct

direct

direct

Indirect

Indirect

Indirect

Indirect

Indirect

Indirect

Indirect

Indirect

Indirect

indirect

indirect

Direct

direct

Xch a, Rx
Xch a, add
Xch a,@Rp
Xchd a, @Rp

Exchange the data between acc

and Rx
Exchange the data between acc
and given add
Exchange the data between acc
and address in Rp
Exchange only lower nibble of
acc and address in Rp

Register

Direct

Indirect

indirect

Arithmetic Instructions
The arithmetic instructions are used to performing addition, subtraction, multiplication,
division, and increment and decrement operation on binary data.
The mnemonic used in arithmetic instructions are ADD, ADDC, SUBB, INC, DEC, MUL,
DIV and DA.
The result of most of the arithmetic operation is stored in accumulator except a few
decrement and increment operations.
The arithmetic instructions except increment and decrement instructions modify the flags of
8031/8051
Arithmetic Instructions: Operational description
Mnemonics
Inc a
Inc Rr
Inc add
Inc @rp
Inc DPTR
dec a
dec Rr
dec add
dec @rp
Add a, #num
Add a, Rx
Add a, add
Add a, @Rp

Add 1 to acc
Add 1 to register Rr
Add 1 to the content of add
Add 1 to the content of the address
in Rp
Add 1 to DPTR
Subtract 1 from acc
Subtract 1 from Rr
Subtract 1 from content of add
Subtract 1 from the content of
address
Add the immediate num with acc
and stores result in acc
Add the data in Rx with acc and
stores result in acc
Add the data in add with acc and
stores result in acc
Add the data at the address in Rp
with acc and stores result in acc

Add the immediate num with acc

and carry, stores result in acc
Add the data in Rx with acc and
Addc a, Rx
carry, stores result in acc
Add the data in add with acc and
Addc a, add
carry, stores result in acc
Addc a, @Rp Add the data at the address in Rp
Addc a,#num

Addressing
mode
Register
Register
Direct

No. of bytes
No. of
occupied
cycles used
1
1
1
1
2
1

indirect

Register
Register
Register
Direct

1
1
1
2

2
1
1
1

indirect

immediate

Register

Direct

Indirect

immediate

Register

Direct

Indirect

with acc and carry, stores result in

acc
Subtract immediate num and carry
Subb a, #num
from acc; stores the result in acc
Subtract the content of add and
Subb a, add carry from acc; stores the result in
acc
Subtract the data in Rx and carry
Subb a, Rx
from acc; stores the result in acc
Subtract the data at the address in
Subb a, @Rp Rp and carry from acc; stores the
result in acc
Multiply acc and register B. store
Mul ab
the lower byte of result in acc and
higher byte in B
divide acc by register B. store
div ab
quotient in acc and remainder in B
After addition of two packed BCD
Da a
numbers, adjust the sum to decimal
format

immediate

Register

Direct

Indirect

---

---

---

Logical Instructions:
The logical instructions are used to perform logical AND, OR, Exclusive-OR,
Complement and rotate left and right.
The various mnemonics used for logical instructions are ANL, ORL, XRL, CLR,
CPL, RL, RLC, RR and RRC AND SWAP.
Only the rotate through the carry instruction will affect the flag.
In most of the result of logical instruction is stored in accumulator and in some instructions
the result is stored in RAM/SFR.
Logical Instructions: Operational description
Addressing No. of bytes
No. of
Mnemonics
mode
occupied
cycles used
AND each bit of acc with same
Anl a, #num
bit of immediate num, stores Immediate
2
1
result in acc
AND each bit of acc with same
Anl a, add
bit of content in add, stores result
Direct
2
1
in acc
AND each bit of acc with same
Anl a, Rx
bit of content of Rx, stores result
Register
1
1
in acc
AND each bit of acc with same
Anl a, @Rp
bit of content of add given by Rp,
Indirect
1
1
stores result in acc
AND each bit of acc with same
Anl add, a
bit of direct add num, stores
Direct
2
1
result in add
Anl add, #num AND each bit of direct add with
direct
3
2

orl a, #num
orl a, add
orl a, Rx
orl a, @Rp
orl add, a
orl add, #num
Xrl a, #num
Xrl a, add
Xrl a, Rx
Xrl a, @Rp
Xrl add, a
Xrl add, #num
Clr a
Cpl a
Anl c, b
Anl c, /b
Orl c, b
Orl c, /b
Cpl c

same bit of immediate num,

stores result in add
OR each bit of acc with same bit
of immediate num, stores result
in acc
OR each bit of acc with same bit
of content in add, stores result in
acc
OR each bit of acc with same bit
of content of Rx, stores result in
acc
OR each bit of acc with same bit
of content of add given by Rp,
stores result in acc
OR each bit of acc with same bit
of direct add num, stores result in
add
OR each bit of direct add with
same bit of immediate num,
stores result in add
XOR each bit of acc with same
bit of immediate num, stores
result in acc
XOR each bit of acc with same
bit of content in add, stores result
in acc
XOR each bit of acc with same
bit of content of Rx, stores result
in acc
XOR each bit of acc with same
bit of content of add given by Rp,
stores result in acc
XOR each bit of acc with same
bit of direct add num, stores
result in add
XOR each bit of direct add with
same bit of immediate num,
stores result in add
Clear each bit of acc
Complement each bit of acc
AND carry with given bit b,
stores result in carry
AND carry with complement of
given bit b, stores result in carry
OR carry with given bit b, stores
result in carry
OR carry with complement of
given bit b, stores result in carry
Complement carry flag

Immediate

Direct

Register

Indirect

Direct

direct

Immediate

Direct

Register

Indirect

Direct

direct

Direct
direct

1
1

1
1

--

-----

Cpl b
Clr c
Clr b
Mov c, b
Mov b, c
Setb c
Setb b
Rl a
Rr a
Rlc a
Rrc a
Swap a

Complement bit b
Clear carry flag
Clear given bit b
Copy bit b to carry
Copy carry to bit b
Set carry flag
Set bit b
Rotate acc one bit left
Rotate acc one bit right
Rotate acc one bit left with carry
Rotate acc one bit right with
carry
Exchange upper and lower nibble
of acc

-----------

2
1
2
2
2
1
2
1
1
1

1
1
1
1
2
1
1
1
1
1

--

--

Branching Instructions:
The branching instructions will modify the content of PC so that the program
execution sequence is changed to new address.
There are two types of branching instructions like condition and unconditional
instructions.
In conditional branching the content of PC is changed only if the condition specified
is true.
In unconditional branching the PC is always modified.
The program branching instructions are ACALL, LCALL, RET, AJMP, LJMP, SJMP,
JMP, JZ, JNZ, CJNE, DJNZ and NOP.
Branching Instructions: Mnemonic
Operational description
Jc label
Jnc label
Jb b,label
Jnb b,label
Jbc b,label
Cjne a, add,
label
Cjne
a,
#num, label
Cjne Rx,
#num, label
Cjne @Rp,
#num, label
Djnz Rx,
label
Djnz add,
label

Jump to label if carry is set to 1

Jump to label if carry is cleared to 0
Jump to label if given bit is set to 1
Jump to label if given bit is cleared to 0
Jump to label if given bit is set. Clear the bit
Compare the content of accumulator with the
content of given address and if not equal jump to
label
Compare the content of accumulator with
immediate number and if not equal jump to label
Compare the content of Rx with the immediate
number and if not equal jump to label
Compare the content of location in Rp with
immediate number and if not equal jump to label
Decrement the content of Rx and jump to the
label if it is not zero
Decrement the content of address and jump to
the label if it is not zero

No of bytes
occupied
2
2
3
3
3

No. of cycles
used
2
2
2
2
2

Jz label
Jnz label
Jmp
@a+dptr
Ajmp sadd
Ljmp ladd
Sjmp radd
nop
Acall sadd
Lcall ladd
Ret
reti

Jump to the label if content of accumulator is 0

Jump to the label if content of accumulator is not
0
Jump to the address created by adding the
contents on accumulator and dptr
Take a jump to absolute short range address sadd
Take a jump to absolute long range address sadd
Take a jump to relative address radd
Short form of no operation means do nothing and
go to next instruction
Pushes the content of Acc on stack and load it
will absolute short range address sadd
Pushes the content of Acc on stack and load it
will absolute long range address sadd
returns from subroutine by restoring the Acc
from stack using pop operation
Returns from interrupt subroutine by restoring
Acc from stack using pop operation

2
3
2

2
2
2

Boolean Instructions:
The Boolean variable instructions operate on a particular bit of a data.
These instructions perform clear, complement or move a particular bit of bit addressable
RAM/SFR or carry flag.
If a particular bit is set or cleared then this instruction will transfer the PC address to new
address.
The Boolean instructions are CLR, SETB, CPL, ANL, ORL, MOV, JC and JNC.
BOOLEAN VARIABLE MANIPULATION
Mnemonic
Operational description
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
JC
JNC
JB
JNB
JBC

C
bit
C
bit
C
bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
rel
rel
bit,rel
bit,rel
bit,rel

No of bytes
occupied
Clear Carry
1
Clear direct bit
2
Set Carry
1
Set direct bit
2
Complement Carry
1
Complement direct bit
2
AND direct bit to CARRY
2
AND complement of direct bit to Carry
2
OR direct bit to Carry
OR complement of direct bit to Carry
Move direct bit to Carry
2
Move Carry to direct bit
2
Jump if Carry is set
2
Jump if Carry not set
2
Jump if direct Bit is set
3
Jump if direct Bit is Not set
3
Jump if direct Bit is set & clear bit
3

Oscillator
Period
12
12
12
12
12
12
24
24
2
24
2
24
12
24
24
24
24
24
24

Interfacing to LCD Display

Most projects you create with the 8051 CPU require some form of display. The most
common way to accomplish this is with the LCD (Liquid Crystal Display). LCDs have
become a cheap and easy way to get text display for an embedded system Common display
are set up as 16 to 20 characters by 1 to 4 lines.

UNDERSTANDING LCD
Pin out
8 data pins D7:D0
Bi-directional data/command pins.
Alphanumeric characters are sent in ASCII format.
RS: Register Select
RS = 0 -> Command Register is selected
RS = 1 -> Data Register is selected

 R/W: Read or Write

0 -> Write, 1 -> Read
E: Enable (Latch data)
Used to latch the data present on the data pins.
A high-to-low edge is needed to latch the data.
VEE : contrast control
NOTE: When writing to the display, data is transferred only on the high to low transition of
this signal. However, when reading from the display, data will become available shortly after
the low to high transition and remain available until the signal falls low again.
Display Data RAM (DDRAM)
Display data RAM (DDRAM) is where you send the characters (ASCII code) you want to see
on the LCD screen. It stores display data represented in 8-bit character codes. Its capacity is
80 characters (bytes). Below you see DD RAM address layout of a 2*16 LCD.

In the above memory map, the area shaded in black is the visible display (For 16x2 display) .
For first line addresses for first 15 characters is from 00h to 0Fh. But for second line address
of first character is 40h and so on up to 4Fh for the 16th character.
So if you want to display the text at specific positions of LCD , we require to manipulate
address and then to set cursor position accordingly .
Character Generator RAM (CGRAM)-User defined character RAM
In the character generator RAM, we can define our own character patterns by program. CG
RAM is 64 bytes, allowing for eight 5*8 pixel, character patterns to be defined. However
how to define this and use it is out of scope of this tutorial. So I will not talk any more about
CGRAM
Registers
The HD44780 has two 8-bit registers, an instruction register (IR) and a data register (DR).
The IR stores instruction codes. The DR temporarily stores data to be written into DDRAM
or CGRAM and temporarily stores data to be read from DDRAM or CGRAM. Data written
into the DR is automatically written into DDRAM or CGRAM by an internal operation. .
These two registers can be selected by the register selector (RS) signal. See the table below:
:
Register Selection
RS R/W
Operation
0 0 IR write as an internal operation (display clear, etc.)
0
1

1 Read busy flag (DB7) and address counter (DB0 to DB6)

DR write as an internal operation (DR to DDRAM or
0
CGRAM)
1 DR read as an internal operation (DDRAM or CGRAM to DR)

1
Busy Flag (BF)
When the busy flag is 1, the LCD is in the internal operation mode, and the next instruction
will not be accepted. When RS = 0 and R/W = 1 (see the table above), the busy flag is output

to DB7 (MSB of LCD data bus). The next instruction must be written after ensuring that the
busy flag is 0.
LCD Commands
The LCDs internal controller accept several commands and modify the display accordingly.
These commands would be things like:
Clear screen
Return home
Shift display right/left
Instruction
Decimal
HEX
Function set (8-bit interface, 2 lines, 5*7 Pixels)
56
38
Function set (8-bit interface, 1 line, 5*7 Pixels)
48
30
Function set (4-bit interface, 2 lines, 5*7 Pixels)
40
28
Function set (4-bit interface, 1 line, 5*7 Pixels)
32
20
Entry mode set
See Below See Below
Scroll display one character right (all lines)
28
1E
Scroll display one character left (all lines)
24
18
Home (move cursor to top/left character position)
2
2
Move cursor one character left
16
10
Move cursor one character right
20
14
Turn on visible underline cursor
14
0E
Turn on visible blinking-block cursor
15
0F
Make cursor invisible
12
0C
Blank the display (without clearing)
8
08
Restore the display (with cursor hidden)
12
0C
Clear Screen
1
01
Set cursor position (DDRAM address)
128 + addr
80+ addr
Set pointer in character-generator RAM (CG RAM address)
64 + addr
40+ addr
Entry mode set
This command sets cursor move direction and display shift ON/OFF. There are 4 possible
function set commands; 04, 05, 06, and 07. This command changes the direction the cursor
moves by setting the address counter to increment or decrement. This command is very
important. If you do not understand it you may not see anything or what you actually wanted
to see on LCD screen. I have created 4 animated gifs to demonstrate what the function set
command is all about.
Set cursor position (DDRAM address)
As said earlier if we want to display the text at specific positions of LCD, we require to
manipulate address and then to set cursor position accordingly.
I want to display "MAHESH" in message "Hi MAHESH" at the right corner of first line then
I should start from 10th character.
So referring to table 80h+0Ah= 8Ah.

INTERFACING LCD TO 8051

The 44780 standard requires 3

control lines as well as either 4 or 8
I/O lines for the data bus. The user
may select whether the LCD is to
operate with a 4-bit data bus or an 8bit data bus.
If a 4-bit data bus is used, the LCD
will require a total of 7 data lines.
If an 8-bit data bus is used, the LCD will require a total of 11 data lines.
The three control lines are EN, RS, and RW.
Note that the EN line must be raised/lowered before/after each instruction sent to the LCD
regardless of whether that instruction is read or write, text or instruction. In short, you must
always manipulate EN when communicating with the LCD. EN is the LCD's way of knowing
that you are talking to it. If you don't raise/lower EN, the LCD doesn't know you're talking to
it on the other lines.
Checking the Busy Flag
You can use subroutine for checking busy flag or just a big (and safe) delay.
1.
2.
3.
4.

Set R/W Pin of the LCD HIGH(read from the LCD)

Select the instruction register by setting RS pin LOW
Enable the LCD by Setting the enable pin HIGH
The most significant bit of the LCD data bus is the state of the busy
flag(1=Busy,0=ready to accept instructions/data). The other bits hold the current value
of the address counter.
If the LCD never come out from "busy" status because of some problems ,The program will
"hang," waiting for DB7 to go low. So in a real applications it would be wise to put some
kind of time limit on the delay--for example, a maximum of 100 attempts to wait for the busy
signal to go low. This would guarantee that even if the LCD hardware fails, the program
would not lock up.
CODE EXAMPLE
It is easy (and clean tech. ) to make different subroutines and then call them as we need.
Busy flag checking
ready:
setb P1.7 ;D7 as input
clr P3.6 ;RS=0 cmd
setb P3.5 ;RW=1 for read
again:

Data write Routine

data:
mov P1, A ;move acc. data to port
setb P3.6 ;RS=1 data
clr P3.5 ;RW=0 for write
setb P3.7 ;H->L pulse on E
clr P3.7

Command write Routine

command:
mov P1, A ;move acc. data to port
clr P3.6 ;RS=0 for cmd
clr P3.5 ;RW=0 for write
setb P3.7 ;H->L pulse on E
clr P3.7

setb P3.7 ;H->L pulse on E

clr P3.7
jb P1.7, again
ret

lcall ready
ret

Initialization
initialization:
mov A, #38H ; Initialize, 2-lines, 5X7
matrix.
lcall Command
mov A, #0EH ; LCD on, cursor on
lcall Command
mov A, #01H ; Clear LCD Screen
lcall Command
mov A, #06H ; Shift cursor right
lcall Command

lcall ready
ret

Display clear
clear:
setb p3.7 ;enable EN
clr 3.6 ;RS=0 for cmd.
mov DATA,#01h
clr p3.7 ;disable EN
lcall ready
RET

Displaying "HI"
lcall initialization
lcall clear
mov A,#'H'
acall data
mov A,#'I'
lcall data

Note- As we need to clear the

LCD frequently and not the
whole initialisation , it is better
to use this routine separately.

Let's now try code for displaying text at specific positions.

I want to display "MAHESH" in message "Hi MAHESH" at the right corner of first line then
I should start from 10th character.

So referring to table 80h+0Ah= 8Ah.

So below is code and I don's think that you will need explanation comments.
ASSEMBLY LANGUAGE
lcall Initialization
lcall clear
mov a,#'H'
lcall data
mov a,#'I'
lcall data
mov a,#8ah
lcall command
mov a,#'M'
lcall data
mov a,#'A'
lcall data

mov a,#'H'
lcall data
mov a,#'E'
lcall data
mov a,#'S'
lcall data
mov a,#'H'
lcall data
Interfacing 8279 with 8031/8051 microcontroller:
The 8279 can be interfaced to 8031/8051 controller to provide the keyboard and 7segment LED display.
A simple schematic for interfacing 8279 with 8031/8051 microcontroller is shown.

The of 8279 is mapped as data memory, because the 8031/8051 controller supports
only memory mapping of I/O device, and read and write operation is possible only with
data memory.
The data lines D7- D0 of 8031/8051 are connected to DB7 DB0 lines of 8279.
The address line A0 of 8031/8051 is connected to A0 of 8279 to provide the internal
address.
The address lines A13, A14 and A15 are decoded to generate eight chip select signals,
and in this CS2 (low) are used as chip select for 8279.
The signals RD (Low) and WR (Low) are logically ANDed and used as logic low
enable for decoder and the signal PSEN (Low) is used as logic high enable for decoder.
The clock frequency at X2 pin of 8031/8051 can be divided using any clock divider
circuit to generate 3 MHz clock for 8279.
A RC circuit can be employed to generate the reset signal for 8031/8051 as well as for
8279.
The addresses allotted to 8279 are listed in table.

The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in
encoded scan. (Because in decoded scan, only 4 numbers of 7-segment LEDs can be
interfaced):

In encoded scan the output of scan lines will be binary count. Therefore an external,
3-to-8 decoder is used to decode the scan lines SL0, SL1 and SL2 of 8279 to produce eight
scan lines S0 to S7.

The decoded scan lines S0 and S1 are common for keyboard and display.

The decoded scan lines S2 to S5 are used only for display and the decoded scan lines
S6 and S7 are not used in the system.

Anode and Cathode drivers are provided to take care of the current requirement of
LEDs.

The pnp transistors, BC 158 are used as driver transistors.

The anode drivers are called segment drivers and cathode drivers are called digit
drivers.

The 8279 output the display code for one digit through its output lines (OUT A0 to
OUT A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

The display code is inverted by segment drivers and sent to segment bus.

The scan code is decoded by the decoder and turns ON the corresponding digit driver.
Now one digit of the display character is displayed. After a small interval (10 millisecond, typical), the display is turned OFF (i.e., display is blanked) and the above process
is repeated for next digit. Thus multiplexed display is performed by 8279.

The keyboard matrix is- formed using the return lines, RL 0 to RL3 of 8279 as columns
and decoded scan lines S0 and S1 as rows.

A hexa key is placed at the crossing point of each row and column. A key press will
short the row and column. Normally the column and row line will be high.

During scanning the 8279 will output binary count on SL0 to SL3, which is decoded
by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If
there is a key press then the corresponding column will be zero.

If 8279 detects a key press then it waits for debounce time and again read the columns
to generate key code.

In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key
press. The key code consist of the binary value of the column and row in which the key is
found and the status of shift and control key.
After a scan time, the next row is made zero and the above process is repeated and so on.
Thus 8279 continuously scan the keyboard.

UNIT IV PERIPHERAL INTERFACING 9

Study on need, Architecture, configuration and interfacing, with ICs: 8255, 8259,
8254,8237,8251,8279, - A/D and D/A converters &Interfacing with 8085 & 8051.
Study on need, Architecture, configuration and interfacing, with ICs:
4.1 8255 Architecture, configuration and interfacing with 8085 & 8051
4.2 8259 Architecture, configuration and interfacing with 8085 & 8051
4.3 8254 Architecture, configuration and interfacing with 8085 & 8051
4.4 8237 Architecture, configuration and interfacing with 8085 & 8051
4.5 8251 Architecture, configuration and interfacing with 8085 & 8051
4.6 8279 Architecture, configuration and interfacing with 8085 & 8051
4.7 A/D and D/A converters &Interfacing with 8085 & 8051.
4.1 8255 Architecture, configuration and interfacing with 8085 & 8051
4.2 8259 Architecture, configuration and interfacing with 8085 & 8051
4.3 8254 Architecture, configuration and interfacing with 8085 & 8051
4.4 8237 Architecture, configuration and interfacing with 8085 & 8051
4.5 8251 Architecture, configuration and interfacing with 8085 & 8051
4.6 8279 Architecture, configuration and interfacing with 8085 & 8051
4.7 A/D and D/A converters &Interfacing with 8085 & 8051.

UNIT V MICRO CONTROLLER PROGRAMMING & APPLICATIONS 9

Data Transfer, Manipulation, Control Algorithms& I/O instructions Simple programming
exercises key board and display interface Closed loop control of servo motor- stepper
motor control Washing Machine Control.