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Vendor: Xilinx
Current readme.txt Version: 1.0.0
Date Last Modified: 03JUN2014
Date Created: 03JUN2014
Associated Filename: xapp1188.zip
Associated Document:
XAPP1188, FPGA Configuration from SPI Flash Memory using the Zynq-7000
All Programmable SoC
Supported Device(s): 7-series FPGA devices
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This readme file contains these sections:
1.
2.
3.
4.
5.
6.
7.

REVISION HISTORY
OVERVIEW
SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
DESIGN FILE HIERARCHY
INSTALLATION AND OPERATING INSTRUCTIONS
OTHER INFORMATION (OPTIONAL)
SUPPORT

1. REVISION HISTORY
<Describe changes to the reference design ZIP file using this format>
Readme
Date
Version
Revision Description
=========================================================================
01JUL2014 1.0
Initial Xilinx release.
=========================================================================
2. OVERVIEW
This readme describes how to use the files that come with XAPP1188
The main focus of this example is to demonstrate how the FPGA configuration is
accomplished by a single function XQspiPs_PolledTransfer(). It sends out the
read command to the PROM and reads the configuration bitstream out. As explaine
d
in the XAPP118 this effectively delivers the bitstream directly to the target F
PGA.
This example assumes the target Zynq SoC programmable logic is configured by
the bitstream created by the Vivado project associated with XAPP1188
The Vivado hardware design targets a Zynq evaluation board HW-Z7-ZC702. The des
ign
was verified between the ZC702 board and an internal Kintex-7 board based on th
e
connections described in XAPP1188.
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
* Xilinx Vivado 2013.4 or higher
* Xilinx Vivado SDK 2013.4 or higher
4. DESIGN FILE HIERARCHY
<Describe the file hierarchy by type (HDL files, simulation files, etc.)>
<For example:>
The directory structure underneath this top-level folder is described
below:
/<target dir>

|
+----/SDK
|
This is the Vivado SDK project directory. It contains the software code
for
|
Zynq processor to read configuration bitstream from the QSPI PROM on ZC7
02
|
board.
|
+----/Vivado
This is the Vivado h/w project for Zynq. It implements the GPIO attached t
o the
AXIGP on the PL side. The GPIOs are used to monitor the FPGA configuraton
control
pins.
5. INSTALLATION AND OPERATING INSTRUCTIONS
1)
2)
3)
4)

unzip the reference design zip file xapp118.zip to a directory

Launch Vivado 2013.4 and open <target dir>/Vivado/XAPP1188.xpr
Implement the design and build the bitstream for Zynq
Launch SDK 2013.4 and change workspace to <target dir>/SDK

6. OTHER INFORMATION
None
7. SUPPORT
To obtain technical support for this reference design, go to
www.xilinx.com/support to locate answers to known issues in the Xilinx
Answers Database or to create a WebCase.