Vlsi 2015 Ieee Titles

VLSI IEEE TITLES-2015
EMTECH LABZ
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Mobile : +91 875 488 0168 e-mail : emtechlabz.info@gmail.com
VLSI IMAGE PROCESSING

ELIP01
Median Filtered Image Quality Enhancement and Anti-Forensics via

Variational Deconvolution
ELIP02
Utilizing Image Scales Towards Totally Training Free Blind Image Quality
Assessment
ELIP03
A Source-Channel Coding Approach to Digital Image Protection and SelfRecovery
ELIP04
Variable-Length Signature for Near-Duplicate Image Matching
ELIP05
Edge-Preserving Image Denoising via Group Coordinate Descent on the GPU
ELIP06
Content-Based Image Retrieval Using Features Extracted From HalftoningBased Block Truncation Coding
ELIP07
Fast Edge-Aware Processing via First Order Proximal Approximation
ELIP08
A Novel Image Representation via Local Frequency Analysis for Illumination

Invariant Stereo Matching
ELIP09
An Efficient DCT-Based Image Compression System Based on Laplacian

Transparent Composite Model
ELIP10
Multiview Matrix Completion for Multilabel Image Classification
SIGNAL PROCESSING
ELSP01
A Memristor-Based Continuous-Time Digital FIR Filter for Biomedical Signal

Processing
ELSP02
Razor Based Programmable Truncated Multiply and Accumulate, EnergyEMTECH LABZ


EMTECH LABZ
Reduction for Efficient Digital Signal Processing

ELSP03
A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing
ELSP04
Space-Time Adaptive Processing Using Pattern Classification
ELSP05
On Sparse Methods for Array Signal Processing in the Presence of

Interference
ELSP06
Identification of SM-OFDM and AL-OFDM signals based on their secondorder cyclostationarity
ELSP07
High-Speed Data Processing Module for LLRF
ELSP08
An FPGA-Based Multicore System for Real-Time Bearing Fault Diagnosis

Using Ultrasampling Rate AE Signals
ELSP09
Error analysis of subaperture processing in 1-D ultrasound arrays
ELSP10
Signal Design for Context Aware Distributed Radar Sensing Networks Based
on Wavelets
VIDEO PROCESSING
ELVP01
A Low-Complexity Embedded Compression Codec Design With Rate Control

for High-Definition Video
ELVP02
Optimal Scalable Video Scheduling Policies for Real-Time Single- and

EMTECH LABZ

EMTECH LABZ
Multiuser Wireless Video Networks
ELVP03
Cross-Layer Resource Allocation for Video Streaming Over OFDMA

Cognitive Radio Networks
ELVP04
Adaptive General Scale Interpolation Based on Weighted Autoregressive

Models
ELVP05
SIMD(Single Instruction Multiple data) Acceleration for HEVC(High

Efficiency Video Codec) Decoding
ELVP06
Global Motion Assisted Low Complexity Video Encoding for UAV

Applications
ELVP07
Fusion of Global and Local Motion Estimation Using Foreground Objects for
Distributed Video Coding
ELVP08
An Effective Ultrasound Video Communication System Using Despeckle

Filtering and HEVC
ELVP09
Efficient In-Loop Filtering Across Tile Boundaries for Multi-Core HEVC

Hardware Decoders With 4 K/8 K-UHD Video Applications
ELVP10
A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 HighTier Applications
EMTECH LABZ

EMTECH LABZ
VLSI COMMUNICATION SYSTEM
ELCS01
Differential Secret Sharing in Wireless Networks
ELCS02
Parallel Monitoring for the Next Generation of Train Control Systems
ELCS03
A high-performance
blue filter for a white-led-based
visible light
communication system
ELCS04
An Effective Ultrasound Video Communication System Using Despeckle

Filtering and HEVC
ELCS05
Transmission media for an SDM-based optical communication system
ELCS06
One-Bit Sigma-Delta Modulator for Nonlinear Visible Light Communication

Systems
ELCS07
Detection of False Data Injection Attacks in Smart Grid Communication

Systems
ELCS08
Coded Distributed Diversity: A Novel Distributed Reception Technique for

Wireless Communication Systems
EMTECH LABZ

EMTECH LABZ
ELCS09
Mobile Communication Systems in the Presence of Fading/Shadowing, Noise

and Interference
ELCS10
Design and Implementation of Smart Home Control Systems Based on

Wireless Sensor Networks and Power Line Communications
LOW POWER VLSI
ELLP01
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks
ELLP02
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator
ELLP03
Algorithm and Architecture for a Low-Power Content-Addressable Memory

Based on Sparse Clustered Networks
ELLP04
Reliable
Low-Power
Multiplier
Design
Using
Fixed-Width
Redundancy Block
ELLP05
Low-Power Programmable PRPG With Test Compression Capabilities
ELLP06
Low-Cost On-Chip Clock Jitter Measurement Scheme
EMTECH LABZ
Replica

EMTECH LABZ
ELLP07
Low power sensor design for IoT and mobile healthcare applications
ELLP08
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee

SoCs
ELLP09
A Low-Cost Hardware Architecture for Illumination Adjustment in RealTime Applications
ELLP10
A Low Power and High Sensing Margin Non-Volatile Full Adder Using
Racetrack Memory
ELLP11
A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point

Arithmetic
ELLP12
Variable Latency Speculative Han-Carlson Adder
ELLP13
Reliable Radix-4 Complex Division for Fault-Sensitive Applications.
ELLP14
Recursive Approach to the Design of a Parallel Self-Timed Adder
ELLP15
Design and Analysis of Approximate Compressors for Multiplication.
ELLP16
High-Speed
Demonstration
of
Bit-Serial
Floating-Point
Adders
and
Multipliers Using Single-Flux-Quantum Circuits

ELLP17
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit

Encoding.
ELLP18
A Modified Partial Product Generator for Redundant Binary Multipliers.
EMTECH LABZ

EMTECH LABZ
Network On Chip/System on chip
ELNOC01 An Offline Method for Designing Adaptive Routing Based on Pressure Mode
ELNOC02 NoC-based Protection for SoC Time-Driven Attacks
ELNOC03 A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks
ELNOC04 Architecture Support for Task Out-of-Order Execution in MPSoCs
ELNOC05 A High-Performance On-Chip Bus (MSBUS) Design and Verification
TESTING
ELTE01
A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3

Dimensional Memories
ELTE02
Low-Power Programmable PRPG With Test Compression Capabilities
ELTE03
Fault Analysis-Based Logic Encryption
ELTE04
FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion

Using Dummy Logic
ELTE05
Novel Test-Mode-Only Scan Attack and Countermeasure for CompressionBased Scan Architectures
ELTE06
Key Updating for Leakage Resiliency with Application to AES

Modes of Operation.
EMTECH LABZ

EMTECH LABZ
ELTE07
Test Compression for Circuits with Multiple Scan Chains.
BIO-MEDICAL
ELBM01
Implementation of Medical Image Segmentation using Virtex FPGA kit
ELBM02
Novel VLSI Architecture for Real Time Medical Image Segmentation
ELBM03
Implementation ofNB PRY Transceiver of IEEE 802.15.6 WBAN on FPGA
ELBM04
Low Power Sensor Design for IoT and Mobile Healthcare Applications
ELBM05
A Flexible Multichannel EEG Feature Extractor and Classifier for Seizure

Detection
ELBM06
Medical Data Compression and Transmission in Wireless Ad Hoc Networks
ELBM07
Deoxyribonucleic Acid (DNA) for a Shared Secret Key Cryptosystem with

Diffie Hellman Key sharing technique
CRYTOGRAPHY
ELCY01
An Encryption Scheme Using Chaotic Map and Genetic Operations for

Wireless Sensor Networks
ELCY02
Implementation of a New Lightweight Encryption Design for Embedded

Security
ELCY03
Key Updating for Leakage Resiliency With Application to AES Modes of

Operation
EMTECH LABZ

EMTECH LABZ
EMTECH-LABZ provides Educational & Development boards for Industries and

has been at the forefront of technological and market innovation in FPGA and
Embedded products for High Performance Computing applications and Embedded
development.
We offer certified project internship for B.E/B.Tech, M.E/M.Tech, PhD candidates
in the field of VLSI,EMBEDDED,MATLAB, and Software and firmware
developments. Our deep industry knowledge enables us to provide you with
innovative ideas that help you improve productivity and innovative ideas.
VLSI
Bio medical
Matlab
GPS based
DSP
GSM/GPRS based
Image processing
Image processing
Audio and Video
Automation
processing
Neural network
Wireless projects
Nanotechnology
Robotics
Security system
Fuzzy logic
Cryptography
Artificial intelligence
Communication system
Zig-bee
Testing
Bluetooth
Networking
Our Support:
Innovative project idea implementation.
IEEE transactions papers implementation.
Providing high-end technical support.
Providing latest Hardware & EDA support.
Hardware support
EMTECH LABZ

EMTECH LABZ
Providing ideas and assist to publish the papers on journals.
Assisting for project thesis preparation.
Providing Industry enabled project Internship certificate.
We have all kinds of High end FPGA boards and CPLDs, We offer complete hands on training
in FPGAs with real-time exposure. Also we provide training in EDA tools such as Modelsim,
Questasim, Quartus II , XILINX ISE, MATLAB, NIOS II IDE, Tanner, HSPICE.
For any Enquires contact us @

E-mail id: emtechlabz.info@gmail.com
Mobile No: +91 875 488 0168 / +91 9095188016
EMTECH LABZ

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VLSI IEEE TITLES-2015

VLSI IMAGE PROCESSING

Median Filtered Image Quality Enhancement and Anti-Forensics via

A Source-Channel Coding Approach to Digital Image Protection and SelfRecovery

Variable-Length Signature for Near-Duplicate Image Matching

Edge-Preserving Image Denoising via Group Coordinate Descent on the GPU

Fast Edge-Aware Processing via First Order Proximal Approximation

A Novel Image Representation via Local Frequency Analysis for Illumination

An Efficient DCT-Based Image Compression System Based on Laplacian

Multiview Matrix Completion for Multilabel Image Classification

A Memristor-Based Continuous-Time Digital FIR Filter for Biomedical Signal

Razor Based Programmable Truncated Multiply and Accumulate, EnergyEMTECH LABZ

VLSI IEEE TITLES-2015

Reduction for Efficient Digital Signal Processing

A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing

Space-Time Adaptive Processing Using Pattern Classification

On Sparse Methods for Array Signal Processing in the Presence of

Identification of SM-OFDM and AL-OFDM signals based on their secondorder cyclostationarity

High-Speed Data Processing Module for LLRF

An FPGA-Based Multicore System for Real-Time Bearing Fault Diagnosis

Error analysis of subaperture processing in 1-D ultrasound arrays

A Low-Complexity Embedded Compression Codec Design With Rate Control

Optimal Scalable Video Scheduling Policies for Real-Time Single- and

VLSI IEEE TITLES-2015

Multiuser Wireless Video Networks

Cross-Layer Resource Allocation for Video Streaming Over OFDMA

Adaptive General Scale Interpolation Based on Weighted Autoregressive

SIMD(Single Instruction Multiple data) Acceleration for HEVC(High

Global Motion Assisted Low Complexity Video Encoding for UAV

An Effective Ultrasound Video Communication System Using Despeckle

Efficient In-Loop Filtering Across Tile Boundaries for Multi-Core HEVC

VLSI IEEE TITLES-2015

VLSI COMMUNICATION SYSTEM

Differential Secret Sharing in Wireless Networks

Parallel Monitoring for the Next Generation of Train Control Systems

blue filter for a white-led-based

An Effective Ultrasound Video Communication System Using Despeckle

Transmission media for an SDM-based optical communication system

One-Bit Sigma-Delta Modulator for Nonlinear Visible Light Communication

Detection of False Data Injection Attacks in Smart Grid Communication

Coded Distributed Diversity: A Novel Distributed Reception Technique for

VLSI IEEE TITLES-2015

Mobile Communication Systems in the Presence of Fading/Shadowing, Noise

Design and Implementation of Smart Home Control Systems Based on

LOW POWER VLSI

A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

Algorithm and Architecture for a Low-Power Content-Addressable Memory

Low-Power Programmable PRPG With Test Compression Capabilities

Low-Cost On-Chip Clock Jitter Measurement Scheme

VLSI IEEE TITLES-2015

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee

A Low-Cost Hardware Architecture for Illumination Adjustment in RealTime Applications

A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point

Variable Latency Speculative Han-Carlson Adder

Reliable Radix-4 Complex Division for Fault-Sensitive Applications.

Recursive Approach to the Design of a Parallel Self-Timed Adder

Design and Analysis of Approximate Compressors for Multiplication.

Multipliers Using Single-Flux-Quantum Circuits

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit

A Modified Partial Product Generator for Redundant Binary Multipliers.

VLSI IEEE TITLES-2015

Network On Chip/System on chip