Generate Statements

Dr.Ravi Sindal
Professor,Deptt of E&TC
IET,DAVV,Indore

Generate Statements
Concurrent statements can be conditionally
selected or replicated during the elaboration
phase using the generate statement. There
are two forms of the generate statement.
Using the for-generate scheme, concurrent
statements can be replicated a predetermined
number of times.
With the if-generation scheme, concurrent
statements can be conditionally selected
for execution.
Dr.Ravi Sindal,IET,DAVV,Indore

 The format of a generate statement using the

for-generation scheme is
generate-label:
for
generate-identifier in
discrete-range generate
concurrent-statements
end generate [ generate-label];

Dr.Ravi Sindal,IET,DAVV,Indore

 The values in the discrete range must be

globally static, that is, they must be
computable at elaboration time.
During elaboration, the set of concurrent
statements are replicated once for each
value in the discrete range.
There is an implicit declaration for the
generate identifier within the generate
statement, and therefore, no declaration
for this identifier
is required.
Dr.Ravi Sindal,IET,DAVV,Indore
4

A 4-bit full-adder

Dr.Ravi Sindal,IET,DAVV,Indore

entity FULL_ADD4 is
port (A, B: in BIT_VECTOR(3 downto 0); CIN: in BIT;
SUM: out BIT_VECTOR(3 downto 0); COUT: out BIT);
end FULL_ADD4:
architecture FOR_GENERATE of FULL_ADD4 is
component FULL_ADDER
port (A, B, C: in BIT; COUT, SUM: out BIT);
end component;
signal CAR: BIT_VECTOR(4 downto 0);
begin
CAR(0) <= CIN;
GK: for K in 3 downto 0 generate
FA: FULL_ADDER port map (CAR(K), A(K), B(K),
CAR(K+1),SUM(K));
end generate GK;
COUT <= CAR(4);

end FOR_GENERATE;
Dr.Ravi Sindal,IET,DAVV,Indore

 After elaboration, the generate statement is

expanded to
FA(3): FULL_ADDER port map (CAR(3), A(3), B(3),
CAR(4), SUM(3));
FA(2): FULL_ADDER port map (CAR(2), A(2), B(2),
CAR(3), SUM(2));
FA(1): FULL_ADDER port map (CAR(1), A(1), B(1),
CAR(2), SUM(1));
FA(0): FULL_ADDER port map (CAR(0),
A(0), B(0),
CAR(1), SUM(0));
Dr.Ravi Sindal,IET,DAVV,Indore

 The body of the generate statement can

also have other concurrent statements.
For example, in the previous architecture
body,
the
component instantiation
statement could be replaced by signal
assignment statements like given on next
slide
Dr.Ravi Sindal,IET,DAVV,Indore

G2: for M in 3 downto 0 generate

SUM(M) <= (A(M) xor B(M)) xor CAR(M);
CAR(M+1 ) <= (A(M) and B(M)) and
CAR(M);

end generate G2;

Dr.Ravi Sindal,IET,DAVV,Indore

If-generation scheme

genarate-label: expression generate

concurrent-statements
end generate [ generete-label ] ;

Dr.Ravi Sindal,IET,DAVV,Indore

10

A 4-bit counter

Dr.Ravi Sindal,IET,DAVV,Indore

11

entity COUNTER4 is
port (COUNT, CLOCK: in BIT; Q: buffer BIT_VECTOR(0 to 3));
end COUNTER4;
architecture IF_GENERATE of COUNTER4 is
component D_FLIP_FLOP
port (D, CLK: in BIT; Q: out BIT);
end component;
begin
GK: for K in 0 to 3 generate
GKO: if K = 0 generate
DFF: D_FLIP_FLOP port map (COUNT, CLOCK,
Q(K));
end generate GK0;
GK1_3: if K > 0 generate
DFF: D_FLIP_FLOP port map (Q(K-1), CLOCK, Q(K));
end generate GK1_3;
end generate GK;

end IF_GENERATE;
Dr.Ravi Sindal,IET,DAVV,Indore

12

 A simpler example is when a buffer is to

be selected that has different delays
based on the value of a constant

Dr.Ravi Sindal,IET,DAVV,Indore

13

GA: if USER_WANTS = LOW_DELAY generate

Z <= A after 2 ns;
end generate;
GB: if USER_WANTS = MEDIUM_DELAY generate
Z <= A after 10 ns;
end generate;
GC: if USER_WANTS = HIGH_DEU\Y generate
Z <= A after 25 ns;

end generate;
Dr.Ravi Sindal,IET,DAVV,Indore

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