CURRICULUM VITAE

SHIVARAM VENKATESH N
nv673@snu.edu.in, venkateshshivaram@yahoo.com

# 43 APN NAGAR
Selaiyur
Chennai - 600 073.

08449022488(M) 09789841916 (M) 044-22290418 (R)

Career Objective:
To secure a challenging position where I can effectively contribute my skills as VLSI Engineer,
possessing competent Technical Skills.
Courses about to Pursue at STMicroelectronics:
VLSI Design and Test Flow, Memory Design, Mixed Signal Design and Multimedia Computing.
Educational Qualifications:

Discipline/
Examination
Specialization
M.Tech*

B.E

School/college

Board/
University

VLSI Systems
and Technology

School of
Engineering

Shiv Nadar
University

Electronics and
Communication
Engineering

S M K Fomra
Institute of
Technology

Intermediate

Science +
Maths Stream

S. S. C

S.S.C

Year of
Passing

Percentage/
GPA

2014*

6.22*

Anna University

2012

7.78

Kendriya Vidyalaya
No 2 Tambaram

C.B.S.E.

2008

74.2%

Kendriya Vidyalaya
No 2 Tambaram

C.B.S.E.

2006

83.2%
*Upto 1st Semester

Computer Skills:
Languages

C, C++.

Operating Systems

Windows 2000/XP/07.

Software Packages

Matlab 10.0, PSpice, TSpice, L-Edit, S-Edit, W-Edit, Xilinx 11.1, Modelsim
6.4, Microwave CST 10.0.

Achievements:
Participated in Inter-School Mathematics competition conducted by Madras
Christian College and won 3rd prize in Mathematical Quiz.
Participated in Patrol leader cum Tritiya Sopan Scouting camp.
Won Governors Award in Scouting.

 Presented Paper in National Conference conducted by Saveetha Engineering

College Sponsored by Directorate of Atomic Energy, Govt. of India, Council of
Scientific and Industrial Research, Govt. of India.
Presented Paper in International Conference conducted by Sri Lakshmi Ammal
Engineering College, Tamil Nadu.
Won Best Conference Paper Award at the National Conference sponsored by
IEEE, held at VGI Group of Institution, Uttar Pradesh

Academic Project
Project1:

Block truncation using Genetic Algorithm

Software Package Used for Implementation:

Operating System:
Windows XP.

MATLAB 10.0

DESCRIPTION:
In this project, the high level Image compression is obtained for both gray level and color
images using Block truncation method. The algorithm used for implementing block truncation is a
novel and unique technique called as Genetic Algorithm. To show the difference between our
compression method and other method, we go in for Vector Quantization technique using Lindey Buzo
Gray(LBG) algorithm and compare both the results obtained for various image parameters. The results
show that the Genetic algorithm used yields a better result.
Project2:
An EBG based Dual frequency Microstrip Patch Antenna Array for RFID
Applications
Software Package Used for Implementation:
Operating System:
Windows07.

MICROWAVE CST STUDIO 10.0

DESCRIPTION:
The objective of this project is to design and implement a 2 * 2 Microstrip Patch Antenna
Array for RFID application using EBG structures. Generally EBG structures are used for generating
narrowband antenna. Here in this project, we modify the properties of EBG structures thereby
producing wideband signals by introducing the concept of Spiral Ground Planes. Then we modify our
designed antenna for radiating Dual Frequency by doing appropriate design modification. The
designed antenna is then fabricated and tested. .
Project3:

Logical Level Capacitance and Power Modelling for Digital Logic Circuits

Software Package Used for Implementation:

Operating System: Windows07

TANNER SPICE

DESCRIPTION:
The calculation of Power for CMOS circuit at the logical level will help in Power Optimization
problem which is a big constrain, as the Power specification plays a key role in the design of MOS in
SM and DSM technology. The Capacitances plays a vital role in Power calculation, so Modelling of it
plays a primary role. In this Literature, the Capacitance Modelling is done to reduce the Power
Dissipation by designing the former at the Logical Level. The Work Carried out is shown in
comparison with the traditional results. It is seen that the output gets bettered after the circuit is
modelled according to this literature.

Project4:
Image Compression and Spectral Analysis of Signals using Binary Discrete Cosine
Transform and Binary Hartley Transform using Walsh Hadamard Transform
Software Package Used for Implementation:
MATLAB 10.0
Operating System: Windows08
To develop the binary version of Discrete cosine transform (DCT) and Hartley transform (HT)
with the help of Walsh-Hadamard transform (WHT), establishing a relation between them. And using
the transform in signal processing applications like Image Compression and Spectral Analysis of
Signal. The method of approximating the given transform by exploiting WHT is used here. The
resulting transform approximates the given transform while maintaining the properties of WHT. This
is used to develop binary DCT (BDCT) and binary DHT (BDHT) and then we will consider the use of
these transform in Image compression and Spectral Analysis of Signal.
Project5:
Low Power Modelling of Nano-Scale Adders by Capacitance Modelling
Software Package Used for Implementation:
TANNER SPICE
Operating System: Windows07
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is
presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new
design, and optimized another one, all with the goal to reduce the static power consumption. To further
reduce the Power consumption, the Capacitance modelling is done. The design has been simulated and
evaluated using the DSM technology tool.

Personal Profile:
Name
Fathers Name
Sex
Marital Status
Nationality
Hobbies
Permanent Address

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Phone No
Date of Birth

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Shivaram Venkatesh N
Nellaiappan S
Male
Single
Indian
Cooking, Reading and listening to songs.
# 43 APN Nagar
Selaiyur
Chennai 600 073
08449022488
22-10-1990

Declaration:
I hereby declare that the above-mentioned information is correct up to my knowledge
and I bear the responsibility for the correctness of the above-mentioned particulars.

Place: Greater Noida

(Shivaram Venkatesh N)