MODELING AND DIGITAL CONTROL IMPLEMENTATION OF

BIDIRECTIONAL STEP-UP STEP-DOWN DC-DC CONVERTERS FEATURING

THE ZETA-SEPIC

Adriano Ruseler, Ivo Barbi

Federal University of Santa Catarina - UFSC, Power Electronics Institute - INEP
PO box 5119, ZIP code 88040-970, Florianópolis, SC, BRAZIL
ruseler@inep.ufsc.br, ivobarbi@inep.ufsc.br

Abstract—This paper deals with the current control of the

bidirectional Zeta-Sepic DC-DC converter. By means of the state
average method, the transfer function representing the ratio of
the input inductor current to the duty-cycle is deducted and val-
idated by simulation. A digital controller is proposed, analyzed,
designed and simulated. The proposed digital controller is tested
on a 50 V input, 50 V, 500 W output and 50 kHz switching
frequency, using a Texas Instruments DSP TMS 320F2812. The
experimental results obtained in the laboratory agree well with
the results predicted by theoretical analysis.
Fig. 1. Operation Modes
Keywords—Zeta-SEPIC, Bidirectional, DC-DC Converter.

I. I NTRODUCTION
In meaning of power flow, the DC-DC converters can be
classified as unidirectional or bidirectional,which can be sub-
divided as isolated and non-isolated. Converters bidirectional
topologies mainly derive from the basics ones. For a buck
and boost non-isolated derived topology, sources may have
different voltage levels because of the fact that in one power
flow direction the converter operates as a step-down and in
other direction as a step-up converter.
This paper presents a non-isolated converter that operates
in step-up and step-down mode no matter in what direction
the power is flowing. The basics topologies used, are the Zeta
converter and the SEPIC converter. The junction of these two
converters forms the Zeta-Sepic bidirectional converter, which
in addiction is a natural isolated topology [1], [2], [3].
A complete analysis for the Zeta-Sepic converter operating
in the continuous conduction mode (CCM) is made, beginning
from converter circuit explanation to a practical validation of
the theoretical study. The state-space averaging technique was
used to model the converter resulting in a compact form to
represent the converter dynamics, being suitable for use in
software designed to handle matrices as MATLAB. The union
of the two fourth-order converters results in one third-order
converter, which means a simplest control strategy in compare
of the Zeta or SEPIC control structures.
II. T HE Z ETA -SEPIC B IDIRECTIONAL C ONVERTER
T OPOLOGY
The Zeta-SEPIC Bidirectional converter is the composition
of two classical converters, the Zeta and SEPIC converters.
What converter is active, depends on what direction the power
flows. For example, if power flows from source Va to Vb , the
Zeta converter is active.
Fig. 2. Converter conductions losses considered.
On other hand, power flowing from source Vb to Va the
SEPIC converter is active. For convenience this two states are
called Zeta Mode and SEPIC Mode respectively, as show in
Fig. 1.
A. Operation principle and circuit states
The converter operates in continuous conduction mode
(CCM). Using complementary commands there are two circuit
states within one switching period. Fig. 3 shows the two circuit
states. Circuit state A occurs when MOSFET Sa is conducting
and circuit state B when MOSFET Sb is conducting.
B. Main waveforms of the bidirectional Zeta-SEPIC converter
The Zeta-Sepic converter waveforms are the same of the
Zeta when in Zeta mode and the SEPIC converter when in
SEPIC mode, as shown in Fig. 4.
III. S TATE S PACE AVERAGED M ODEL
Sepic converter was modeled using the state space averaging
technique. The converter operates in continuous conduction
mode having two power states defined by the switch Sa
position. The initial step in the state space modeling is
writing the differential equations that describes the converter in
 diLa
      
dt −(RV a + RLa ) −RV a 0 iLa 1 0  
diLb va
K dt
= −RV a −(RV a + RCab + RLb ) 1   iLb  +  1 −1  (1)
dvCab vb
dt
0 −1 0 vCab 0 0 | {z }
| {z } | {z } | {z } u
Aa x Ba
diLa
      
dt −(RCab + RLa ) 0 −1 iLa 0 0  
diLb va
K dt
= 0 −RLb 0   iLb  + 0 −1
  (2)
dvCab vb
dt
1 0 0 vCab 0 0 | {z }
| {z } | {z } | {z } u
Ab x Bb
   
~ + ~x̂) 
d(X n o    n o  
K =A a (D + ˆ + Ab 1 − (D + d)
d) ˆ  X ˆ + Bb 1 − (D + d)
~ + ~x̂ + Ba (D + d) ˆ  U ~ + ~û (3)
dt 
| {z }
 
| {z }

A Bu

inductors currents and capacitors voltages. The input u vector

contains the independent inputs of the system such as the
sources Va and Vb voltages. The next step is to average each
state equation matrix by the duty of the corresponding circuit
state, for example A = Aa d + Ab (1 − d) being d the duty
cycle. The system equation (4), (5) and (6) represents the steps
for linearization and ac perturb about a quiescent point.
xiT s
dh~
K = Ah~xiT s + Buh~uiT s
dt (4)
h~y iT s = Ch~xiT s + Eh~uiT s

hdiT s = D + dˆ
h~xiT s = X~ + ~x̂
Fig. 3. Circuit state A (upper) and circuit state B (lower). (5)
h~uiT s = U + ~û
~
~ + ~ŷ
h~y iT s = Y
~ ~
K d(X+ x̂)
= A(X~ + ~x̂) + Bu(U
~ + ~û)
dt (6)
Y + ŷ = C(X + x̂) + E(U + ~û)
~ ~ ~ ~ ~

Defining the output vector y equal to the state vector x, the

Fig. 4. Main waveforms of the Zeta-SEPIC bidirectional converter operating
in Zeta Mode (left) and in SEPIC Mode (right).
each circuit state. The equation (1) represents the differential
equations for the State A, including the conduction losses.
In the same way, the differential equations are represented
in matrix form (2) for the State B.
Let the x vector be the state variables, which are the
C matrix is the identity. For the case in study, the E matrix
is zero, so the working system for modeling the converter is
shown in (3) .
 
La 0 0
K =  0 Lb 0  (7)
0 0 Cab
A. Steady state analysis, the DC model
A steady state analysis is required in order to specify the
converter components and implement a prototype. Developing
equation (3) and collecting the DC terms, the system (8) is
archived. Note that to obtain the steady state for the converter
including or not the nonidealities the only change is made in
matrix Aa and Ab , this characteristic justifies the use of state
averaging technique to model the converter.
The system unknowns for the converter operating in Zeta
mode are D, ILa and VCab . For the converter operating in
SEPIC mode they are D, ILb and VCab .
  
ILa  
Va
0 = [Aa · D + Ab (1 − D)] ·  ILb  + [Ba · D + Bb (1 − D)] · (8)
Vb
VCab
−1  
−−→

x̂(s)  ~ + (Ba − Bb )U
~
H(s) = = K · s − [Aa · D + Ab (1 − D)] (Aa − Ab )X (9)

ˆ
d(s) | {z } | {z }

A Bd
 
(D − 1) · RCab − D · RV a − RLa −D · RV a −1 + D
A= −D · RV a −D · (RV a + RCab ) − RLb D  (10)
1−D −D 0
 
(RCab − RV a ) ILa − RV a · ILb + VCab + Va
Bd =  −RV a · ILa − (RV a + RLa ) ILb + VCab + Va  (11)
−ILa − ILb

TABLE I TABLE II
C ONVERTER PARAMETERS AND CONDUCTION RESISTANCES . S TEADY STATE OPERATION POINTS OF THE Z ETA -S EPIC BIDIRECTIONAL
CONVERTER WITH COMPONENTS RESISTANCES .
Parameter Value Resistance
Parameter Zeta Mode SEPIC Mode
La 347 µH 0.17 Ω
Lb 233 µH 0.197 Ω ILa 12.6537 A -10.4167 A
Cab 58 µF 0.003 Ω ILb 10.4167 A -12.4356 A
Va 48 V 0.2 Ω VCab 47.9010 V 47.3210 V
Vb 48 V 0.2 Ω D 0.5485 0.4558

As an example, the static gain can be obtained solving
(8) for the ideal converter resulting in equation (12) which
is identical to the static gain of the Zeta and to the SEPIC
converters.
Vb D 4.289e5s2 + 9.83e8s + 1.242e13
= =G (12)
Va 1−D
B. Modeling the converter dynamics
The converter dynamics model is obtained by manipulating
equation (3) and selecting the first-order terms. Applying
the Laplace transform and manipulating the system to relate
the state variables against the converter duty cycle drives to
equation (9).
C. Converter non-idealities
As an attempt to simplify the controller design, the converter
conduction losses are considered. The MOSFET is considered
to be ideal because he operates as a diode or as a switch de-
pending on the current direction, avoiding unnecessary model
complexity. Doing so, the system (9) remains the same in
Zeta and SEPIC modes. Table I lists the prototype parameters
values and Table II lists the steady state values necessaries to
obtain the converter model.
Applying the parameters listed in Table I and Table II for
the converter operating in Zeta mode in equations (9), (10)
and (11) the transfer function (13) that relates the inductor Lb
current with the duty cycle is obtained.
3.917e5s2 − 7.43e8s + 7.788e12
GiLb,zeta (s) = (13)
s3 + 2133s2 + 3.331e7s + 4.302e10
For the converter operating in SEPIC mode the transfer
function relates the inductor Lb current with the duty cycle
as in (2.10).
GiLb,sepic (s) = (14)
s3 + 2000s2 + 3.093e7s + 3.957e10
Model validation is made by the use of ac analysis (Fig.
5) in PSIM software. The start frequency is 12.5 Hz and end
frequency of 12.5 kHz, with 51 data points and excitation
source amplitude of 0.005. The PSIM generate data are
imported into MATLAB and displayed together with bode
diagrams of the modeled system. As shown in Fig. 6 the
perfect data fit validate the converter ac small signal model.
A graphic Bode plot and pole-zero map comparison is made
in Fig. 7 for the converter operating in Zeta mode and in Fig.
8 for operation in SEPIC mode. The pole-zero map shifts to
the left when considering the non-ideal converter parameters,
turning the current plant more damped as confirmed in the
bode diagram.
IV. C URRENT C ONTROLLER IMPLEMENTATION
A closed loop control is needed to drive power from one
source to another. The diagram in Fig. 9 show the block
diagram for the current control loop and delimits the analog
and digital signals. The proportional integral controller is
chosen to obtain a zero error to step reference signal.
To interface the analog signal from the current sensor with
the ADC module, an auxiliary circuit is required. This circuit
consists of an MSB low pass filter [4] at 5 kHz, following
 Fig. 8. Comparisons between ideal converter model and non-ideal converter
model operating in SEPIC Mode

Fig. 5. Setup used to validate the dynamics model with losses.

Fig. 9. The comparison with simulated point against the equated model

continuous up/down mode. The timer period register (TxPR)

determines the switching frequency and the maximum value
of the compare register, limiting the resolution of the PWM
module by log2 (TxPR) bits [7]. The compare register value
Fig. 6. The comparison with simulated point against the equated model
represents the duty cycle, value in a Q format chosen as the
ceiled value of the PWM resolution (Q11). The DSP clock
frequency is 150 MHz and the switching frequency is 50 kHz.
The ADC module gain for control loop and the PWM module
gain can be evaluated by the equations (16) and (17).
(212 − 1) 1 4095 ∼ 1
GADC = 12
= = (16)
3 2 3 · 4096 3

2QnP W M 211
GPWM =  = = 1.365 (17)
fDSP clock
round 2f 1500
Switching

Fig. 7. Comparisons between ideal converter model and non-ideal converter
model operating in Zeta Mode
by an inverter with offset of 1.5 V and a limiter voltage CI
(0-3V). For control design the equivalent transfer function of
the current conditioner circuit is (15).
2.408e007
CondI (s) =
s2 + 1.692e004s + 1.605e008
A. Fixed point considerations (DSP TMS320F2812)
A fixed point DSP was used to implement the digital
controller. In order to optimize his numeric performance, fixed
point arithmetic and C28x IQMath Library were studied [5].
As the ADC module has 12 bits [6], the Q format for the
ADC variables was chosen to be Q12. A symmetric PWM
waveform is obtained by configuring timer 1 to count in a
B. Proportional integral current controller design
The PI controller was designed in MATLABs toolbox for
the converter operating in Zeta Mode with the set point in
10 A, by locating the zero at 1.8 kHz and adjusting the gain
to obtain a first order response. For digital implementation,
the controller is discretized with Tustin method and sampling
frequency of two times the switching frequency. The PI con-
troller (18) obtained was designed for the converter operating
(15)
in Zeta mode.
0, 002693z − 0, 002403
CiLb,zeta (z) = (18)
z−1
The step response for the converter operating in both modes
are shown in Fig. 10. Using the same controller in SEPIC
mode shows a similar behavior and proves that the same
controller can be used to control the converter in both power
flows directions.
 Fig. 10. The comparison with simulated point against the equated model.
Fig. 11. Full featured simulation structure of the implemented converter.
Fig. 12. Simulation result for the converter switching between operation
modes
V. N UMERIC S IMULATION R ESULTS
A simulation of the circuit (see Fig. 11) with all parameters
cited above has been carried out in the software PSIM. The
simulated results shown in Fig. 12 are in accordance with the
expected step response illustrated in Fig. 10.
Fig. 13. Experimental results for the converter switching from Zeta mode to
SEPIC mode.
Fig. 14. Experimental results for the converter switching from SEPIC mode
to Zeta mode.
VI. P ROTOTYPE I MPLEMENTATION AND E XPERIMENTAL
R ESULTS
A prototype was implemented in order to validate all
theoretical study. The converter was designed to handle 500
W of nominal power. Batteries where used as voltage sources
bidirectional in current. To validate the converter operations
modes, the current reference was set to put the converter in
Zeta and in SEPIC Modes. The current in inductance Lb is
measured and the results are showed in Fig. 13 and in Fig.
14. The waveforms obtained in the laboratory agree well with
the results predicted by theoretical analysis presented in Fig.
12.
The converter exhibits a nonlinear behavior near zero cur-
rent point crossing. This phenomenon is caused by the dead
time of the drivers. To minimize this effect, the dead time
was set to a minimal value adjusted experimentally in the
laboratory.
VII. C ONCLUSION
This paper presented a completed analysis of the bidirec-
tional Zeta-Sepic DC-DC converter. A brief analysis shows
that this converter behaves in the same way as the classic Zeta
converter when power flows from source Va to source Vb and
as the SEPIC converter when power flow changes. The state-
space averaging technique was used to model the converter
dynamics and to find the steady state operation point, without
increase of modeling complexity when the conduction losses
were considered. Modeling the converter with non-idealities
brings advantages for the controller design mainly because
the dumping effect introduced by the consideration of the
converter resistances.
The experimental results obtained validate the theoretical
study previous made. The outline shown in this paper can
be used to model, control, simulate and implement almost
all DC-DC converters operating in continuous conduction
mode. This converter is a possible candidate to substitute
the conventional bidirectional buck-boost converter in some
practical applications, such as renewable power supply systems
and electric vehicles.
R EFERENCES
[1] A. Ruseler, “Bidirectional zeta-sepic dc-dc isolated converter
with active clamping and interleaving,” Master’s thesis, Federal
University of Santa Catarina, 2011. [Online]. Available:
http://www.tede.ufsc.br/teses/PEEL1428-D.pdf
[2] I. Kim, S. Paeng, J. Ahn, E. Nho, and J. Ko, “New bidirectional ZVS
PWM Sepic/Zeta DC-DC converter,” in Industrial Electronics, 2007. ISIE
2007. IEEE International Symposium on, Jun. 2007, pp. 555 –560.
[3] I.-D. Kim, Y.-H. Lee, B.-H. Min, E.-C. Nho, and J.-W. Ahn, “Design
of bidirectional PWM Sepic/Zeta DC-DC converter,” in 7th Internatonal
Conference on Power Electronics, 2007. ICPE ’07, 2007, pp. 614–619.
[4] M. Steffes, “Design methodology for MFB filters in ADC interface
applications analog & mixed-signal,” Texas Instruments, Tech. Rep.,
2006. [Online]. Available: http://www.ti.com/
[5] I. Texas Instruments, “C28x iqmath library - a virtual floating point
engine,” Texas Instruments, Tech. Rep. SPRC087, 2009. [Online].
Available: http://www.ti.com/tool/SPRC087
[6] ——, “Tms320x281x analog-to-digital converter (adc) reference guide
(rev. d),” Texas Instrument, Tech. Rep. SPRU060D, 2005. [Online].
Available: http://www.ti.com/lit/ug/spru060d/spru060d.pdf
[7] ——, “Tms320x281x dsp. event manager (ev). reference guide,”
Texas Instrument, Tech. Rep. SPRU065E, 2007. [Online]. Available:
http://www.ti.com.cn/cn/lit/ug/spru065e/spru065e.pdf