Professional Documents
Culture Documents
on
August 2000
Acknowledgements.
Sd/-
Abstract
Contents
1. INTRODUCTION
1.1. Cordless Power Controller
2. REVIEW
a. Telephone signaling systems
b. DTMF description
c. Interface to the telephone line
d. The TRIAC
3. EXPERIMENTAL PROCEDURE
a. Hardware details
b. Software details
4. CONCLUSION
5. APPENDIX
Introduction
Review
was developed in the late 1950's. The oscillator was particularly adapted to the
low and variable power available from the central office battery over the range
of the existing loops to the station set. The oscillator design the central office in
the presence of the noise from numerous sources that is always present on the
telephone circuits, but not so high as to exceed crosstalk. The concept of a fourby-four frequency code resulted in a relatively simple mechanical system at the
station set.
1. The dialing and supervisory capabilities of the system over typical and
limiting plant conditions. A sample of adequate size and diversity including
various gauges of loaded and non-loaded cable and wire and exposure to
various environmental conditions was needed.
2. The effectiveness of the protection provided in the system against false
signals. It was anticipated that signal like impulses would be generated by
speech, line noise, test supervisory tones that exist on telephone circuits.
3. The reliability, stability and maintenance requirements of the equipment and
its components under typical conditions.
4. Customer usage characteristics such ass dialing speed, learning rate, signal
pulse duration, error types and rates.
5. The results of the second set of trials led to the conclusion that a practical
new dialing scheme could be developed based on the technical concept of
the system and components used in the technical trials.
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1.
The signals must not contain an out of band component such as DC step.
2.
The first of these two requirements the need for the signals to be wholly
contained within the voice frequency band also brings with it the
problem of vulnerability to talk off. The second reintroduced the
uncharted domain of active devices.
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Guard action of the type that has been discussed requires that only one of
the two tones making up a valid signal be admitted to each limiter. To derive the
fill benefit of limiter guard action, as much of the speech spectrum as possible
should be given access to the limiter. A band pass filter preceding the limiter to
separate two components of a valid signal, would defeat this objective, since it
would permit competition for limiter capture between a signal frequency and
only portion of the speech burst lying in the same band. However a filter
attenuating merely the other group of frequencies allows competition with the
whole speech spectrum except with the attenuated band.
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GROUP A
GROUP B
(Hz)
(Hz)
697
1209
770
1336
852
1477
941
1633
All frequencies are essentially within the 700-1700 Hz range, and the
spacing is adequate to accommodate the recognition bands. The 16 pairs of
frequencies representing valid signals avoid low order ratios.
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A valid digit is defined as one of the low frequency group together with
one tone out of the high frequency group. In total, there are sixteen
combinations possible but we use only the digits 0-9. The maximum dialing
speed with a DTMF system is typically 7 digits per second, i.e., a tone burst of
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70 msec. With the pulse dialing system, the speed varies between 1.1 to 0.56
digits per second. The DTMF is therefore ten times faster. The major application
for DTMF is low speed data transfer.
1209 Hz
1336 Hz
1477 Hz
1633 Hz
697 Hz
770 Hz
852 Hz
941 Hz
Two tunable oscillators, one for the low frequency group and one for the
high frequency group can be used to generate DTMF tones as shown in the
figure above.
However, due to accurate frequency demand, ICs were put together with
a crystal oscillator and two synthesizers which generate the DTMF tone
digitally. Although, it cannot synthesize the exact DTMF frequency, an
inexpensive crystal has turned out to be the most popular type of DTMF
synthesizer clock that generates a frequency of 3579545Hz and can be divided
down to the DTMF frequencies with only a small error.
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The DTMF tones generated by the DTMF dialer must applied to the
telephone line respecting the AAC and DC requirements of the PTT. Most
bipolar DTMF dialers incorporate an on chip line interface. This approach
results in very simple and efficient circuit designs. The DTMF dialer is powered
from the speech circuit peripheral supply point. The DTMF tones are transmitted
to the telephone line via the speech circuit line interface. The mute signal
generated by the DTMF dialer, controls the speech circuit and determines when
to transmit speech and DTMF signals. The switch over from speech mode to
dialing mode can be realized without noticeable audible clicks.
If the speech circuit passes part of the signals on its DTMF input to the
earpiece output, a confidence tone will be introduced. This approach is called
the common line interface architecture because both the speech and dialing parts
of telephone are connected to the by the same interface.
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Either positive or negative gate signals may be used to trigger the triac
into conduction. This characteristic helps to simplify circuit design. The load or
main current terminals are designated as MT1 and MT2. Usually, MT1 is taken
as the point of reference for voltage and current measurements made and the
gate terminal. Maximum current and offset voltage ratings are of the order of 40
A and 800 V, respectively.
The triac can be switched into conduction in either the first or third
quadrant by excessive voltage across the MT2- MT1 terminals. Triac control
circuits are designed so that the rated the rated minimum blocking voltage
(VDRM) is never exceeded. Transients on the ac power line can cause the off-
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state voltage to rise above voltage break over point. When this happens, leakage
current through the reverse biased junction avalanches, and the triac is latched
into conduction.
A triac can be switched into conduction by a sharp increase of the offstate voltage. The symbol dV/dt stands for the rate of change of voltage with
respect to time. The peak off-state voltage does not have to exceed the voltage
break over point for this mode of switching to occur. Generally referred to as the
critical or static dV/dt, the rapid increase in voltage across the triac results in a
charging current through the internal capacitance of the device. When this
charging current equals or exceeds the gate trigger current (Igt), the triac is
triggered into conduction. The resulting current in a capacitor is a function of the
capacitance and the rate of change of voltage across the capacitor. This is given
by the equation:
I=C * dV/dt
Where,
I is the charging current in amperes,
C is the capacitance in farads,
dV is the change in volts,
dt is the time (in seconds) associated with the voltage change.
Typical static dV/dt ratings for triacs range from about 10 V/secs for
low power devices to about 100V/microsecs for high power devices.
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protect the triac against voltage transients, which exceed the break over voltage
level. The design of snubber circuits must take into account peak line voltages,
load characteristics, and time constant of the RC network must be small when
compared to the ac load conduction time.
Most triacs possess a gate control turn on time (tg) of the order of 1.5 to 5
microseconds. The triac should be triggered with a fast-rising current waveform
for reliable turn on characteristics. Care should be taken to avoid exceeding the
gate power dissipation limits of the device being used. Unlike the SCR, the triac
is turned on twice each ac cycle. Thus the triac must be turned off promptly at the
end of each cycle so that it can be turned on in the opposite direction for the next
half cycle. The successive turn on and turn off is referred to as commutation.
Inductive loads such as motors and transformers pose a difficult task for
triac commutation. The current in an inductive load is lagging the supplied
voltage. This lagging load current holds the triac in a state of conduction past the
end of the ac half cycle. When the load current drops below the holding current,
the triac switches to the off-state conditions. By this time the voltage associated
with the next half-cycle has risen to an appreciable level. This permits a sudden
increase in the voltage across the triac and this may prematurely trigger
conduction during the next half-cycle. The maximum rate of rise of an off-state
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voltage that will not trigger the triac into conduction is known as the
commutating dV/dt rating. This is usually expressed in volts per microsecond.
More critical than static dV/dt limitations, the commutating dV/dt ratings for
triacs range from 1 to 5V/microsec. Snubber circuit can be used to eliminate this
problem.
As with other thyristors, the operating characteristics of the triac may vary
considerably with changing temperature. All temperature related specifications
are usually referenced to case temperature. Gate trigger current and gate trigger
voltage both vary inversely with case temperature-higher temperature requires
lower amplitude gate signals. The minimum dc holding current also varies
inversely with case temperature. Dc holding current is also related to the voltage
polarity across the main terminals. i.e.; dc holding current for first quadrant may
exceed thee third quadrant dc holding current by 10 to 40 percent.
The design of triac control circuits requires that careful attention be given
to temperature characteristics concerning such operating parameters as gate
rigger signals, dc holding currents, and commutating conditions. In particular,
low temperature operating environments require higher amplitude trigger signals
for reliable operation.
2.4.1.6.Triac Specifications
and
types
of
packages.
The
MAC3030-40/MAC3030-401
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A resistor is connected to the gate circuit to limit the gate current and is
about 100 ohms.
Triac zero crossing switching circuits are used in industrial control and
related applications. Like static switching, zero crossing power switching systems
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The diac is one of the more common trigger devices in use today. Other
trigger devices used in triac gate circuits include unijunction transistors (UJTs)
and special two-transistor configurations usually fabricated as one integrated
circuit.
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Experimental procedure
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MCU card
Input card
Output card
Power supply unit
seven input lines from the input card. They are connected to port3 and are
namely,
P3.1 Hook detector
P3.2 DTMF interrupt
P3.3 ZCD interrupt
P3.4 BCD
P3.5 BCD
P3.6 BCD
P3.7 BCD
MCU card has 3 output lines (port1) and can be listed below.
P1.0 mode selector
P1.1 lamp
P1.2 firing pulses
Output p1.0 goes to a Darlington pair, which drives a relay. This relay
switches the device between two operating modes, Telephone mode and Power
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control mode. An LED indicator is also attached with this relay. P1.1 also goes
to a Darlington pair, which controls the lamp (ON/OFF). The firing pulses for the
TRIAC are output through P1.1.These pulses directly go to the optocoupler
MOC3011 through buffer. All the output lines are connected through the buffer
IC74144 in order to prevent the loading of port1.
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output. A zero crossing detector with hysterisis follows each filter output. When
each signal amplitude at the output exceeds the specified level it is transferred to
full swing logic signal. When input signals are recognized to be effective, DV
becomes high, and the correct code of the tone (DTMF) digit is transferred.
The input ac is clipped using two antiparallel diodes. This clipped signal
is fed to the 339 components (The 339 IC is a Quad comparator)
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The output of the comparator would be a square wave with period 20m
sec. we uses a pulse of width 100 sec at every 10m sec interval in order to
interrupt the microcontroller (int1). In order to generate these pulses, the square
wave is fed to IC 74123. It is a dual retriggerable monoshot. One of the
monoshots is made positive edge triggered, ie sensitive to the clock and the
other is made sensitive to the negative edge of the clock.
The value of resistors and capacitors of both of the monoshots are
designed to achieve the desired pulse width of 100 sec. Finally the outputs of
both monoshots are ORed to get the desired ZCD signal.
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29
Start
Initialization of SP
Ports, timer, Mode,
Interrupts, hook&
fan bits
Is hook
Off? ie
P3.1=1?
No
Yes
Enables int0,
Sets hook bit
Is hook
On? ie
P3.1=0?
Yes
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No
Key press
Disables all
interrupts, read
port3
Is
Modebit
Yes
Yes
Set?
No
DPTR loaded
From memory with
Address of LT2
Is
A=
Yes
@DPTR ?
Decrements R7
(Contains the no:
of digits in code)
No
Is
R7=0?
Yes
Set
Mode bit
No
C
31
DPTR incremented
and stored in memory
Mode changed to
PCM
B
Ret I
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Is
A=light
Select?
Yes
Device bulb
is selected
No
Is
A= fan
Select?
Yes
Device fan
is selected
No
Is A=
Device
Toggle?
Yes
Is
Device
bulb?
No
Is
Device
No
Yes
Complements
bulb state
Complements
Fan bit
No
fan?
Yes
E
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E
F
Is
A=(
Yes
-)
Is
Delay
step>0?
Yes
Decrement
Delay step
No
No
Is
A=(
+)
Yes
Is
Delay
step<7?
No
No
Enable all
interrupts
Ret I
34
Yes
Increment
Delay step
ZCD
Enables counter
Counting and
Counter0 interrupt
Ret I
35
Counter0
Counting reset,
counter int disabled
count loaded in R3
Complements port
for fan
Dec r3,
Is r3=0?
Yes
Ret I
36
No
Delay
Dec r2,
Is r2=0?
Return
37
Conclusion
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39
Appendix
40
Bibliography
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References:
1. The 8051 Microcontroller Architecture,
Programming & applications
Kenneth J. Ayala
Clay Laster
Sites visited:
1. http://www.acebus.com
2. http://www.motorola.com
3. http://atmel.com
4. http://icmaster.com
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